M28256
256 Kbit (32Kb x8) Parallel EEPROM
with Software Data Protection
PRELIMINARY DATA
January 1999 1/21
This is preliminaryinformationon a new productnow in developmentor undergoing evaluation.Detail s aresubject to change without notice.
AI01885
15
A0-A14
W
DQ0-DQ7
VCC
M28256
G
E
VSS
8
Figure 1. LogicDiagram
28
1
PDIP28 (BS) PLCC32 (KA)
A0-A14 Address Input
DQ0-DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
VCC Supply Voltage
VSS Ground
Table1. SignalNames
FASTACCESSTIME:
– 90ns at 5V
– 120ns at 3V
SINGLESUPPLYVOLTAGE:
–5V±10%for M28256
– 2.7V to 3.6Vfor M28256-xxW
LOWPOWER CONSUMPTION
FASTWRITE CYCLE:
– 64 BytesPageWrite Operation
– Byte or Page Write Cycle
ENHANCEDEND of WRITEDETECTION:
– Data Polling
– ToggleBit
STATUS REGISTER
HIGHRELIABILITYDOUBLE POLYSILICON,
CMOSTECHNOLOGY:
– Endurance>100,000Erase/Write Cycles
– Data Retention>10 Years
JEDEC APPROVEDBYTEWIDE PIN OUT
ADDRESS and DATALATCHEDON-CHIP
SOFTWAREDATAPROTECTION
DESCRIPTION
The M28256and M28256-Ware 32Kx8 lowpower
ParallelEEPROMfabricatedwithSTMicroelectron-
ics proprietary double polysilicon CMOS technol-
ogy.
TSOP28 (NS)
8 x13.4mm
28
1
SO28 (MS)
300 mils
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
W
A11
G
E
DQ5DQ1
DQ2 DQ3VSS DQ4
DQ6
A12
A14 VCC
AI01886
M28256
8
1
2
3
4
5
6
7
9
10
11
12
13
14 16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIPPin Connections
AI01887
A13
A8
A10
DQ4
17
A0
NC
DQ0
DQ1
DQ2
DU
DQ3
A6
A3
A2
A1
A5
A4
9
W
A9
1
A14
A11
DQ6
A7
DQ7
32
DU
VCC
M28256
A12
NC
DQ5
G
E
25
VSS
Figure 2B. LCC PinConnections
Warning: NC = Not Connected, DU = Don’t Use.
A1
A0
DQ0
A5
A2
A4
A3
A9
A11 DQ7
A8
GE
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A13
W
A12
A6
A14
VCC
A7
AI01889
M28256
28
1
22
78
14
15
21
VSS
A10
Figure 2D. TSOPPin Connections
DQ0
DQ1
A3
A0
A2
A1 A10
E
A13
DQ7
G
DQ5
VCC
DQ4
A9
W
A4
A14
A7
AI01888
M28256
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
DQ2
VSS
A6
A5
DQ6
28
27
26
25
24
23 A11
DQ3
1
A12
A8
Figure 2C. SOPin Connections
2/21
M28256
Symbol Parameter Value Unit
TAAmbient Operating Temperature (2) –40to85 °C
T
STG Storage TemperatureRange – 65 to 150 °C
VCC Supply Voltage – 0.3 to 6.5 V
VIO Input/Output Voltage – 0.3 to VCC +0.6 V
VIInput Voltage – 0.3 to 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) (3) 4000 V
Notes: 1. Except for therating ”OperatingTemperature Range”, stresses above those listed in theTable ”AbsoluteMaximum Ratings” may
cause permanent damage to the device. These are stressratings only andoperation of the device at these orany otherconditions
above those indicated in the Operating sections of this specification is notimplied.Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Depends on range.
3. 100pF through 1500Ω; MIL-STD-883C, 3015.7
Table2. Absolute MaximumRatings (1)
AI01697
ADDRESS
LATCH
A6-A14
(Page Address)
X DECODE
CONTROL LOGIC
256K ARRAY
ADDRESS
LATCH
A0-A5
Y DECODE
VPP GEN RESET
SENSE AND DATA LATCH
I/O BUFFERS
EGW
PAGE
LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
Figure 3. Block Diagram
3/21
M28256
Mode E G W DQ0 - DQ7
Read VIL VIL VIH Data Out
Write VIL VIH VIL Data In
Standby / Write Inhibit VIH X X Hi-Z
Write Inhibit X X VIH Data Out or Hi-Z
Write Inhibit X VIL X Data Out or Hi-Z
Output Disable X VIH X Hi-Z
Notes: 1. X = VIH or VIL.
Table3. OperatingModes (1)
The devices offer fast access time with low power
dissipationand requiresa 5V or 3V power supply.
The circuit has been designed to offer a flexible
microcontroller interface featuring both hardware
and software handshaking with Data Polling and
Toggle Bit and access to a status register. The
devices support a 64 byte page write operation.A
Software Data Protection (SDP) is also possible
using the standard JEDECalgorithm.
PIN DESCRIPTION
Addresses (A0-A14). The address inputs select
an 8-bit memory location during a read or write
operation.
Chip Enable (E). The chip enable input must be
lowto enableall read/writeoperations.When Chip
Enableis high, power consumptionis reduced.
Output Enable (G). The Output Enableinput con-
trols the data output buffers andis used to initiate
readoperations.
DataIn/Out(DQ0-DQ7).Datais writtento orread
fromthe memorythrough the I/O pins.
WriteEnable(W). TheWriteEnableinputcontrols
the writingof datato the memory.
OPERATIONS
Write Protection
In orderto preventdata corruptionand inadvertent
writeoperations;an internalVCC comparatorinhib-
its Write operationsif VCC is belowVWI (see Table
7andTable9).Accessto thememoryinwritemode
is allowed after a power-upas specifiedin Table 7
and Table 9.
Read
The device is accessedlike a static RAM. WhenE
and G are low with W high, the data addressedis
presented on the I/O pins. The I/O pins are high
impedancewhen either G or E is high.
Write
Write operations are initiated when both W and E
are low and G is high.The device supportsboth E
and W controlled write cycles. The Address is
latched by the falling edge of E or W which ever
occurslastand theData on the risingedge of E or
W which ever occurs first. Once initiated the write
operation is internally timed until completion and
the status of the Data Polling and the Toggle Bit
functions on DQ7 and DQ6 is controlled accord-
ingly.
Page Write
Page write allows up to 64 bytes within the same
page to be consecutivelylatched into the memory
prior to initiating a programming cycle. All bytes
must be located in a single page address, that is
A14-A6 must be the same for all bytes;if not,the
Page Write instruction is not executed. The page
writecan be initiatedby any byte write operation.
A page write is composed of successive Write
instructions which have to be sequenced with a
specific period of time between two consecutive
Write instructions, period of time which has to be
smaller than the tWHWH value (see Table 12 and
Table 13).
If this period of time exceedsthe tWHWH value, the
internalprogrammingcyclewillstart.Onceinitiated
thewrite operationis internallytimed until comple-
tion and the status of the Data Polling and the
ToggleBit functionson DQ7and DQ6 is controlled
accordingly.
DESCRIPTION(Cont’d)
4/21
M28256
Status Register
ThedevicesprovideseveralWriteoperationstatus
flags that can be used to minimizethe application
write time. These signals are available on the I/O
portbits during programming cycleonly.
Data Polling bit (DQ7). During the internal write
cycle, any attempt to read the last byte written will
produce on DQ7 the complementary value of the
previously latched bit. Once the write cycle is fin-
ished the true logic value appears on DQ7 in the
readcycle.
Toggle bit (DQ6). The devices offer another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the
first read value is ”0”) on subsequent attempts to
read any byte of the memory. When the internal
cycle is completed the toggling will stop and the
data read on DQ7-DQ0 is the addressed memory
byte.The deviceis nowaccessiblefor a newRead
or Writeoperation.
PageLoadTimerStatusbit(DQ5). Duringa Page
Write instruction, the devices expectto receivethe
stream of data with a minimum period of time
between each data byte. This period of time
(tWHWH) is defined by the on-chipPage Load timer
whichrunning/overflowstatusis availableon DQ5.
DQ5 Low indicates that the timeris running, DQ5
High indicatesthe time-outafter whichthe internal
writecycle will start.
Software Data Protection
The devices offer a software controlled write pro-
tectionfacility thatallowstheusertoinhibitallwrite
modesto the device.This can be usefulin protect-
ing the memory from inadvertentwritecyclesthat
may occur due to uncontrolledbus conditions.
Thedevicesareshippedasstandardinthe”unpro-
tected” state meaning that the memory contents
canbe changedas required by the user. After the
Software Data Protection enable algorithm is is-
sued, the device enters the ”Protect Mode” of
operationwhere no furtherwrite commands have
any effect on the memorycontents.
The devices remain in this mode until a valid
SoftwareDataProtection(SDP)disablesequence
is received whereby the device reverts to its ”un-
protected”state. TheSoftware Data Protection is
fully non-volatile and is not changed by power
on/off sequences. To enable the Software Data
Protection (SDP) the device requires the user to
write(with a Page Write addressing three specific
databytestothreespecificmemorylocations,each
locationin a different page) as per Figure 6. Simi-
larly to disable the Software Data Protection the
userhas to writespecificdata bytes intosix differ-
ent locations as per Figure 5 (with a Page Write
adressing different bytes in differentpages).
Thiscomplexseriesensuresthattheuserwillnever
enable or disable the Software Data Protection
accidentally.
To write into the devices when SDP is set, the
sequence shown in Figure 6 must be used. This
sequence provides an unlock key to enable the
write action, and at the same time SDP continues
to be set.
Anextension tothis is where SDPis requiredto be
set, and data is to be written.
Using the same sequenceas above, the data can
be written and SDP is set at the same time, giving
both these actions in the same Write cycle (tWC).
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS X X X X X
DP = Data Polling
TB = Toggle Bit
PLTS = Page Load Timer Status
Figure 4. Status Bit Assignment
5/21
M28256
AI01698B
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
SDP is set
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
WRITE Data
to
be Written in
any Address
SDP ENABLE ALGORITHM
Page
Write
Instruction
Page
Write
Instruction
WRITE
is enabled
SDP
Set SDP
not Set
Write
in Memory Write
Data
+
SDP Set
after tWC
Figure 5. SoftwareData Protection Enable Algorithmand Memory Write
AI01699B
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 80h in
Address 5555h
Unprotected
State
after
tWC (Write Cycle time)
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE 20h in
Address 5555h
Page
Write
Instruction
Figure 6. SoftwareData Protection Disable Algorithm
6/21
M28256
Input Rise and Fall Times ≤20ns
Input Pulse Voltages (M28256) 0.4V to 2.4V
Input Pulse Voltages (M28256-W) 0V toVCC –0.3V
Input and Output TimingRef. Voltages(M28256) 0.8V to 2.0V
Input and Output TimingRef. Voltages(M28256-W) 0.5 VCC
Table4. ACMeasurementConditions
AI02101B
4.5V to 5.5V Operating Voltage
2.7V to 3.6V Operating Voltage
VCC – 0.3V
0V
0.5 VCC
2.4V
0.4V
2.0V
0.8V
Figure 7. AC Testing Input Output Waveforms
AI02102B
OUT
CL= 100pF
CLincludes JIG capacitance
IOL
DEVICE
UNDER
TEST
IOH
Figure 8. AC Testing EquivalentLoad Circuit
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6 pF
C
OUT Output Capacitance VOUT =0V 12 pF
Note: 1. Sampled only,not 100% tested.
Table5. Capacitance(1) (TA=25°C, f =1 MHz)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤VIN ≤VCC 10 µA
ILO Output Leakage Current 0V ≤VIN ≤VCC 10 µA
ICC (1) Supply Current (TTL inputs) E = VIL,G=V
IL ,f=5MHz 30 mA
Supply Current (CMOS inputs) E = VIL,G=V
IL ,f=5MHz 25 mA
I
CC1 (1) Supply Current (Standby) TTL E = VIH 1mA
I
CC2 (1) Supply Current (Standby) CMOS E > VCC –0.3V 100 µA
VIL Input Low Voltage – 0.3 0.8 V
VIH Input High Voltage 2 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1mA 0.4 V
VOH Output HighVoltage IOH = –400 µA 2.4
Note: 1. All I/O’sopen circuit.
Table6. Read Mode DC Characteristicsfor M28256
(TA=0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
7/21
M28256
Symbol Parameter Min Max Unit
tPUR Time Delay to Read Operation 1 µs
tPUW Time Delay to Write Operation (once VCC ≥VWI)5ms
V
WI Write Inhibit Threshold 3.0 4.2 V
Note: 1. Sampled only,not 100% tested.
Table 7. PowerUp Timingfor M28256 (1)
(TA= 0 to 70°C or –40 to 85°C; VCC =4.5V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤VIN ≤VCC 10 µA
ILO Output Leakage Current 0V ≤VIN ≤VCC 10 µA
ICC (1) Supply Current (CMOS inputs) E=V
IL,G=V
IL, f = 5 MHz, VCC = 3.3V 15 mA
E=V
IL,G=V
IL, f = 5 MHz, VCC = 3.6V 15 mA
ICC2 (1) Supply Current (Standby) CMOS E > VCC –0.3V 20 µA
VIL Input Low Voltage – 0.3 0.6 V
VIH Input High Voltage 2 VCC + 0.5 V
VOL Output Low Voltage IOL = 2.1 mA 0.2 VCC V
VOH Output HighVoltage IOH = –400 µA 0.8 VCC V
Note: 1. All I/O’sopen circuit.
Table8. Read Mode DC Characteristicsfor M28256-W
(TA=0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
Symbol Parameter Min Max Unit
tPUR Time Delay to Read Operation 1 µs
tPUW Time Delay to Write Operation (once VCC ≥VWI)10ms
V
WI Write Inhibit Threshold 1.5 2.5 V
Note: 1. Sampled only,not 100% tested.
Table9. PowerUp Timingfor M28256-W(1)
(TA= 0 to 70°C or –40 to 85°C; VCC =2.7V to 3.6V)
8/21
M28256
Symbol Alt Parameter TestCondition M28256 Unit
-90 -12 -15 -20
min max min max min max min max
tAVQV tACC Address Valid to
Output Valid E=V
IL,G=V
IL 90 120 150 200 ns
tELQV tCE Chip Enable Low to
Output Valid G=V
IL 90 120 150 200 ns
tGLQV tOE Output EnableLow
to Output Valid E=V
IL 40 45 50 50 ns
tEHQZ (1) tDF Chip Enable High to
Output Hi-Z G=V
IL 0 40 0 45 0 50 0 50 ns
tGHQZ (1) tDF Output EnableHigh
to Output Hi-Z E=V
IL 0 40 0 45 0 50 0 50 ns
tAXQX tOH Address Transition
to Output Transition E=V
IL,G=V
IL 0000ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table10. ReadMode AC Characteristics
(TA=0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol Alt Parameter TestCondition M28256-W Unit
-12 -15 -20 -25
min max min max min max min max
tAVQV tACC Address Valid to
Output Valid E=V
IL,G=V
IL 120 150 200 250 ns
tELQV tCE Chip Enable Low to
Output Valid G=V
IL 120 150 200 250 ns
tGLQV tOE Output EnableLow
to Output Valid E=V
IL 45 70 80 100 ns
tEHQZ (1) tDF Chip Enable High to
Output Hi-Z G=V
IL 0 45 0 50 0 55 0 60 ns
tGHQZ (1) tDF Output EnableHigh
to Output Hi-Z E=V
IL 0 45 0 50 0 55 0 60 ns
tAXQX tOH Address Transition
to Output Transition E=V
IL,G=V
IL 0000ns
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table11. Read Mode AC Characteristics
(TA=0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
9/21
M28256
Symbol Alt Parameter TestCondition M28256 Unit
Min Max
tAVWL tAS Address Valid to Write Enable Low E = VIL,G=V
IH 0ns
t
AVEL tAS Address Valid to Chip Enable Low G = VIH,W=V
IL 0ns
t
ELWL tCES Chip Enable Low to Write Enable Low G = VIH 0ns
t
GHWL tOES Output Enable High to Write Enable
Low E=V
IL 0ns
t
GHEL tOES Output Enable High to Chip Enable Low W = VIL 0ns
t
WLEL tWES Write Enable Low to Chip Enable Low G = VIH 0ns
t
WLAX tAH Write Enable Low to Address Transition 50 ns
tELAX tAH Chip Enable Low to Address Transition 50 ns
tWLDV tDV Write Enable Low to Input Valid E = VIL,G=V
IH 1µs
tELDV tDV Chip Enable Low to Input Valid G = VIH,W=V
IL 1µs
tELEH tWP Chip Enable Low to Chip Enable High 50 ns
tWHEH tCEH Write Enable High to Chip Enable High 0 ns
tWHGL tOEH Write Enable High to Output Enable
Low 0ns
t
EHGL tOEH Chip Enable High to Output Enable Low 0 ns
tEHWH tWEH Chip Enable High to Write Enable High 0 ns
tWHDX tDH Write Enable High to Input Transition 0 ns
tEHDX tDH Chip Enable High to Input Transition 0 ns
tWHWL tWPH Write Enable High to Write Enable Low 100 ns
tWLWH tWP Write Enable Low to Write Enable High 50 ns
tWHWH tBLC Byte Load Repeat Cycle Time 0.15 150 µs
tWHRH tWC Write Cycle Time 5 ms
tEL,t
WL E or W Input Filter Pulse Width Note 1 10 ns
tDVWH tDS Data Valid before Write Enable High 50 ns
tDVEH tDS Data Validbefore ChipEnable High 50 ns
Note: 1. Characterized only but not testedin production.
Table12. Write Mode AC Characteristics
(TA=0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
10/21
M28256
Symbol Alt Parameter TestCondition M28256-W Unit
Min Max
tAVWL tAS Address Valid to Write Enable Low E = VIL,G=V
IH 0ns
t
AVEL tAS Address Valid to Chip Enable Low G = VIH,W=V
IL 0ns
t
ELWL tCES Chip Enable Low to Write Enable Low G = VIH 0ns
t
GHWL tOES Output Enable High to Write Enable
Low E=V
IL 0ns
t
GHEL tOES Output Enable High to Chip Enable Low W = VIL 0ns
t
WLEL tWES Write Enable Low to Chip Enable Low G = VIH 0ns
t
WLAX tAH Write Enable Low to Address Transition 70 ns
tELAX tAH Chip Enable Low to Address Transition 70 ns
tWLDV tDV Write Enable Low to Input Valid E = VIL,G=V
IH 1µs
tELDV tDV Chip Enable Low to Input Valid G = VIH,W=V
IL 1µs
tELEH tWP Chip Enable Low to Chip Enable High 100 ns
tWHEH tCEH Write Enable High to Chip Enable High 0 ns
tWHGL tOEH Write Enable High to Output Enable
Low 0ns
t
EHGL tOEH Chip Enable High to Output Enable Low 0 ns
tEHWH tWEH Chip Enable High to Write Enable High 0 ns
tWHDX tDH Write Enable High to Input Transition 0 ns
tEHDX tDH Chip Enable High to Input Transition 0 ns
tWHWL tWPH Write Enable High to Write Enable Low 100 ns
tWLWH tWP Write Enable Low to Write Enable High 100 ns
tWHWH tBLC Byte Load Repeat Cycle Time 0.2 150 µs
tWHRH tWC Write Cycle Time 5 ms
tEL,t
WL E or W Input Filter Pulse Width Note 1 10 ns
tDVWH tDS Data Valid before Write Enable High 50 ns
tDVEH tDS Data Validbefore ChipEnable High 50 ns
Note: 1. Characterized only but not testedin production.
Table13. Write Mode AC Characteristics
(TA=0 to 70°C or –40 to 85°C; VCC = 2.7V to 3.6V)
11/21
M28256
Note: WriteEnable (W) = High.
AI01700
VALID
tAVQV tAXQX
tGLQV tEHQZ
tGHQZ
DATA OUT
A0-A14
E
G
DQ0-DQ7
tELQV Hi-Z
Figure 9. ReadMode AC Waveforms
AI01701
VALID
tAVWL
A0-A14
E
G
DQ0-DQ7 DATA IN
W
tWLAX
tELWL
tGHWL
tWLDV
tWHEH
tWHGLtWLWH
tWHWL
tWHDXtDVWH
Figure 10. WriteMode AC Waveforms - Write Enable Controlled
12/21
M28256
AI01702
VALID
tAVEL
A0-A14
E
G
DQ0-DQ7 DATA IN
W
tELAX
tGHEL
tWLEL
tELDV
tEHGL
tEHDXtDVEH
tELEH
tEHWH
Figure 11. Write Mode AC Waveforms - Chip Enable Controlled
AI01703B
A0-A14
E
G
DQ0-DQ7
W
tWHWH
Addr 0
DQ5
Addr 1 Addr 2 Addr n
tWHWH
tWHRH
tWLWH
tWHWL
Byte 0 Byte 1 Byte 2 Byte n
Byte n
Figure 12. Page Write Mode AC Waveforms - Write Enable Controlled
13/21
M28256
AI01704
A0-A5
E
G
DQ0-DQ7
W
tWLWH
tDVWH
Byte 0
tWHWL
A6-A14
tWLAX
tWHWH
tWHDX
tAVEL
5555h 2AAAh 5555h
Byte 62 Byte 63AAh 55h A0h
Byte Address
Page Address
Figure 13. Software Protected Write Cycle Waveforms
Note: A6 through A14 must specify the same page address duringeach high tolow transitionof W (or E) afterthe software code has been
entered. G must be high only when W and E are both low.
AI01705
A0-A14
E
G
DQ7
W
DQ7 DQ7DQ7 DQ7DQ7
READYLAST WRITE INTERNAL WRITE SEQUENCE
Address of the last byte of the Page Write instruction
Figure 14. Data Polling WaveformSequence
14/21
M28256
AI01706
A0-A14
E
G
DQ6
W
READYLAST WRITE INTERNAL WRITE SEQUENCE
(1)
TOGGLE
DQ6 DQ6
Figure 15. Toggle Bit Waveform Sequence
Note: 1. First Toggle bit is forced to ’0’.
15/21
M28256
ORDERING INFORMATION SCHEME
Speed
90 (1) 90ns
12 120ns
15 150ns
20 200ns
25 (2) 250ns
Operating Voltage
blank 4.5V to 5.5V
W 2.7V to 3.6V
Package
BS PDIP28
KA PLCC32
MS SO28 300 mils
NS TSOP28
8 x 13.4mm
Temperature Range
1(3) 0to70°C
6 –40 to 85 °C
Option
T Tape & Reel
Packing
Example: M28256 – 15 W KA 6 T
Notes: 1. Not available for ”W” operatingvoltage.
2. Available for ”W” operating voltage only.
3. Temperature Range on request only.
Devices are shipped from the factory with the memory contentset at all ”1’s” (FFh).
Fora listofavailableoptions(Speed,Package,etc...)or forfurtherinformationon anyaspect of thisdevice,
please contactthe STMicroelectronics Sales Office nearestto you.
16/21
M28256
PDIP
A2
A1
A
L
B1 B e1
D
S
E1 E
N
1
C
α
eA
eB
D2
Symb mm inches
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 36.83 37.34 1.450 1.470
D2 33.02 – – 1.300 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.08 0.070 0.082
α0°10°0°10°
N28 28
Drawing is not to scale.
PDIP28 - 28 pin Plastic DIP, 600 mils width
17/21
M28256
PLCC
D
Ne E1 E
1N
D1
Nd
CP
B
D2/E2 e
B1
A1
A
R
0.51 (.020)
1.14 (.045)
F
A2
Symb mm inches
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 – 0.38 – 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N32 32
Nd 7 7
Ne 9 9
Drawing is not to scale.
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
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M28256
SO-b
E
N
CP
Be
A2
D
C
LA1 α
H
A
1
Symb mm inches
Typ Min Max Typ Min Max
A 2.46 2.64 0.097 0.104
A1 0.13 0.29 0.005 0.011
B 0.35 0.48 0.014 0.019
C 0.23 0.32 0.009 0.013
D 17.81 18.06 0.701 0.711
E 7.42 7.59 0.292 0.299
e 1.27 – – 0.050 – –
H 10.16 10.41 0.400 0.410
L 0.61 1.02 0.024 0.040
α0°8°0°8°
N28 28
CP 0.10 0.004
Drawing is not to scale.
SO28 - 28 lead Plastic Small Outline, 300 mils body width
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Symb mm inches
Typ Min Max Typ Min Max
A 1.25 0.049
A1 0.20 0.008
A2 0.95 1.15 0.037 0.045
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.55 - - 0.022 - -
L 0.50 0.70 0.020 0.028
α0°5°0°5°
N28 28
CP 0.10 0.004
Drawing is not to scale.
TSOP28- 28 lead Plastic Thin Small Outline, 8 x 13.4mm
TSOP-c
D1
E
78
CP
B
e
A2
A
22
D
DIE
C
LA1 α
21
28
1
20/21
M28256
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