GS66508P-E05 650V enhancement mode GaN transistor PRELIMINARY DATASHEET Features - 650V enhancement mode power switch - Ultra low FOM Island TechnologyTM die - Low inductance GaNPXTM package - Reverse current capability - Zero reverse recovery charge - Source-sense for optimal high speed design - RoHS 6 compliant Applications - On-board battery chargers - 400V DC-DC conversion - Inverters, UPS, and VFD motor drive - AC-DC power supplies (PFC & primary) - VHF small form factor power adapters - High frequency, high efficiency power conversion D top view D TP* G SS G S SS S * TP = thermal pad. TP is internally connected to the substrate and must be connected externally to the source (S) Absolute Maximum Ratings (Tcase = 25C except as noted) Parameters Operating Junction Temperature Storage Temperature Range Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Tcase=25C) (Note 1) Continuous Drain Current (Tcase=100C) Pulsed Drain Current (Tcase=25C) (Note 2) Symbol TJ TS VDS VGS IDS(cont)25 IDS(cont)100 IDpulse Value -55 to +150 -55 to +150 650 10 30 23 60 Units C C V V A A A Units (1) Saturation imposes current limit. (2) Pulse width is limited by TJ(max). Thermal Characteristics (Typical values unless otherwise noted) Parameters Symbol Value Thermal Resistance (junction to case) RJC 0.5 Thermal Resistance (junction to ambient) (Note 3) RJA 51 Maximum Soldering Temperature (MSL3 rated) TSOLD 260 C /W C (3) Device mounted on 40mm x 40mm x 1.5mm single layer epoxy PCB FR4 with 6cm2 copper area (thickness 70m) for thermal pad connection. PCB is vertical without air stream cooling. For optimized thermal designs, refer to Application Note GN005 "Thermal Analysis and PCB Design Guidelines for GaN Enhancement Mode Power Switching Transistors" . Ordering Information Part number GS66508P-E05 Package type GaNPX Preliminary - Rev 150223 Ordering code GS66508P-E05-TY Packing method Tray Pack quantity 100 (c) 2009-2015 GaN Systems Inc. This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. 1 GS66508P-E05 650V enhancement mode GaN transistor PRELIMINARY DATASHEET Electrical Characteristics (Typical values at Tcase= 25C unless otherwise noted) Parameters Drain-to-Source Breakdown Voltage Symbol Min BVDSS 650 Typ Max Units Conditions (Note 4) V Drain-to-Source On Resistance (TJ =25C) 55 m 140 m 1.6 V 2 A 400 A RDS(ON) Drain-to-Source On Resistance (TJ=150C) Gate Threshold Voltage VGS(th) Drain to Source Leakage Current (TJ=25C) IDSS Drain to Source Leakage Current (TJ=150C) VGS =0V ID=1mA VGS =7V, TJ=25C ID=9A VGS =7V, TJ=150C ID=9A VDS =VGS ID=7mA VDS=650V VGS =0V, TJ=25C VDS=650V VGS =0V, TJ=150C VGS=7V, VDS=0V TJ=25C f=1MHz, open drain Gate to Source Current IGS 40 A Gate Resistance RG 1.5 Gate Plateau Voltage Vplat 3 V VDS=400V Source-Drain Reverse Voltage VSD 2.8 V VGS=0V, TJ =25C ISD = 9A Input Capacitance CISS 200 Output Capacitance COSS 67 pF Reverse Transfer Capacitance CRSS 2.0 VDS=400V VGS=0V f=1MHz Effective Output Capacitance, Energy Related Co(er) 88 pF Co(tr) 143 pF QG(TOT) 6.5 nC Gate-to-Source Charge QGS 1.4 nC Gate-to-Drain Charge QGD 2.8 nC Reverse Recovery Charge QRR 0 nC Output Charge QOSS 57 nC (Note 5) Effective Output Capacitance, Time Related (Note 6) Total Gate Charge VGS =0V VDS=0 to 400V ID =constant VGS =0V VDS=0 to 400V VGS=0 to 7V VDS=400V VGS=0V VDS=400V (4) All parameters are specified with the substrate and thermal pad connected to the source (5) Co(er) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0V to the stated VDS (6) Co(tr) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0V to the stated VDS Preliminary - Rev 150223 (c) 2009-2015 GaN Systems Inc. This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. 2 GS66508P-E05 650V enhancement mode GaN transistor PRELIMINARY DATASHEET Package Dimensions Pads plated with ENIG immersion gold process Recommended Minimum Footprint This is a generic layout to be adapted for specific application needs. Thermal via size and layout are for reference only. For further details, see GaN Systems application note GN005 "Thermal Design Considerations for GaN Enhancement Mode Power Switching Transistors" www.gansystems.com North America Europe Asia Important Notice - Unless expressly approved in writing by an authorized representative of GaN Systems, GaN Systems components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or space applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of performance. GaN Systems hereby disclaims any or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights. GaN Systems standard terms and conditions apply. (c) 2009-2015 GaN Systems Inc. All rights reserved. Preliminary - Rev 150223 (c) 2009-2015 GaN Systems Inc. This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. 3 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: GaN Systems: GS66508P-E05-TY GS66508P-E05-MR