Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 9 1Publication Order Number:
MC100EPT21/D
MC100EPT21
3.3VDifferential LVPECL to
LVTTL Translator
The MC100EPT21 is a Differential LVPECL to LVTTL translator.
Because LVPECL (Positive ECL) levels are used only +3.3 V and
ground are required. The small outline 8−lead SOIC package makes
the EPT21 ideal for applications which require the translation of a
clock or data signal.
The VBB output allows this EPT21 to be cap coupled in either
single−ended or differential input mode. When single−ended cap
coupled, VBB output is tied to the D input and D is driven for a
non−inverting buffer, or VBB output is tied to the D input and D is
driven for an inverting buffer. When cap coupled differentially, VBB
output is connected through a resistor to each input pin. If used, the
VBB pin should be bypassed to VCC via a 0.01 F capacitor. For
additional information see AND8020. For a single−ended direct
connection use an external voltage reference source such as a resistor
divider. Do not use VBB for a single−ended direct connection or port to
another device.
•1.4 ns Typical Propagation Delay
•Maximum Frequency > 275 MHz Typical
•24 mA TTL outputs
•Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
•Open Input Default State
•Q Output Will Default LOW with Inputs Open or at GND
•The 100 Series Contains Temperature Compensation
•VBB Output
•New Differential Input Common Mode Range
Device Package Shipping†
ORDERING INFORMATION
MC100EPT21D SO−8 98 Units/Rail
MC100EPT21DR2 SO−8
MC100EPT21DT TSSOP−8 100 Units/Rail
MC100EPT21DTR2 TSSOP−8
*For additional information, see Application Note
AND8002/D
MARKING
DIAGRAMS*
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ALYW
KPT21
ALYW
KA21
2500 Tape & Reel
2500 Tape & Reel
SO−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
1
8
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MC100EPT21
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2
1
2
3
45
6
7
8
Q
GND
VCC
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
D
NCD
VBB
NC
LVTTL
LVPECL
PIN DESCRIPTION
PIN
Q
D**, D** Differential LVPECL Input Pair
FUNCTION
LVTTL Output
VCC
VBB Output Reference Voltage
Positive Supply
GND Ground
NC No Connect
** Pins will default to VCC/2 when left open.
ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 50 k
Internal Input Pullup Resistor 50 k
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 81 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC PECL Power Supply GND = 0 V 3.8 V
VIN PECL Input Voltage GND = 0 V VI VCC 0 to 3.8 V
IBB VBB Sink/Source ± 0.5 mA
TA Operating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
JA Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM 8 SOIC
8 SOIC 190
130 °C/W
°C/W
JC Thermal Resistance (Junction−to−Case) std bd 8 SOIC 41 to 44 °C/W
JA Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM 8 TSSOP
8 TSSOP 185
140 °C/W
°C/W
JC Thermal Resistance (Junction−to−Case) std bd 8 TSSOP 41 to 44 °C/W
Tsol Wave Solder < 2 to 3 sec @ 248°C 265 °C
2. Maximum Ratings are those values beyond which device damage may occur.
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PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV
VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 4) 2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 A
IIL Input LOW Current D
D −150 0.5 −150 0.5 −150 0.5 A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
3. Input parameters vary 1:1 with VCC.
4. VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The V IHCMR range is referenced to the mos t positiv e side of the
differential input signal.
TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C
Symbol Characteristic Condition Min Typ Max Unit
VOH Output HIGH Voltage IOH = −3.0 mA 2.4 V
VOL Output LOW Voltage IOL = 24 mA 0.5 V
ICCH Power Supply Current Outputs set to HIGH 5 12 20 mA
ICCL Power Supply Current Outputs set to LOW 8 18 26 mA
IOS Output Short Circuit Current −130 −80 mA
AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fmax Maximum Frequency
(See Figure 2. Fmax/JITTER) 275 350 275 350 275 350 MHz
tPLH,
tPHL Propagation Delay to
Output Differential 1200
1200 1450
1400 1800
1800 1200
1200 1450
1400 1800
1800 1300
1200 1450
1400 1900
1900 ps
tSKPP Part−to−Part Skew (Note 6) 500 500 500 ps
tJITTER Random Clock Jitter (RMS)
(See Figure 2 Fmax/JITTER) 0.2 < 1 0.2 < 1 0.2 < 1 ps
VPP Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV
tr
tfOutput Rise/Fall Times
(0.8V − 2.0V) Q, Q 330 500 900 330 500 900 330 500 900 ps
5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 to GND and CL = 20 pF to GND. Refer to FIgure 3.
6. Skews are measured between outputs under identical transitions.
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Figure 2. Fmax/Jitter
0
500
1000
1500
2000
2500
3000
0 50 100 150 200 250 300 350 400 450 500 550 600
1
2
3
4
5
6
FREQUENCY (MHz)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
VOH
VOL 0.5 V
VOUTpp (mV)
JITTEROUT ps (RMS)
É
É
Figure 3. TTL Output Loading Used For Device Evaluation
CHARACTERISTIC TEST
CL*R
L
AC TEST LOAD
GND
*CL includes
fixture
capacitance
APPLICATION
TTL RECEIVER
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Resource Reference of Application Notes
AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405 − ECL Clock Distribution Techniques
AN1406 − Designing with PECL (ECL at +5.0 V)
AN1504 − Metastability and the ECLinPS Family
AN1568 − Interfacing Between LVDS and ECL
AN1650 − Using Wire−OR Ties in ECLinPS Designs
AN1672 − The ECL Translator Guide
AND8001 − Odd Number Counters Design
AND8002 − Marking and Date Codes
AND8009 − ECLinPS Plus Spice I/O Model Kit
AND8020 − Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
MC100EPT21
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PACKAGE DIMENSIONS
SO−8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AA
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z SXS
M

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PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6

SEATING
PLANE
PIN 1 14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
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MC100EPT21/D
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