MR4A16B 1M x 16 MRAM FEATURES * * * * * * * +3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Unlimited read & write endurance Data always non-volatile for >20 years at temperature RoHS-compliant small footprint BGA and TSOP2 package All products meet MSL-3 moisture sensitivity level BENEFITS * One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs * Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR4A16B is a 16,777,216-bit magnetoresistive random access memory (MRAM) device organized as 1,048,576 words of 16 bits. The MR4A16B offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To simplify fault tolerant design, the MR4A16B includes internal single bit error correction code with 7 ECC parity bits for every 64 data bits. The MR4A16B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. RoHS The MR4A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR4A16B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C), and industrial temperature (-40 to +85 C) operating temperature options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 3 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 12 5. MECHANICAL DRAWING.......................................................................... 13 6. REVISION HISTORY...................................................................................... 15 How to Reach Us...................................................................................... .......... 16 Copyright (c) 2018 Everspin Technologies, Inc. 1 MR4A16B Rev. 11.7 3/2018 MR4A16B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[19:0] 20 UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 10 ADDRESS BUFFER 10 ROW DECODER CHIP ENABLE BUFFER E FINAL WRITE DRIVERS UPPER BYTE WRITE ENABLE LB LOWER BYTE OUTPUT BUFFER 8 8 16 BYTE ENABLE BUFFER LB SENSE AMPS 1M x 16 BIT MEMORY ARRAY UB UB 8 16 WRITE ENABLE BUFFER W COLUMN DECODER UPPER BYTE OUTPUT BUFFER 8 UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER 8 8 8 8 DQU[15:8] DQL[7:0] LOWER BYTE WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection Copyright (c) 2018 Everspin Technologies, Inc. 2 MR4A16B Rev. 11.7 3/2018 MR4A16B DEVICE PIN ASSIGNMENT Figure 1.1 Pin Diagrams for Available Packages (Top View) 1 2 3 4 5 6 LB G A0 A1 A2 NC A DQU8 UB A3 A4 E DQL0 B DQU9 DQU10 A5 A6 DQL1 DQL2 C VSS DQU11 A17 A7 DQL3 VDD D VDD DQU12 DC A16 DQL4 VSS E DQU14 DQU13 A14 A15 DQL5 DQL6 F DQU15 NC A12 A13 W DQL7 G A18 A8 A9 A10 A11 A19 H 1 2 3 4 54 53 52 51 5 6 7 50 49 48 8 9 47 46 10 11 12 13 45 44 43 42 14 15 16 17 18 19 41 40 39 38 37 36 20 21 22 35 34 33 23 32 24 25 26 27 31 30 29 28 NC A19 A0 A1 A2 A3 A4 E DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 W A5 A6 A7 A8 A9 NC NC NC 48-Pin BGA NC A18 A17 A16 A15 G UB LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 DQ9 DQ8 DC A14 A13 A12 A11 A10 NC NC NC 54-Pin TSOP2 Table 1.2 Operating Modes E1 G1 W1 LB1 UB1 Mode VDD Current DQL[7:0]2 DQU[15:8]2 H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z L H H X X Output disabled IDDR Hi-Z Hi-Z L X X H H Output disabled IDDR Hi-Z Hi-Z L L H L H Lower Byte Read IDDR DOut Hi-Z L L H H L Upper Byte Read IDDR Hi-Z DOut L L H L L Word Read IDDR DOut DOut L X L L H Lower Byte Write IDDW Din Hi-Z L X L H L Upper Byte Write IDDW Hi-Z Din L X L L L Word Write IDDW Din Din 1 H = high, L = low, X = don't care 2 Hi-Z = high impedance Copyright (c) 2018 Everspin Technologies, Inc. 3 MR4A16B Rev. 11.7 3/2018 MR4A16B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field greater than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings 1 Symbol Parameter VDD Supply voltage2 VIN Voltage on an pin 2 IOUT Output current per pin PD Package power dissipation 3 TBIAS Temperature under bias Tstg Storage Temperature TLead Lead temperature during solder (3 minute max) Hmax_write Maximum magnetic field Hmax_read Maximum magnetic field Conditions Value Unit -0.5 to 4.0 V -0.5 to VDD + 0.5 V 20 mA 0.600 W Commercial -10 to 85 C Industrial -45 to 95 C -55 to 150 C 260 C 8000 A/m During Write During Read or Standby 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. 3 Power dissipation capability depends on package characteristics and use environment. Copyright (c) 2018 Everspin Technologies, Inc. 4 MR4A16B Rev. 11.7 3/2018 MR4A16B Electrical Specifications Table 2.2 Operating Conditions Symbol VDD 1 2 3 Parameter Temp Range Min Typical Max Unit Power supply voltage 3.0 3.3 3.6 V VWI Write inhibit voltage 2.5 2.7 3.0 1 V VIH Input high voltage 2.2 - VDD + 0.3 2 V VIL Input low voltage -0.5 3 - 0.8 V TA Temperature under bias 0 - 70 C -40 - 85 C Commercial Industrial 1 There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width 10 ns) for I 20.0 mA. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width 10 ns) for I 20.0 mA. Power Up and Power Down Sequencing The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram VWI VDD BROWNOUT or POWER LOSS 2 ms STARTUP READ/WRITE INHIBITED 2 ms RECOVER NORMAL OPERATION NORMAL OPERATION READ/WRITE INHIBITED VIH VIH E W Copyright (c) 2018 Everspin Technologies, Inc. 5 MR4A16B Rev. 11.7 3/2018 MR4A16B Electrical Specifications Table 2.3 DC Characteristics Symbol Parameter Conditions Min Max Unit Ilkg(I) Input leakage current All - 1 A Ilkg(O) Output leakage current All - 1 A - 0.4 V VSS + 0.2 V 2.4 - V VDD - 0.2 - V VOL VOH Output low voltage IOL = +4 mA IOL = +100 A Output high voltage IOH = -4 mA IOH = -100 A Table 2.4 Power Supply Characteristics Symbol IDDR IDDW Parameter AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) AC active supply current - write modes1 (VDD= max) Typical Max Unit 60 68 mA 152 180 mA 9 14 mA 5 9 mA AC standby current ISB1 (VDD= max, E = VIH) no other restrictions on other inputs CMOS standby current ISB2 (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. Copyright (c) 2018 Everspin Technologies, Inc. 6 MR4A16B Rev. 11.7 3/2018 MR4A16B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance 1 Symbol CIn 1 Parameter Typical Max Unit Address input capacitance - 6 pF CIn Control input capacitance - 6 pF CI/O Input/Output capacitance - 8 pF Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3.1 Output load for all other timing parameters See Figure 3.2 f = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Parameter Logic input pulse levels Figure 3.1 Output Load Test Low and High ZD= 50 Output RL = 50 VL = 1.5 V Figure 3.2 Output Load Test All Others 3.3 V 590 Output 5 pF 435 Copyright (c) 2018 Everspin Technologies, Inc. 7 MR4A16B Rev. 11.7 3/2018 MR4A16B Timing Specifications Table 3.3 Read Cycle Timing 1 Read Mode Symbol 1 2 3 Parameter Min Max Unit 35 - ns tAVAV Read cycle time tAVQV Address access time - 35 ns tELQV Enable access time - 35 ns tGLQV Output enable access time - 15 ns tBLQV Byte enable access time - 15 ns tAXQX Output hold from address change 3 - ns tELQX Enable low to output active 3 - ns tGLQX Output enable low to output active 3 0 - ns tBLQX Byte enable low to output active 0 - ns tEHQZ Enable high to output Hi-Z 3 0 15 ns tGHQZ Output enable high to output Hi-Z 0 10 ns tBHQZ Byte high to output Hi-Z 3 0 10 ns 2 3 3 3 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Figure 3.3A Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected (EVIL, GVIL). Figure 3.3B Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) t GLQX t GHQZ t GLQV LB, UB (BYTE ENABLE) Q (DATA OUT) t BLQX Copyright (c) 2018 Everspin Technologies, Inc. t BHQZ t BLQV Data Valid 8 MR4A16B Rev. 11.7 3/2018 MR4A16B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled) 1 Symbol Unit 35 - ns tAVWL Address set-up time 0 - ns tAVWH Address valid to end of write (G high) 20 - ns tAVWH Address valid to end of write (G low) 20 - ns Write pulse width (G high) 15 - ns Write pulse width (G low) 15 - ns Data valid to end of write 10 - ns tWHDX Data hold time 0 - ns tWLQZ Write low to data Hi-Z 3 0 15 ns tWHQX Write high to output active 3 3 - ns tWHAX Write recovery time 12 - ns tWLEH tDVWH 3 Max Write cycle time 2 tWLEH tWLWH 2 Min tAVAV tWLWH 1 Parameter All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min). Figure 3.4 Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t AVWH t WHAX E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL UB, LB (BYTE ENABLED) t DVWH D (DATA IN) t WHDX DATA VALID t WLQZ Q (DATA OUT) Hi -Z Hi -Z t WHQX Copyright (c) 2018 Everspin Technologies, Inc. 9 MR4A16B Rev. 11.7 3/2018 MR4A16B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled) 1 Symbol Unit 35 - ns tAVEL Address set-up time 0 - ns tAVEH Address valid to end of write (G high) 20 - ns tAVEH Address valid to end of write (G low) 20 - ns Enable to end of write (G high) 15 - ns Enable to end of write (G low) 3 15 - ns tDVEH Data valid to end of write 10 - ns tEHDX Data hold time 0 - ns tEHAX Write recovery time 12 - ns tELEH tELWH 3 Max Write cycle time 2 tELWH 2 Min tAVAV tELEH 1 Parameter All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled) t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) UB, LB (BYTE ENABLE) t DVEH D (DATA IN) Q (DATA OUT) Copyright (c) 2018 Everspin Technologies, Inc. t EHDX Data Valid Hi-Z 10 MR4A16B Rev. 11.7 3/2018 MR4A16B Timing Specifications Table 3.6 Write Cycle Timing 3 (LB/UB Controlled) 1 Symbol Max Unit Write cycle time 2 35 - ns tAVBL Address set-up time 0 - ns tAVBH Address valid to end of write (G high) 20 - ns tAVBH Address valid to end of write (G low) 20 - ns Write pulse width (G high) 15 - ns Write pulse width (G low) 15 - ns tDVBH Data valid to end of write 10 - ns tBHDX Data hold time 0 - ns tBHAX Write recovery time 12 - ns tBLWH tBLEH tBLWH 2 Min tAVAV tBLEH 1 Parameter All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled) t AVAV A (ADDRESS) t AVEH t BHAX E (CHIP ENABLE) W (WRITE ENABLE) t AVBL t BLEH t BLWH UB, LB (BYTE ENABLED) t DVBH D (DATA IN) Q (DATA OUT) t BHDX Data Valid Hi -Z Copyright (c) 2018 Everspin Technologies, Inc. Hi -Z 11 MR4A16B Rev. 11.7 3/2018 MR4A16B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 4 A 16 B C MA 35 R Carrier Speed Package Temperature Range Blank = Tray, R = Tape & Reel 35 ns MA = FBGA, YS = TSOP Blank= Commercial (0 to +70 C), C= Industrial (-40 to +85C ) Revision Data Width Type 16 = 16-bit A = Asynchronous Density 4 =16Mb Magnetoresistive RAM Table 4.1 Available Parts Grade Temp Range Package 48-BGA Commercial 0 to +70 C 54-TSOP2 48-BGA Industrial -40 to +85C 54-TSOP2 Copyright (c) 2018 Everspin Technologies, Inc. Shipping Container Trays Tape & Reel Trays Tape & Reel Order Part Number MR4A16BMA35 MR4A16BMA35R MR4A16BYS35 MR4A16BYS35R Tray MR4A16BCMA35 Tape & Reel MR4A16BCMA35R Tray MR4A16BCYS35 Tape & Reel MR4A16BCYS35R 12 MR4A16B Rev. 11.7 3/2018 MR4A16B 5. MECHANICAL DRAWING Figure 5.1 48-FBGA BOTTOM VIEW TOP VIEW (DATUM B) PIN A1 INDEX PIN A1 INDEX 6 5 4 3 2 1 A (DATUM A) B C D E F G H SEATING PLANE SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS o 0.35mm Ref Min Nominal Max A 1.19 1.27 1.35 A1 0.22 0.27 0.32 b D E D1 E1 DE SE e 0.31 0.36 0.41 Ref aaa bbb ddd eee fff Tolerance of, from and position Print Version Not To Scale 1. Dimensions in Millimeters. 10.00 BSC 2. The `e' represents the basic solder ball grid pitch. 10.00 BSC 3. `b' is measurable at the maximum solder ball diameter 5.25 BSC 3.75 BSC 0.375 BSC 0.375 BSC in a plane parallel to datum C. 4. Dimension `ddd' is measured parallel to primary datum C. 5. Primary datum C (seating plane) is defined by the crowns 0.75 BSC of the solder balls. 6. Package dimensions refer to JEDEC MO-205 Rev. G. 0.10 0.10 0.10 0.15 0.08 Copyright (c) 2018 Everspin Technologies, Inc. 13 MR4A16B Rev. 11.7 3/2018 MR4A16B 5. MECHANICAL DRAWING Figure 5.2 54-TSOP2 A2 D 54 A1 A 28 3 L1 E E1 2 c 27 1 0.20(0.008) M b e R1 R2 0.71 REF. 0.21(0.008)REF. C 0.665(0.026)REF. GAGE PLANE SEATING PLANE 0.25 mm 0.10 C 1 Ref Min Nominal A Max 1.20 A1 0.05 0.10 0.15 A2 b c D E E1 e L L1 R1 R2 1 2 3 0.95 1.00 1.05 0.30 0.35 0.45 0.12 Print Version Not To Scale 0.21 1. Dimensions in Millimeters. 2. Package dimensions refer to JEDEC MS-024 22.10 22.22 22.35 11.56 11.76 11.95 10.03 10.16 10.29 0.80 BSC 0.40 0.50 0.60 0.80 REF 0.12 - - 0.12 - 0.25 0 - 8 0.40 - - 15 REF 15 REF Copyright (c) 2018 Everspin Technologies, Inc. 14 MR4A16B Rev. 11.7 3/2018 MR4A16B 6. REVISION HISTORY Rev Date Description of Change 1 May 29, 2009 Establish Speed and Power Specifications 2 July 27, 2009 Increase BGA Package to 11 mm x 11 mm 3 Nov 26, 2009 Changed ball definition of H6 to A19 and G2 to NC in Figure 1.2. 4 Mar 10, 2010 Changed speed marking and timing specs to 35 ns part. Changed BGA package to 10 mm x 10mm 5 Apr 7, 2010 Added 54-TSOP package options. 6 Oct 7, 2011 Added AEC-Q100 Grade 1 product option. Max. magnetic field during write (Hmax_write ) increased to 8000 A/m. Revised IDDW typical from110 to 152mA, max from TBD to 180mA; IDDR max from TBD to 68mA; ISB1 typical from 11 to 9ma; ISB2 from typical 7 to 5mA. 7 Oct 28, 2011 8 August 6, 2012 9 August 27, 2013 Corrected the AEC Q-100 Grade A ordering option to be available in 54-TSOP2, not 48BGA. 9.1 Jaunary 29, 2014 Corrected minor typo in Ordering PN table. 10 April 25, 2014 AEC-Q100 removed until qualified product is available. 11 September 17, 2014 48-BGA package options moisture sensitivity level upgraded to MSL-5. 11.1 May 19, 2015 Revised Everspin contact information. 11.2 June 11, 2015 Corrected Japan Sales Office telephone number. 11.3 July 29, 2015 Minor correction to the `ddd' tolerance value for the BGA Package (Note 4.) 11.4 March 11, 2016 The BGA package moisture sensitivity level rating is changed to MSL-6 in Table 4.1. 11.5 November 22, 2016 The BGA package moisture sensitivity level rating is changed to MSL-5 in Table 4.1. 11.6 May 09, 2017 All products meet MSL-3 moisture sensitivity level 11.7 March 23, 2018 Updated the Contact Us table Added note to BGA package option products are MSL-6 only, MSL-3 qualification underway. Fixed typo on BGA drawing: Top View incorrectly labeled Bottom View. Figure 2.1 Power Up and Power Down Timing redrawn. Added 54-TSOP illustrations. Reformatted all parametric tables. Reformatted Table 4.1 Ordering Part Numbers. Copyright (c) 2018 Everspin Technologies, Inc. 15 MR4A16B Rev. 11.7 3/2018 7. HOW TO CONTACT US How to Reach Us: Everspin Technologies, Inc. Home Page: Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Copyright (c) 2018 Everspin Technologies, Inc. Filename: EST00352_MR4A16B_Datasheet_Rev11.7032318 Copyright (c) 2018 Everspin Technologies, Inc. 16 MR4A16B Rev. 11.7 3/2018