MOTOROLA _ SEMICO NDU KR NIC6801 MC6803 Microcontroller/Microprocessor (MCU/MPU) The MC6801 is an 8-bit single-chip microcontroller unit (MCU) which significantly enhances the capabilities of the M6800 Family of parts. It includes an upgraded M6800 microprocessor unit (MPU) with upward-source and object-code compatibility. Execution times of key instructions have been improved and several new instructions have been added including an unsigned multiply. The MCU can function as a monolithic microcontroller or can be expanded to a 64K byte address space. It is TTL compatible and requires one + 5-volt power supply. On-chip resources include 2048 bytes of ROM, 128 bytes of RAM, a serial communications interface {SCI}, paraliel | O, and @ three-func- tion programmable timer. The MC6803 can be considered as an MC6801 operating in modes 2 or 3. An EPROM version of the MC6801, the MC68701 microcontroller, is available for systems develop- ment. The MC68701 is pin and code compatible with the MC6801 MC6803 and can be used to emu- late the MC6801 MC6803. The MC68701 is described in a separate Advanced Information publication. @ Enhanced MC6800 Instruction Set 8-8 Multiply Instruction Serial Communications interface (SCI) @ Upward Source and Object Code Compatibility with the M6800 16-Bit Three-Function Programmable Timer Single-Chip or Expanded Operation to 64K Byte Address Space @ Bus Compatibility with the M6800 Family @ 2048 Bytes of ROM (MC6801 Only) e e . e e 128 Bytes of RAM 64 Bytes of RAM Retainable During Powerdown 29 Parallel | OQ and Two Handshake Control Lines Internal Clock Generator with Divide-by-Four Output 40 to 85 C Temperature Range This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA MICROPROCESSOR DATA 3-92MC6801/6803 FIGURE 1 M6801 MICROCOMPUTER FAMILY BLOCK DIAGRAM XTAL EXTAL ESET vec Vss TR iS wee Expanded Multiplexed Expanded Non- Multiplexed | [ Single Chip P37. A7/D7 D7 W/O P36 AG/D6 =DB) O/O P35 AS/D5 =DBO/0 P34. A4/D4 AO P33. A3/DS3 D3. P32. A2/D2 D2)/O P31 AI/DI D1 OO P30 AQ/DO 6DO OO sc2 R/IW R/W OS3 SC1 AS iOS $3 P20 P21 P22 P23 P24 P47 A15 AZ 40 P46 Ala AG 1/0 P45 ANB AS 0 P44 Al2 A4 VO P43 ANT A3 vo P42 AIO A2 0 P41 AQ Al vo P40 AB AQ vO P10 Pit P12 P13 P14 P15 P16 P17 2048 x 8 ROM {See Note) Vec NOTE: No functioning ROM in MC6803 POWER CONSIDERATIONS The average chip-junction temperature, Ty, in C can be obtained from: Ty=Ta +H{Pp 8ya} (1) where: Ta = Ambient Temperature, C Car = Package Thermal Resistance, Junction-to-Ambient, C/W PD = Pint+PeorT PINT = Iec x Vcc, Watts Chip Internal Power PportT = Port Power Dissipation, Watts User Determined For most applications PegrT<Pi_t and can be neglected. PPQRT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and Ty (if Pport is neglected) is: Pp =K {Ty + 273C) (2) Solving equations (1) and (2) for K gives: K=Pp- (Ta + 273C) + 8yarPD? (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ty MOTOROLA MICROPROCESSOR DATA 3-93MAXIMUM RATINGS MC6801/6803 i . This device contains circuitry to protect the Rating | Symbol Value Unit inputs against damage due to high static volt- Supply Voltage Vcc -0.3to +7.0 v ages or electric fields; however, it is advised that normal precautions be taken to avoid Input Voltage Vin - 0.3 to +7.0 Vv application of any voltage higher than max- Operating Temperature Range Ta TL to Ty Cc imum rated voltages to this high-impedance MC6801, MC6803 0 to 70 circuit. For proper operation it is recom- MC6801C, MC6803C -40 to +85 mended the Vin and Vout be constrained to the range Vsg = (Vin or Vout) ~ Vcc. Input Storage Temperature Range Tstg - 55 to + 150 c protection is enhanced by connecting un- used inputs to either Vpp or Vss. THERMAL CHARACTERISTICS Characteristic Symbol Value Unit | Thermal Resistance HA cw Plastic 50 | Cerdip 50 | CONTROL TIMING (Vcc - 5.0 V +5%, Vgg=0) we MC6801 MC6801-1 MC68B01 . Characteristic Symbol > > + Unit Min | Max | Min | Max | Min | Max Frequency of Operation fo 0.5 1.0 0.5 1.25 0.5 2.0 MHz Crystal Frequency IX TAL 2.0 4.0 2.0 5.0 2.0 8.0 | MHz External Oscillator Frequency Afo 2.0 40 2.0 5.0 2.0 8.0 i MHz Crystal Oscillator Start Up Time tre _ 100 _ 100 _ 100 : ms Processor Control Setup Time tPcs 200 | 170 _ 110 | : ns : DC ELECTRICAL CHARACTERISTICS (Vcc 5.0 Vde = 5%, Vgg =0, Ta- TL to TH, unless otherwise noted) | MC6801 MC6801C Characteristic Symbol MC6803 MC6803C Unit Min Max Min Max | Input High Voltage RESET, VIH Vss -4.0 Vcc Vss- 4.0 Vec ov Other Inputs Vss~ 2.0 Vcc Vsg-2.2 Vee Input Low Voltage Allinputs! Vit Vss~0.3 | Vgg-0.8 | Vgg-03 | Vgg-0.8 v Input Load Current Port 4 lin _ 0.5 _ 0.8 mA ; (Vin =O to 2.4 V)} sci 0.8 _ 1.0 j Input Leakage Current lin nA (Vin =0 to 5.25 V) NMI, IRQ1, RESET _ 2.5 5.0 i Hi-Z (Off State) Input Current | (Vin = 0.5 to 2.4 V) Ports 1,2,and3|/ {Ts| _ 10 _ 20 pA Output High Voltage VOH v : (lload- 65 pA, Voc = Min)* Port 4, SC1, SC2 Vss- 2.4 _ Vss-2.4 _ (ILoad~ ~- 100 pA, Voc = Min) Other Outputs Vssgt 2.4 _ Vss~2.4 _ i i Output Low Voltage VOL | ov (ILoad = 2.0 mA, Vec = Min} All outputs _ Vss705 _ Vss~ 0.6 | Dartington Drive Current (VQ = 1.5 V) Port 1 IOH 1.0 4.0 1.0 5.0 | mA Internal Power Dissipation PINT _ 1200 _ 1500 ' mw (Measured at Ta = TL in Steady-State Operation} | Input Capacitance Port 3, Port 4,SC1| Cin _ 12.5 _ 12.5 pF: (Vin - 0, Ta = 25C, fo = 1.0 MHz) Other Inputs _ 10 10 | Vec Standby Powerdown| VspB 4.0 5.25 4.0 5.25 | V | Powerup] Vsp 4.75 5.25 4.75 5.25 | Standby Current Powerdown| IspB | _ 6.0 _ 8.0 mA | *Negotiable to 100 pA (for further information contact the factory) MOTOROLA MICROPROCESSOR DATA 3-94MC6801/6803 PERIPHERAL PORT TIMING (Refer to Figures 2-5) MC6801 MC6801-1 MC68B01 Characteristic Symbol MCc6803 MC6803-1 MC68B03 Unit Min | Max | Min | Max | Min | Max Peripheral Data Setup Time tppsu | 200 _ 200 _ 100 _ ns Peripheral Data Hold Time tPOH 200 - 200 _ 400 - ns Detay Time, Enable Positive Transition to OS3 Negative tosp1 _ 350 _ 350 _ 250 ns Transition Deiay Time, Enable Positive Transition to OS3 Positive tosp2 _ 350 _ 350 _ 250 ns Transition Delay Time, Enable Negative Transition to Peripheral Data Valid tpwpo _ 350 _ 350 _ 250 ns Delay Time, Enabie Negative Transition to Peripheral tcMOS _ 2.0 _ 2.0 _ 2.0 MS CMOS Data Valid Input Strobe Pulse Width tpwis | 200 _ 200 _ 100 ns Input Data Hold Time tiH 50 _ 50 _ 30 _ ns Input Data Setup Time us 20 20 _ 20 _ ns FIGURE 2 DATA SETUP AND HOLD TIMES FIGURE 3 DATA SETUP AND HOLD TIMES (MPU READ) (MPU WRITE} 3 Y MPU Read \ MPU Wate E fy tpoH E tppsu PDH P10-P17 tomos P20-P24 " P40-P47 Data Valid Inputs tPDH tPDSU erie - Outer Data Valid Inputs * Data Valid Port Outputs NOTES 1. 10 k pullup resistor required for port 2 to reach 0.7 Vee. 2. Not applicable to P21 3. Port 4 cannot be pulled above Vcc * Port 3 non-latched operation (LATCH ENABLE =0) FIGURE 4 PORT 3 OUTPUT STROBE TIMING FIGURE 5 PORT 3 LATCH TIMING (MC6801 SINGLE-CHIP MODE) (MC6801 SINGLE-CHIP MODE) MPU access of Port 3* E NF VS Address (59996) x xX Bus P30-P37 Kttosp1 tosp2 inpute O83 * Access matches output strobe select (OSS =0, a read; OSS = 1, a write} ae Data Valid NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voitage of 2.0 volts, unless otherwise noted Neeeeeeeeeeeeeeeeee eee eee ee es MOTOROLA MICROPROCESSOR DATA 3-95MC6801/6803 BUS TIMING (See Notes 1 and 2) Ident. a mceso1 | Mceso1-1 | MC6sB01 Number Characteristics | Symbol MC6803 MC6803-1 MC68B03_- Unit | Min Max Min Max Min Max : 1 Cycle Time | teye 1.0 2.0 0.8 2.0 0.5 20 . us 2 Pulse Width, E Low PWet | 430 1000 | 360 1000 | 210 ; 1000! ns_ ; 3 Pulse Width, E High PWEH 450 1000 360 1000 220 1000 : ns 4 Clock Rise and Fall Time tr, tf = 25 = 25 = 20 ns 9 Address Hold Time tAH 20 = 20 10 : ons, 12 Non-Muxed Address Valid Time to E* Ltav 200 150 | 70 _ ns 17 Read Data Setup Time toSR 80 70 _, 40 'ons 18 Read Data Hold Time tDHR +0 10 410 ns, 19 [Write Data Delay Time topw | | 225, | 200; | 120. ns_, 21 Write Data Hold Time tpHw_, 20 = ;, 20 |; 10 + as 22 Muxed Address Valid Time to E Rise* tAVM 200 | 150 |; 80 _ ns 24 Muxed Address Valid Time to AS Fall* tASL 60 =. 50 , 20 _ ns 25 Muxed Address Hold Time tAHL 20 20 , 10 = ns 26 Delay time, E to AS Rise* tasD 90** 70** _;, 45"* ns 27 Pulse Width, AS High* PWaASH| 220 , i 170 _, 110 ns 28 Delay Time, AS to E Rise* tasep | 90, | 70 4 ) = ns 29 Usable Access Time* tacc 595 I t 465 i 270 i - . ons *At specified cycle time. **tasSp parameters Itsted assume external TTL clock drive with 50. ~5o duty cycle. Devices driven by an external TTL clock with 50% ~ 1% duty cycle or which use a crystal have the following tasp specifications: +00 nanoseconds minimum (1.0 MHz devices), 80 nanoseconds minimum (1.25 MHz device), 50 nanoseconds minimum (2.0 MHz devices} FIGURE 6 BUS TIMING 1 See Note 4 105 R/W, Address (Non Muxed} Note 3 Adadr/Data Read Data Muxed Muxed Addr/Data Werte Data Muxed Muxed Address Strobe (AS) 25 4 NOTES 1. Voltage tevels shown are Vi <0.5 V, Viy=2.4 V, unless otherwise specified 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified 3. Usable access time is computed by: 12+3-17+4 4. Memory devices should be enabled only during E high to avoid port 3 bus contention OOOO eee MOTOROLA MICROPROCESSOR DATA 3-96MC6801/6803 FIGURE 7 CMOS LOAD Test Point -~] T 30 pF FIGURE 8 TIMING TEST LOAD PORTS 1, 2, 3, 4 Vcc Ry 1.8 k2 Test Point MMD6150 or Equivalent MMD7000 or Equivalent C=90 pF for P30-P37, P40-P47, E, SC1, SC2 = 30 pF for P10-P17, P20-P24 R= 37 kf for P40-P47, SC1, SC2 = 24 kQ for P10-P17, P20-P24 = 24 kQ for P30-P37, E INTRODUCTION The MC6801 is an 8-bit monolithic microcomputer which can be configured to function in a wide variety of applica- tions. The facility which provides this extraordinary flexibility is its ability to be hardware programmed into eight different operating modes. The operating mode controls the con- figuration of 18 of the 40 MCU pins, available on-chip resources, memory map, location {internal or external} of in- terrupt vectors, and type of external bus. The configuration of the remaining 22 pins is not dependent on the operating mode. Twenty-nine pins are organized as three 8-bit ports and one 5-bit port. Each port consists of at least a data register and a write-only data direction register. The data direction register is used to define whether corresponding bits in the data register are configured as an input (clear) or output (set). The term port, by itself, refers to all of the hardware associated with the port. When the port is used as a data port or 1/0 port, itis controlled by the port data direction register and the programmer has direct access to the port pins using the port data register. Port pins are labeled as Pij where i identifies one of four ports and } indicates the par- ticular bit. The microprocessor unit {MPU} is an enhanced MC6800 MPU with additional capabilities and greater throughput. It is upward source and object code compatible with the MC6800. The programming model is depicted in Figure 9, where accumulator D is a concatenation of accumulators A and B. A list of new operations added to the M6800 instruc- tion set are shown in Table 1. The MC6803 can be considered an MC6801 that operates in Modes 2 and 3 only MOTOROLA MICROPROCESSOR DATA 3-97MC6801/6803 FIGURE 9 PROGRAMMING MODEL | | B o 8-Bit Accumulators A and B 0 Or 16-Bit Double Accumulator D 9 Index Register (X} oJ Stack Pointer (SP) | Program Counter (PC) 7 A 15 0 "5 x 6 sP eB PC 7 0 H N]Z]PV]C] Condition Code Register (CCR) Carry/ Borrow from MSB Overflow Zero Negative Interrupt ii = _ Half Carry (From Bit 3) OPERATING MODES The MC6801 provides eight different operating modes (0 through 7) and the MC6803 provides two operating modes (2 and 3). The operating modes are hardware selectable and determine the device memory map, the configuration of port 3, port 4, SC1, SC2, and the physical location of the inter- rupt vectors. FUNDAMENTAL MODES The eight operating modes can be grouped into three fun- damental modes which refer to the type of bus it supports: single chip, expanded non-multiplexed, and expanded multiplexed. Single-chip modes include 4 and 7, expanded non-multiplexed mode is 5, and the remaining five modes are expanded multiplexed modes. Table 2 summarizes the char- acteristics of the operating modes. MC6801 Single-Chip Modes (4, 7) In the single-chip mode, the four MCU ports are con- figured as paraltel input/output data ports, as shown in Figure 10. The MCU functions as a monolithic microcom- puter in these two modes without external address or data buses. A maximum of 29 I/O lines and two port 3 control lines are provided. Peripherals or another MCU can be inter- faced to port 3 in a loosely coupled dual processor configura- tion, as shown in Figure 11. TABLE 1 NEW INSTRUCTIONS Instruction Description ABX Unsigned addition of accumulator B to index register ADDD Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator ASLD or LSLD | Shifts the double accumulator left (towards MSB) one bit; the LSB 1s cleared and the MSB is shifted into the C bit BHS Branch if higher or same; unsigned conditional branch {same as BCC) BLO Branch if lower; unsigned conditional branch (same as BCS) BRN Branch never JSR Additional addressing mode: direct LDD Loads double accumulator from memory LSL Shifts memory or accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C bit (same as ASL) LSRD Shifts the double accumulator right (towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C bit MUL Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator PSHX Pushes the index register to stack PULX Pulls the index register from stack STD Stores the double accumulator to memory SUBD Subtracts memory from the double accumulator and leaves the difference in the double accumulator CPX Internal processing modified to permit its use with any conditional branch instruction MOTOROLA MICROPROCESSOR DATA 3-98MC6801/6803 In single-chip test mode (4), the RAM responds to $XX80 through $XXFF and the ROM is removed from the internal address map. A test program must first be loaded into the RAM using modes 0, 1, 2, or 6. If the MCU is reset and then programmed into mode 4, execution will begin at $XXFE:XXFF. Mode 5 can be irreversibly entered from mode 4 without asserting RESET by setting bit 5 of the port 2 data register. This mode is used primarily to test ports 3 and 4 in the single-chip and non-multiplexed modes. MC6801 Expanded Non-Multiplexed Mode (5) A modest amount of external memory space is provided in the expanded non-multiplexed mode while significant on- chip resources are retained. Port 3 functions as an 8-bit bidirectional data bus and port 4 is configured initially as an input data port. Any combination of the eight least-signifi- cant address lines may be obtained by writing to the port 4 data direction register. Stated alternatively, any combination of AO to A7 may be provided while retaining the remainder as input data lines. Internal pullup resistors pull the port 4 lines high until the port is configured. Figure 12 illustrates a typical system configuration in the expanded non-multiplexed mode. The MCU. interfaces directly with M68C0 Family parts and can access 256 bytes of external address space at $100 through $1FF. IOS provides an address decode of external memory ($100-$1FF) and can be used as a memcry-page select or chip-select line TABLE 2 SUMMARY OF MC6801/03 OPERATING MODES Commen to all Modes: Reserved Register Area Port 1 Port 2 Programmable Timer Serial Communications Interface Single Chip Mode 7 128 bytes of RAM; 2048 bytes of ROM Port 3 is a parallel |/O port with two control lines Port 4 is a parallel 1/O port S$C1 is Input Strobe 3 (1S3) $C2 is Output Strobe 3 (OS3) Expanded Non-Multiplexed Mode 5 128 bytes of RAM, 2048 bytes of ROM 256 bytes of external memory space Port 3 is an & bit data bus Port 4 is an input port/address bus SC1 is Input/Output Select (IOS) SC2 is Read/Write (R/Wi Expanded Multiplexed Modes 1, 2, 3, 6 Four memory space options (64K address space) (1) No internal RAM or ROM (Mode 3) (2) Internal RAM, no ROM {Mode 2) (3) Internal RAM and ROM (Mode 1) (4) Internal RAM, ROM with partial address bus (Mode 6) Port 3 is a multiplexed address/ data bus Port 4 is an address bus (inputs/address in Mode 6} SC1 is Address Strobe (AS) SC2 is Read/Write (R/W) Test Modes 0 and 4 Expanded Multiplexed Test Mode 0 May be used to test RAM and ROM Single Chip and Non-Multiplexed Test Mode 4 (1) May be changed to Mode 5 without going through Reset (2) May be used to test Ports 3 and 4 as 1/0 ports *The MC6803 operates only in modes 2 and 3. MOTOROLA MICROPROCESSOR DATA 3-99MC6801/6803 Jaw 19S 018 Z M40 O-18 L WOd {Oul IN WN aa 1089 1383 = Agpuels 9DA sor W1x4 Lvov (20-00) = AWLX Jaw, ug OL O-1 teas saul] SSouppy BOL bp 0g saury O.1S $01 Z Mog WH sour eg g seul Ql gs 10g | uog Logsow 14534 Agpuels JOA LOU! W1xX3 LAN lz 4d AV1LXx I ODA DDA NOILVHNDISNOD axa 1d LINW-NON G3ONVdxd Zl SYN jaw) Wg QOL IOS seul] ss S8n Sault 0-1 o-18 SSA saw 18-9 SA aa Zuo 140d Jaw, WG Ot 0-1 1Buag Sault sauiqo-ls O/18 9S Zu saulaO-ts saullO 1S Od p 0g p W0g z 0g sO est sauly saul] sau. ovig8 saul] OvI8 o/18 O18 0g | Hog | Mod saul] 0/18 ' Mog L Mog 10899 Losgow Lo8goW 13934 NW e 13534 43S34 bag AQpuels IA Agpuels 904 Aqpuelsg DOA W1x4 LOU! WAX Lu a WN = IWN = 3 Wwix}_7 4~< WWILX | ] | 35a, 39, DOA NOILVHNSISNOD YOSS3IDOd TWN dIHO-STONIS LL JUNI ~ JQOW dIHD-FIONIS Ol AYNDIA MOTOROLA MICROPROCESSOR DATA 3-100MC6801/6803 Expanded-Multiplex Modes (0, 1, 2, 3, 6) A 64K byte memory space is provided in the ex- panded-muitiplex modes. In each of the expanded-mul- tiplexed modes port 3 functions as a time multiplexed addressdata bus with address valid on the negative edge of address strobe (AS), and data valid while E is high. In modes 0 to 3, port 4 provides address lines A8 to A15. In mode 6, however, port 4 initially is configured at RESET as an input data port. The port 4 data direction register can then be changed to provide any combi- nation of address lines, A8 to A15. Stated alternatively, any subset of A8 to A15 can be provided while retaining the remaining port 4 lines as input data lines. Internal puliup resistors pull the port 4 lines high until software configures the port. In mode 0, the reset vector is external for the first two E cycles after the positive edge of RESET, and internal thereafter. In addition, the internal and external data buses are connected so there must be no memory map overlap in order to avoid potential bus conflicts. Mode 0 is used primarily to verify the ROM pattern and mon- itor the internal data bus with the automated test equip- ment. Only the MC6801 can operate in each of the ex- panded-multiplexed modes. The MC6803 operates only in modes 2 and 3. Figure 13 depicts a typical configuration for the ex- panded-multiplexed modes. Address strobe can be used to control a transparent D-type latch to capture ad- dresses A0-A7, as shown in Figure 14. This allows port 3 to function as a data bus when E is high. PROGRAMMING THE MODE The operating mode is determined at RESET by the tevels asserted on P22, P21, and P20. These levels are latched into PC2, PC1, and PCO of the program control register on the positive edge of RESET. The operating mode may be read from the port 2 data register as shown below, and programming levels and timing must be met as shown in Figure 15. A brief outline of the operating modes is shown in Table 3. Note that if diodes are used to program the mode, the diode forward volt- age drop must not exceed the VMPDD Minimum. PORT 2 DATA REGISTER i 6 5 4 3 2 | 0 pc2 | Pcl PCO | P24 | P23 P22 | P21 | p20 | $003 Circuitry to provide the programming levels is de- pendent primarily on the normal system usage of the three pins. If configured as outputs, the circuit shown in Figure 16 may be used; otherwise, three-state buffers can be used to provide isolation while programming the mode. TABLE 3 MODE SELECTION SUMMARY P22 P21 P20 Interrupt Bus Operating Mode* PC2 PCl PCO ROM RAM Vectors Mode Mode 7 H H H | | | ! Single Chip 6 H H L ! ' | mMuUXxt5. 6) | Multiplexed Partial Decode 5 H L H | i I NMUX(5.6)] Non-Multiplexed Partial Decode 4 H \ L f2) Wp \ \ Single-Chip Test 3 L H H E E E MUx'4) | Multiplexed No RAM or RON 2 L H L E \ E mMux'4) | Muluplexed RAM 1 L L H | | E MUx!4) | Multiplexed RAM and ROM 0 L L L | I (3) muxi4! Multiplexed Test Legend: NOTES | Internal (1) internal RAM is addressed at $XX80 E External MUX Multiplexed NMUX Non-Multiplexed L Logic Zero H Logic One 1,2, and 3 (2) Internal ROM is disabled (3) RESET vector is external for two cycles after RESET goes high (4) Addresses associated with ports 3 and 4 are considered external in modes QO. (5) Addresses associated with port 3 are considered external in modes 5 and 6 (6) Port 4 default is user data input; address output 1s optional by writing to port 4 data direction register *The MC6803 operates only in modes 2 and 3 MOTOROLA MICROPROCESSOR DATA 3-101MC6801/6803 FIGURE 13 EXPANDED MULTIPLEXED CONFIGURATION Voc 1 oo xta E ca L EXTAL & NMI Vcc Standby RESET indi MC6801 Port 1 MC6803 Port 3 8 Lines 8 I/O Lines Multiplexed Data/ Address } B/W Port 2 be AS 5 1/0 Lines = Port 4 Serial 1/0 8 Lines 16-Bit Timer rT Address Bus Vss Vcc XTAL Data Bus EXTAL (D0-D7) Address Bus (AQ-A15) R/W C Vcc Standby Port 1 81/0 Port 2 50 SCl Timer Dy Mm wl my a z = MC6801 MC6803 E Vss ROM RAM PIA NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only during E high time FIGURE 14 TYPICAL LATCH ARRANGEMENT GND AS Dy Q, Port 3 Address/ Data SN74LS373 (Typical) p Address: Ag-A7 Dg Qg p Data: Dg-D7 MOTOROLA MICROPROCESSOR DATA 3-102MC6801/6303 FIGURE 15 MODE PROGRAMMING TIMING See Figure 16 for Diode Arrangement VMPDD Vv 'P20, P21, P22) 7] MPL 2 Mode Latch ----~ RESET Level VMPH Min Mode Inputs (P20, P21, P22) MODE PROGRAMMING (Refer to Figure 15) Characteristic Symbol Min Max __Unit Mode Programming Input Voltage Low (for Ta=0 to 70 C} VMPL - 3.0.17, Vv Mode Programming Input Voltage High ._ VMPH 4.0 | Vv Mode Programming Diode Differential (If Diodes are Used) (for Ta ~- 0 to 70 C) | VMPpD 0.4 2 v RESET Low Pulse Width PWRsTL , 3.0 ,E Cycles Mode Programming Setup Time tmps , 2.0 _, E Cycles Mode Programming Hold Time tMPH : 0 ns RESET Rise Time=1 us 100. 0 RESET Rise Time<1 us Note: For Ta= 40 to 85C, Maximum Vpyyp_L=1.7, and Minimum Vypopp - 0.4 FIGURE 16 TYPICAL MODE PROGRAMMING CIRCUIT Vcc R2 $ Rie Ri ng s 6 RESET > RESET 8 P2O~e P20 (PCO! 9 P21~ P21 (PC 10 P22we P22 1PC2i I] | Mode NOTES: Controi MC6801 1. Mode 7 as shown Switches MC6803 . R2+C~ Reset time constant 2 3. Ry = 10 k (typical!) 4. D=1N914, IN4001 in the 0 to 70C range D Oo D D-1N270, MBD201 in the ~- 40 to 85 C range 5. Diode V should not exceed Viappp min. HH MEMORY MAPS The M6801 Family can provide up to 64K byte address space depending on the operating mode. A memory map for each operating mode is shown in Figure 17. The first 32 locations of each map are reserved for the internal register area, as shown in Table 4, with excep- tions as indicated. MOTOROLA MICROPROCESSOR DATA 3-103MC680 1/6803 FIGURE 17 MC6801/03 MEMORY MAPS (Sheet 1 of 3) MC6801 Multiplexed- Test Mode Mode 0 $0000!1) % YH Internal Registers $001F Li External Memory Space $0080 Internal RAM SOQOF F External Memory Space $F800 Y Yj Internal ROM $FFEF(2) U1 Internal Interrupt Vectors!2) $FFFO NOTES: 1) Excludes the following addresses which may be used externally: $04, $05, $06, $07, and $OF 2} Addresses $FFFE and $FFFF are considered external if accessed within two cycles after a positive edge of RESET and internal at all other times 3 After two MPU cycles, there must be no over lapping of internal and external memory spaces to avoid driving the data bus with more than one device. 4) This mode is the only mode which may be used to examine the interrupt vectors in internal ROM using an external RESET vector MC6801 Mode Multiplexed/ RAM and ROM $0000!1) 77. II Mf, J Internal Reaisters $001F External Memory Space $0080 7 es y Internal RAM $O0FF External Memory Space $F800 OL hb GG Internal ROM $FFEF G4 External Interrupt Vectors $FFFF NOTES 1) Excludes the following addresses which may be used externally: $04, $05, $06, $07, and SOF 2) Internal ROM addresses $FFFO to $FFFF are not usable MOTOROLA MICROPROCESSOR DATA 3-104MC6801/6803 AAXX$ O1 OBXXS Ie Jeadde jm Wyy IeWalU] (b WVU jewalul aposap 0} 89109] ,UOP,, SE Pa}eai} ie Gi O} BY SASSAIppYy (fe jaysibas eyep Z od ayy JO 11g Od ayl Oyul aud e BuyuM Aq [4994 asse oO} Bul -ABY INOYIIM G apo 0} paBueyo aq Aew py apoyy (7 PIIGeSIP SI WOY [Bua oY) (L S31LON Su0}OaA Idnayul resus 4AAXXE Wve [eur O8XX$ (cL) Fiaesnun) 41008 sraisiBay |2usayu] { 0000$ isa, diyd-ajbuig apoy LOBSD WW AOS PUR "40S O08 GOS POS Aj/BUJalxa pasn aq Aew YyoiyM sassaippe Buimaljoy ay) sapn|ox3 ({ S3LON 4dd4$ S10}98A IdNU9}U} [EUI9)XZ 04458 aoeds Alowayy [PUsa)Xy , 4L00$ suaisiBay |euayul { Wy ,)0000$ WOY 39 W8 ON/paxaidiyinyy apow cOBIOW LOB9o |W. Jos Pue *7$ 908 GOS POS -AjjeUsAxa pasn aq ABW YoIUM Sassaippe Buimoy(o} ay) sapnjaxz (1 SALON { 4444s SIOLDBA 1ONAIU| [BUIS]XJ 04448 aoeds Aioway |2U13a] x4 44008 Wy fewary| Ys 0800s aseds Aloway jeuiaxg 4100$ siaysiBay jeusayu| (1 )O000$ WY /paxaidninyy apow c0R99W LOB9OW ( 49 7 3884S) SdVW ABOWAW 0/L0890IN ZI UND! MOTOROLA MICROPROCESSOR DATA 3-105MC680 1/6803 SJOJOIA ONAL] |PUIALU| 7 dads WOy leweaqu 00845 ajqesnun Oy 4400$ WY [eusaiu] J 0800 aigesnun 4100$ siaysiBay |ewa}yj { o000$ diy ajbuis apow LOSSOW JaysiBas UoNdap eyep ay) BullM Aq sindino apew jUN Sau jasse ||IM Saul] SSouppe asay) Sq ajeudoidde ay) Ul S@UO YIM Ud}}UM Uae sey p vod 10) JajsiBa uonoaip eyep ayy jnun SOSSSIPPe UIE]UOD JOU |IIM GLYY-By Seul] SSaIppY 40$ Pue 9Q0$ vos -AljeUsaIxe Pasn aq AeW yoiym sassaippe Buimoyjo} ay) sapnjoxy ( Z S3LON $1OJDBA YONUSLU] JEUISJU| YW dds WOH jewayu 0084$ aoeds AJOWaY) |PU8]X9 4400$ Wry leusaqu Mee oB00$ aoeds Alowayy jBUsa]x3 4100$ siajsiBay jeusau Ye) (, 0000S apodag jenseg /paxaldniny apow LOggD | Ja\siBaz UOoaJIP eyep ayy Buna Aq sjndyno Spew [JUN SeUO JJasse ||IM Saul] sseippe asey] sig ayeudoidde ayy ui saud YIM UaNUuM Uaaq sey p od 10) Ja}siBay UONOaIP elep ayy nun SO8SSBIPPP UIEJUOD JOU [IM / 7 O} Oly Saul] ssouppy saysibar eyep 7 vOd ay) JO 114 OD, BY) OU! aUO e Bu Ajuanb -asqns pue p apow Buisn Aq 134594 YBnoJY) BuloB ynoyn palaua aq ABW apow siy] (Zz {Sl OU) 408 Pue 90s POS :Ajjeusayxa pasn aq you Aew yoiyas sassaippe Huimoyjoy aul SapN|9xJ (| SSLON SIOJOBA JUN Uajul jeusayU] didi WOd Jeualu| 00846 aiqesnur) 4AL0$ aoeds Asowayy }ewsalx3 0010S Saf 44008 WY leuayu| 0800 aiqesnun| 77 4LOOS ssaysiBay jeusayu; { (0000 aposag (2Weg /paxaldnjnyy-UON apow Logs ( 40 1884S) SHYW AXOWAW 0/F0899W 1 JYNODIS ~~ MOTOROLA MICROPROCESSOR DATA 3-106MC6801/6803 MC6801/03 INTERRUPTS The M6801 Family supports two types of interrupt re quests: maskable and non-maskable. A non-maskable inter- rupt (NMI) is always recognized and acted upon at the com- pletion of the current instruction. Maskable interrupts are controiled by the condition code register | bit and by in- dividual enable bits. The | bit controls all maskable inter- rupts. Of the maskable interrupts, there are two types: IRQ}4 and IRQ2. The programmable timer and serial communica- tions interface use an internal |RQ2 interrupt line, as shown in Figure 1. External devices (and !S3) use [RQ1. An IRQ1 in- terrupt is serviced before |RQ2 if both are pending All |RQ2 interrupts use hardware prioritized vectors. The single SCI interrupt and three timer interrupts are serviced in a prioritized order and each is vectored to a separate loca- tion. All interrupt vector locations are shown in Table 5. The interrupt flowchart is depicted in Figure 18 and is common to every interrupt excluding reset. During interrupt servicing the program counter, index register, A accumu- lator, B accumulator, and condition code register are pushed to the stack. The | bit is set to inhibit maskable interrupts and a vector is fetched corresponding to the current highest priority interrupt. The vector is transferred to the program counter and instruction execution is resumed. Interrupt and RESET timing are illustrated in Figures 19 and 20. FUNCTIONAL PIN DESCRIPTIONS Vcc AND Vss Vcc and Vss provide power to a large portion of the MCU. The power supply should provide + 5 volts (+ 5%) to Vcc, and Vss should be tied to ground. Total power dissipation (including Vcc standby), will not exceed Pp milliwatts. Vcc STANDBY Vcc standby provides power to the standby portion ($80 through $BF) of the RAM and the STBY PWR and RAME bits of the RAM control register. Voltage requirements de- pend on whether the device is in a powerup or powerdown state. In the powerup state, the power supply should provide +5 volts {+5%) and must reach Vsp volts before RESET reaches 4.0 volts. During powerdown, Vcc standby must re- main above Vsppg (min) to sustain the standby RAM and STBY PWR bit. While in powerdown operation, the standby current will not exceed ISRB \t is typical to power both Vcc and Vcc standby from the same source during normal operation. A diode must be used between them to prevent supplying power to Vcc during powerdown operation. Vcc standby should be tied to ground in mode 3. TABLE 4 INTERNAL REGISTER AREA Register Address Port 1 Data Direction Register* * * 00 Port 2 Data Direction Register* * * 01 Port 1 Data Register 02 Port 2 Data Register 03 Port 3 Data Direction Register* * * oa* Port 4 Data Direction Register* * * 05* * Port 3 Data Register 06* Port 4 Data Register Q7** Timer Control and Status Register 08 Counter (High Byte) 09 Counter (Low Byte} cA Output Compare Register (High Byte! 0B Output Compare Register (Low Byte) aC input Capture Register (High Byte! ob Input Capture Register Low Byte) OE Port 3 Control and Status Register OF* Rate and Mode Control Register 10 Transmit/ Receive Controi and Status Register W Receive Data Register 12 Transmit Data Register 13 RAM Control Register 14 Reserved 16 1F * External addresses :r. modes C, 1, 2, 3, 5. and 6. carrot be ac cessed in mode 5 (no 10S! **External addresses in modes 0. 1, 2, and 3 ***71= Output, O= Input TABLE 5 MCU INTERRUPT VECTOR LOCATIONS MSB LSB Interrupt FFFE FEFF RESET FFFC FFFD NMI PRFA FFFB Software Interrupt (SW: FFE FFFQ ROI (or 153! FFF6 FFF? ICF {Input Capture: * FFF4 FRFF5 OCF (Output Capture) * FFF2 FFF3 TOF (Timer Overflow) * FFFO FRFFY SCI (RDRF+ ORFE+ TORE:* *{RQ2 Interrupt MOTOROLA MICROPROCESSOR DATA 3-107MC6801/6803 (34HO + 4HGHY + IHCL) dna) IDS tddd 0544 IOS IdnuayU) MOYIBAG, 4OWN{ ddd C444 4dOL idnusajuj asedwo0y indjng G444'v444 430 idnuajuy aunydey indy; 24445-9444 4 | Isanbey Idnualuy aigeysew | 64448444 1Du! \dnualu) aeMyos | g44d-v434 IMS jdnuaiuy aiqexsey YON | 4440444 IWN Jd = 101D8A Jasi6ay apog UoNIPUO? (F4HO + dUGU)edid + IYOLealL =19S 30 a VX Od AYES AUIYOeYY yOeIS q\Su} any l Ie dL LYVHOMOTS LdNYYSLNI 8b 3YNOIS ee) 44443444] 19994 Jd te 10198A ] le 1 dW1Ll 1 MOTOROLA MICROPROCESSOR DATA 3-108MC6801/6803 PUeA ION QIN way 200d G18 Od TXT XX > | QIN MM ATMO et er K x ' PANNANANANANAANNANAARANY MUM Ayr [eusalul 44444443 Qa MON 344 344d 49d ddd) | 4 XXX, KX XX XXX ) AARANAARANNNRNEARANNALET ATUVTILAMALNY a our A80 Adv c 1b te 43S3Y $dd1 Sod) Ou) >| L 2p 1 + 1h A ONIWIL LAS3Y ~ 0% SYNDIA f \ N/a peusazuy yoo g00V VoOV Gl8x LOX Gt-89d 2:0 9d 9P09 dQ apog do aunnoy idnuiay = ST asw eieq JO ISU] S414 JOIDAA ODA JUEAGA14 sng e1eq jeusayuy Sod) >| be ZOU! 4 WN SOdi | fe LOI ssesppy 4ppY BS74PPY ASW sppy APP LL Od MeN 10108/ Jovan = (Z-UldS (9-UdS (G-UldS (PUldS (E-UWdS (2- WdS (L-WldS (UldS apog dg apop do TX XX KK >> XX x XM euro XX yeusayu| eS Wal LALLA LLL LL LIS LI LU ua LH uononsisuy Ise) apAD cle LL# Ol# 6H 84 SH vH d# | 9# cH | c# FJONINOAS LdNYHALNI 6b AYNODIS MOTOROLA MICROPROCESSOR DATA 3-109MC6801/6803 XTAL AND EXTAL These two input pins interface either a crystal or TTL- compatible clock to the MCU internal clock generator. Divide-by-four circuitry is included which allows use of the inexpensive 3.58 MHz or 4.4336 MHz Color Burst TV crystals. A 20 pF capacitor should be tied from each crystal pin to ground to ensure reliable startup and op- eration. Alternatively, EXTAL may be driven by an ex- ternal TTL-compatible clock at 4fg with a duty cycle of 50% (+ 5%) with XTAL connected to ground. The internal oscillator is designed to interface with an AT- cut Quartz crystal resonator operated in parallel resonance mode in the frequency range specified for fxTAL. The crystal should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.* The MCU is compatible with most commercially available crystals. Nominal crystal parameters are shown in Figure 21. RESET This input is used to reset the internal state of the device and provide an orderly startup procedure. During powerup, RESET must be held below 0.8 volts: (1) at least tac after Vcc reaches 4.75 volts in order to provide sufficient time for the clock generator to stabilize, and (2) until Vcc standby reaches 4.75 volts. RESET must be held tow at least three E cycles if asserted during powerup opcration E (ENABLE) This is an output clock used primarily for bus synchroniza- tion. It is TTL compatible and is the slightly skewed divide- by-four result of the device input clock frequency. It will drive one Schottky TTL load and 90 pF, and all data given in cycles is referenced to this clock unless otherwise noted. NON-MASKABLE INTERRUPT (NMI) An NMI negative edge requests an MCU interrupt se- quence, but the current instruction wilt be completed before it responds to the request. The MCU will then begin an inter- rupt sequence. Finally, a vector is fetched from $FFFC and SFFFD, transferred to the program counter and instruction execution is resumed. NMi typically requires a 3.3 kQ (nominal) resistor to Vcc. There is no internal NMI pullup resistor. NMI must be held low for at least one E cycle to be recognized under all conditions. MASKABLE INTERRUPT REQUEST 1 (iRQi) IRQ1 is a level-sensitive input which can be used to re- quest an interrupt sequence. The MPU will complete the cur- rent instruction before it responds to the request. If the inter- rupt mask bit (I bit) in the condition code register is clear, the MCU will begin an interrupt sequence. A vector is fetched from $FFF8 and $FFF9, transferred to the program counter, and instruction execution is resumed. IRQ? typically requires an external 3.3 kQ (nominal) resistor to Vcc for wire-OR applications. IRQ7 has no inter- nal pullup resistor. STROBE CONTROL 1 AND 2 (SC1 AND SC2) The function of SC} and SC2 depends on the operating mode. SC1 is configured as an output in all modes except single-chip mode, whereas SC2 is always an output. SC1 and SC2 can drive one Schottky load and 90 pF. $C1 and SC2 In Single-Chip Mode In single chip mode, SC1 and SC2 are configured as an input and output, respectively, and both function as port 3 control lines. SC1 functions as [$3 and can be used to ind cate that port 3 input data is ready or output data has been accepted. Three options associated with 1S3 are controlled by port 3 control and status register and are discussed in the PORT 3 (P30-P37). If unused, [S3 can remain unconnected SC2 is configured as OS3 and can be used to strobe out put data or acknowledge input data. It is controlled by out- put strobe select (OSS) in the port 3 control and status register. The strobe is generated by a read (OSS = 0) or write (OSS = 1) to the port 3 data register. OS3 timing ts shown in Figure 4. SC1 and SC2 In Expanded Non-Multiplexed Mode In the expanded non-multiplexed mode, both SC1 and SC2 are configured as outputs. SC1 functions as input/ out- put select (TOS) and is asserted only when $0100 through SO1FF is sensed on the internal address bus. SC2 is configured as read/write and is used to control the direction of data bus transfers. An MPU read is enabled when read/write and E are high. SC1 and SC2 In Expanded-Multiplexed Mode In the expanded- multiplexed mode, both SC1 and SC2 are configured as outputs. $C1 functions as address strobe and can be used to demultiplex the eight least-significant ad- dresses and the data bus. A latch controlled by address strobe captures address on the negative edge, as shown in Figure 14. SC2 is configured as read/write and is used to controt the direction of data bus transfers. An MPU read is enabled when read/write and E are high. PORT 1 (P10-P17) Port 1 is a mode independent 8-bit |/O port with each line an input or output as defined by the port 1 data direction register. The TTL compatible three-state output buffers can drive one Schottky TTL load and 30 pF, Darlington tran- sistors, or CMOS devices using external pullup resistors. It is configured as a data input port by RESET. Unused lines can remain unconnected PORT 2 (P20-P24) PORT 2 DATA REGISTER 6 | pce | PCY | PCO P24 | P23 | P22 | P21 | p20 | $0003 Port 2 is a mode-independent, 5-bit, multi-purpose |/O port. The voltage levels present on P20, P21, and P22 on the nsing edge of RESET determine the operating mode of the MCU. The entire port is then configured as a data input port The port 2 lines can be selectively configured as data output lines by setting the appropriate bits in the port 2 data direc- tion register. The port 2 data register 1s used to move data through the port. However, if P21 is configured as an out- put, it will be tied to the timer output compare function and cannot be used to provide output from the port 2 data register. * Devices made with masks subsequent to MSG, M8D, and T5P incorporate an advanced clock with improved startup characteristics MOTOROLA MICROPROCESSOR DATA 3-110MC6801/6803 FIGURE 21 M6801 FAMILY OSCILLATOR CHARACTERISTICS (a) Nominat Recommended Crystal Parameters Nominal Crystal Parameters* 3.58 MHz 4.00 MHz 5.0 MHz 6.0 MHz 8.0 MHz Rs 60 9 502 30-50 & 30-50 2 20-40 2 Co 3.5 pF 6.5 pF 4-6 pF 4-6 pF 4-6 pF Cy 0.015 pF 0.025 pF 0.01-0.02 pF 0.01-0.02 pF 0.01-0.02 pF Q >40 K > 30 K > 20 K > 20 K >20 K *NOTE: These are representative AT-cut crystal parameters only. Crystals of other types of cut may also be used. MC6801 Ly | C R 1 Cy Ss cL CL 2* o- 3 T Jd 1 = = VW C1 = 20 pF (typical) Co Equivalent Circuit NOTE FTL-compatible oscillators may be obtained from: Motorola Component Products Attn: Data Clock Sales 2553 N. Edgington St Franklin Park, 1L 60131 Tel: 312-451-1000 Telex: 433-0067 (b) Oscillator Stabilization Time (tac) L IF 4.75 Vec / * ] 4 RESET S 0.8V k#- tA9C Oscillator Stabilization Time, tRC MOTOROLA MICROPROCESSOR DATA 3-111MC6801/6803 Port 2 can also be used to provide an interface for the serial Communications interface and the timer input edge function. These configurations are described in PROGRAM. MABLE TIMER and SERIAL COMMUNICATIONS INTER- FACE (SCI). The port 2 high-impedance TTL-compatible output buffers are capable of driving one Schottky TTL load and 30 pF, or CMOS devices using external pullup resistors PORT 3 (P30-P37} Port 3 can be configured as an I/O port, a bidirectional 8-bit data bus, or a multiplexed address/ data bus depending on the operating mode. The TTL-compatible high- impedance output buffers can drive one Schottky TTL load and 90 pF. Unused lines can remain unconnected Port 3 In Singie-Chip Mode Port 3 is an 8-bit 1/0 port in the single-chip mode, with each line configured by the port 3 data direction register There are also twa lines, IS3 and OS3, which can be used to control port 3 data transfers Three port 3 options are controlled by the port 3 control and status register and are availabie only in single-chip mode: (1) port 3 input data can be latched using IS3 as a control signal, (2) OS3 can be generated by either an MPU read or write to the port 3 data register, and (3) an IRQ1 in- terrupt can be enabled by an IS3 negative edge. Port 3 latch timing is shown in Figure & PORT 3 CONTROL AND STATUS REGISTER 7 6 5 4 3 2 1 Oo 1S3 IRQ1 x Enable 1S3 Flag OSS |Latch] xX x x Enable SOQQOF Bit 0-2 Bit 3 Not used LATCH ENABLE. This bit controls the input latch for port 3. If set, input data is latched by an IS3 negative edge. The latch is transparent after a read of the port 3 data register. LATCH ENABLE is cleared during reset OSS (Output Strobe Select). This bit determines whether OS3 will be generated by a read or write of the port 3 data register. When clear, the strobe IS generated by a read; when Set, it is generated by a write. OSS is cleared dunng reset Not used 1S3 IRQ1 ENABLE. When set, an [ROW interrupt will be enabled whenever |S3 FLAG is set; when clear, the interrupt is inhibited. This bit is cleared during reset IS3 FLAG. This read-only status bit is set by an IS3 negative edge. It is cleared by a read of the port 3 control and status register (with IS3 FLAG set) followed by a read or write to the port 3 data register or during reset Bit 4 Bit 5 Bit 6 Bit 7 Port 3 In Expanded Non-Multiplexed Mode Port 3 is configured as a bidirectional data bus (D?7-D0) in the expanded non-multiplexed mode. The direction of data transfers is controlied by read/write {SC2). Data 1s clocked by E (enable! Port 3 tn Expanded-Multiplexed Mode Port 3 is configured as a time multiplexed address {AQ0-A7) and data bus (D7-DO) in the expanded-multiplexed modes. where address strobe (AS) can be used to demu!tiplex the two buses. Port 3 1s held in a high-impedance state between valid address and data to prevent bus conflicts PORT 4 (P40-P47} Port 4 is configured as an 8-bit | O port. as address out- puts, or as data inputs depending on the operating mode Port 4 can drive one Schottky TTL load and 90 pF and ts the only port with internal pullup resistors. Unused ines can re- main unconnected Port 4 In Single-Chip Mode In single-chip mode, port 4 functions as an 8-bit | O port with each line configured by the port 4 data direction register. Internal pullup resistors allow the port to directly interface with CMOS at 9 volt levels. External pullup resistors to more than 5 volts, however, cannot be used Port 4 In Expanded Non-Multiplexed Mode Port 4 is configured from reset as an 8-bit input port. where the port 4 data direction register can be written to pro- vide any or all of eight address lines, AQ to A7, internal pullup resistors pull the lines high until the port 4 data direc- tion register is configured Port 4 In Expanded-Multiplexed Mode In all expanded- multiplexed modes except mode 6, port 4 functions as half of the address bus and provides A8 to A15 in mode 6, the port is configured from reset as an 8-bit parallel input port, where the port 4 data direction register can be written to provide any or all of upper address tines A8& to Al. Interna! pullup resistors pull the lines high until the port 4 data direction register 1s configured, where bit 0 con- trols A8 RESIDENT MEMORY The MC6801 provides 2048 bytes of on-chip ROM and 128 bytes of on-chip RAM One half of the RAM is powered through the Vcc standby pin and is maintainable during Vcc powerdown. This stand- by portion of the RAM consists of 64 bytes located from $80 through $BF Power must be supplied to Vcc standby if the internal RAM is to be used regardiess of whether standby power operation is anticipated The RAM is controlled by the RAM control register RAM CONTROL REGISTER ($14) The RAM control register includes two bits which can be used to controi RAM accesses and determine the adequacy of the standby power source during powerdown operation It is intended that RAME be cleared and STBY PWR be set as part of a powerdown procedure MOTOROLA MICROPROCESSOR DATA 3-112MC6801/6803 RAM CONTROL REGISTER 7 6 5 4 3 2 1 0 STBYJRAME| X x x x x PWR Bit 0-5 Not used. Bit 6 RAME RAM Enable. This read/write bit can Bit 7 STBY PWR be used to remove the entire RAM from the internal memory map. RAME is set (enabled) during reset provided standby power is available on the posi- tive edge of RESET. If RAME is clear, any access to a RAM address is exter- nal. If RAME is set and not in mode 3, the RAM is included in the internal map. Standby Power. This bit is a read/write status bit which, when once set, remains set as long as Vcc standby remains above Vspp (mini- mum}. As long as this bit is set follow- ing a period of standby operation, the standby power supply has adequately preserved the data in the standby RAM. If this bit is cleared during a period of standby operation, it indi- cates that Vcc standby had fallen to a level sufficiently below Vseg (mini- standby RAM is not valid. This bit can be set only by software and is not af- fected during reset. PROGRAMMABLE TIMER The programmabie timer can be used to perform input waveform measurements while independently generating an output waveform. Pulse widths can vary from several micro- seconds to many seconds. A block diagram of the timer is shown in Figure 22. COUNTER ($09:0A) The key timer element is a 16-bit free-running counter which is incremented by E tenable). It is cleared during reset and is read-only with one exception: a write to the counter ($09) will preset it to $FFF8. This feature, intended for testing, can disturb serial operations because the counter provides the SCI internal bit rate clock TOF 1s set whenever the counter contains all ones OUTPUT COMPARE REGISTER ($0B:0C) The output compare register is a 16-bit read: write register used to control an output waveform or provide an arbitrary timeout flag. It is compared with the free-running counter on each E cycle. When a match occurs, OCF is set and OLVL Is clocked to an output level register If port 2, bit 1, is con- figured as an output, OLVL will appear at P21 and the output mum) to suspect that data in the compare register and OLVL can then be changed for the next FIGURE 22 BLOCK DIAGRAM OF PROGRAMMABLE TIMER ROD MC6801/ MC6803 Internal Bus I $0D.0E Output Compare Free Running Input Capture Register 16-Bit Counter Register Output Compare Overflow Detect Edge Detect j ] Timer by t bO Q Output Control [ ICF ocr | TOF | EICI [eoci[eroifieocouve| Leve! n J Register Status Register Bit $08 Port 2 DDR TRO2 r Output Compare Pulse | Output input Level Edge Bi Bir 0 Port 2 Porn 2 MOTOROLA MICROPROCESSOR DATA 3-113MC6801/6803 compare. The function is inhibited for one cycle after a write to its high byte (SOB) to ensure a valid compare. The output compare register is set to SFFFF at RESET. INPUT CAPTURE REGISTER ($0D:0E) The input capture register is a 16-bit read-only register used to store the free-running counter when a proper in- put transition occurs as defined by IEDG. Port 2, bit 0 should be configured as an input, but the edge detect circuit always senses P20 even when configured as an output. An input capture can occur independently of ICF: the register always contains the most current value. Counter transfer is in- hibited, however, between accesses of a double byte MPU read. The input pulse width must be at least two E cycles to ensure an input capture under all conditions. TIMER CONTROL AND STATUS REGISTER ($08) The timer contro! and status register (TCSR) is an 8-bit register of which all bits are readable, while only bits 0-4 can be written. The three most-significant bits provide the timer status and indicate if @ a proper evel transition has been detected, a match has occurred between the free-running counter and the output compare register, and @ the free-running counter has overflowed Each of the three events can generate an IRQ2 interrupt and is controlled by an individual enable bit in the TCSR TIMER CONTROL AND STATUS REGISTER (TCSR) 7 6 5 4 3 2 1 0 | ICF | ocr | TOF | EICI [e0c!ero1 [ied Tove] $0008 Bit 0 OLVL Output Level. OLVL is clocked to the output level register by a successful output compare and will appear at P21 if bit 1 of the port 2 data direction register is set. It is cleared during reset. Input Edge. JEDG is cleared during reset and controls which level transi- tion will trigger a counter transfer to the input capture register: 1EDG =0 Transfer on a negative edge }EDG=1 Transfer on a positive-edge. Enable Timer Overflow Interrupt. When set, an IRQ2 interrupt is enabled for a timer overflow; when clear, the interrupt is inhibited. It ts cleared dur- Ing reset Enable Output Compare interrupt. When set, an {RQ2 interrupt is enabled for an output compare; when clear, the interrupt is inhibited. It is cleared during reset Enable input Capture interrupt. When set, an |RQ2 interrupt is enabled for an Input capture; when clear, the inter- rupt is inhibited. It is cleared during reset. Bit 1 EIDG Bit 2 ETO! Bit 3 EOCI Bit 4 EICI Bit 5 TOF Timer Overflow Flag. TOF is set when the counter contains all ones. It is cleared by reading the TCSR (with TOF set} then reading the counter high byte ($09), or during reset Output Compare Flag. OCF is set when the output compare register matches the free-running counter. It is cleared by reading the TCSR (with OCF set) and then writing to the out- put compare register (SOB or $OC), or during reset Input Capture Flag. ICF is set to in- dicate a proper ievel transition; it is cleared by reading the TCSR (with ICF set) and then the input capture register high byte (SOD), or during reset. Bit 6 OCF Bit 7 ICF SERIAL COMMUNICATIONS INTERFACE (SCI) A fult-duplex asynchronous serial communications inter- face (SCI) is provided with two data formats and a variety of rates. The SCI transmitter and receiver are functionally in- dependent, but use the same data format and bit rate. Serial data formats include standard mark/space (NRZ) and Bi- phase and both provide one start bit, eight data bits, and one stop bit. Baud and bit rate are used synonymously in the following description. WAKE-UP FEATURE In a typical serial loop multi-processor configuration, the software protocol will usually identify the addres- see(s) at the beginning of the message. In order to per- mit uninterested MPUs to ignore the remainder of the message, a wake-up feature is included whereby all fur- ther SCI receiver flag (and interrupt) processing can be inhibited until its data line goes idle. An SCi receiver is re-enabled by an idle string of eleven consecutive ones or during reset. Software must provide for the required idle string between consecutive messages and prevent it within messages. PROGRAMMABLE OPTIONS The following features of the SCI are programmabie: @ format: standard mark/space (NRZ) or Bi-phase @ clock: external or internal bit rate clock @ Baud: one of four per E clock frequency, or external clock (x8 desired baud) @ wake-up feature: enabled or disabled @ interrupt requests: enabied individually for transmitter and receiver @ clock output: internal bit rate clock enabled or disabled to P22 SERIAL COMMUNICATIONS REGISTERS The serial communications interface includes four ad- dressable registers as depicted in Figure 23. It is controlled by the rate and mode control register and the transmit/ receive Control and status register. Data is transmitted and MOTOROLA MICROPROCESSOR DATA 3-114MC6801/6803 received utilizing a write-only transmit register and a read- only receive register. The shift registers are not accessible to software. Rate and Mode Control Registers (RMCR) ($10) The rate and mode control register controls the SCI bit rate, farmat, clock source, and under certain conditions, the configuration of P22. The register consists of four write-only bits which are cleared during reset. The two teast-significant bits control the bit rate of the internal clock and the remain- ing two bits control the format and clock source RATE AND MODE CONTROL REGISTER (RMCR) 7 6 5 4 3 2 1 0 x | x | x | x | cct | cco | ssi | sso | $0010 Bit 1:Bit O SS1:SSO Speed Select. These two bits select the baud rate when using the internal clock. Four rates may be selected which are a function of the MCU input frequency. Table 6 lists bit time and rates for three selected MCU frequencies. Bit 3:Bit 2 CC1:CCO Clock Control and Format Select. These two bits control the for- mat and select the serial clock source If CC1 is set. the DDR value for P22 is forced to the complement of CCO and cannot be altered until CC1 is cleared. \f CC1 is cleared after having been set, its DDR value is unchanged. Table 7 defines the formats, clock source, and use of P22. If both CC1 and CCO are set, an external TTL-compatible clock must be connected to P22 at eight times {8X} the desired bit rate, but not greater than E, with a duty cycle of 50% (+ 10%). If CC1:CCO= 10, the internal bit rate clock is provided at P22 regardless of the values for TE or RE NOTE: The source of SCI internai bit rate clock is the timer free-running counter. An MPU write to the counter can disturb serial operations. FIGURE 23 SCI REGISTERS Bit? | Rate and Mode Contro! Register BitO | ccl | cco | $31 | sso| $10 Transmit Receive Control and Status Register a Receive Data Register L_] Port 2 | t | | (Not Addressablei Rx 1 Bit et Receive Shift Register | 3 Clock 10 Bit Rate Bit Generator + 2 , (Not Addressable! L Transmit Shift Register mL | =f Transmit Data Register MOTOROLA MICROPROCESSOR DATAMC6801/6803 Transmit/ Receive Control And Status Register (TRCSR) ($11) The transmit/receive control and status register controls the transmitter, receiver, wake-up feature, and two in- dividua! interrupts and monitors the status of serial opera- tions. Ali eight bits are readable while bits 0 to 4 are also writable. The register is initialized to $20 by RESET TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER (TRCSR) 4 0 [pore lonee]rore] RIE | RE | me | TE | wu | $0011 Bit 0 WU Wake-up on Idle Line. When set, WU enables the wake-up function; it is cleared by eleven consecutive ones or during reset. WU will not set if the line is idle. Bit 1 TE Transmit Enable. When set, P24 DDR bit is set, Cannot be changed, and wil! remain set if TE is subsequently cleared. When TE is changed from clear to set, the transmitter is con nected to P24 and a preamble of nine consecutive ones is transmitted. TE is cleared during reset. Bit 2 TIE Transmit Interrupt Enable. When set, an {RQ2 interrupt is enabled when TDRE is set; when clear, the interrupt is inhibited. TE is cleared during reset Bit 3 RE Receive Enable. When set, the P23 DDR bit ts cleared, cannot be chang- ed, and will remain clear if RE is sutse- quently cleared. While RE is set, the SCI receiver is enabled. RE is cleared during reset. Bit 4 RIE Receiver Interrupt Enable. When set, an IRQ2 interrupt is enabled when BitS TORE Bit 6 ORFE Bit 7 RDRF TABLE 6 SCI BIT TIMES AND RATES RDRF and/or ORFE is set; when clear, the interrupt is inhibited. RIE is cleared during reset Transmit Data Register Empty. TDRE is set when the transmit data register is transferred to the output serial shift register or during reset. It is cleared by reading the TRCSR (with TORE set) and then writing to the transmit data register. Additional data wilt be transmitted only if TDRE has beer cleared Overrun Framing Error. If set, ORFE in- dicates either an overrun or framing er- ror. An overrun is a new byte ready to transfer to the receiver data register with RORF stil set A receiver framing error has occurred when the byte boundaries of the bit stream are not synchronized to the bit counter. An overrun can be distinguished from a framing error by the state of RDRF. if RORF is set, then an overrun has oc- curred; otherwise a framing error has been detected. Data is not transferred to the receive data register im an over- run condition. Unframed data causing a framing error 1s transferred to the receive data register. However, subse- quent cata transfer is blocked until the framing error flag is cleared. * ORFE 1s cleared by reading the TRCSR {with ORFE set) then the receive data register, or during reset Receive Data Register Full. RORF 1s set when the input serial shift register is transferred to the receive data register. It is cleared by reading the TRCSR twith RDRF set), and then the receive data register, or during reset . 4fom 2.4576 MHz 4.0 MHz 4.9152 MHz S$S1:SS0 E 614.4 kHz 1.0 MHz 1.2288 MHz 0 0 + 16 26 s/38,400 Baud 16 4s/62,900 Baud 13.0 ws/76,800 Baud a 1 + 128 208 ws/4,800 Baud 128 ps/7812.5 Baud 104.2 ws/93,600 Baud 1 0 ~ 1024 1.67 ms/600 Baud 1.024 ms/976.6 Baud 833.3 us/1.200 Baud 1 1 = 4096 6.67 ms/150 Baud 4.096 ms/ 244.1 Baud 3.33 ms/300 Baud * External (P22) 13.0 4s/76,800 Baud 8.0 xs/ 125,000 Baud 6.5 ws/ 153,600 Baud * Using maximum clock rate TABLE 7 SC! FORMAT AND CLOCK SOURCE CONTROL cci:cco | Format | Clock | Port 2 Source Bit 2 00 Bi-Phase | Internal | Not Used 01 NRZ Internal | Not Used 10 NRZ (Internal Output 11 NRZ External Input * Devices made with mask number MSG, M8N. and TSP do not transfer unframed data to the receive data register MOTOROLA MICROPROCESSOR DATA 3-116MC6801/6803 SERIAL OPERATIONS The SCI ts initialized by writing control bytes first to the rate and mode control register and then to the transmit/ receive control and status register. When TE is set, the out- put of the transmit serial shift register is connected to P24 and serial output is initiated by transmitting a 9-bit preamble of ones. At this point one of two situations exist: 1) if the transmit data register is empty (TDRE=1), a continuous string of ones will be sent indicating an idle line, or 2) if a byte has been written to the transmit-data register (TDRE=0)}, it will be transferred to the output serial shift register (synchroniz- ed with the bit rate clock), TDRE will be set, and transmis- sion will begin. The start bit (0), eight data bits (beginning with bit 0) and a stop bit (1), will be transmitted. If TDRE is still set when the next byte transfer should occur, ones will be sent until more data is provided. !n Bi-phase format, the output toggles at the start of each bit and at half-bit time when a one is sent Receive operation is controlled by RE which configures P23 as an input and enables the receiver. SC! data formats are il- lustrated in Figure 24. INSTRUCTION SET The MC6801/03 is upward source and object code com- patible with the MC6800. Execution times of key instructions have been reduced and several new instructions have been added, including a hardware multiply. A list of new opera- tions added to the MC6800 instruction set is shown in Table 1. In addition, two new special opcodes, 4E and 5E, are pro- vided fer test purposes. These opcodes force the program counter to increment like a 16-bit counter, causing address lines used in the expanded modes to increment unti! the device is reset. These opcodes have no mnemonics The coding of the first (or onty) byte corresponding to an executable instruction is sufficient to identify the instruction and the addressing mode. The hexadecimal equivalents of the binary codes, which result from the translation of the 82 instructions in all valid modes of addressing, are shown in Table 8. There are 220 valid machine codes, 34 unassigned codes, and 2 codes reserved for test purposes PROGRAMMING MODEL A programming model for the MC6801/03 is shown in Figure 10. Accumulator A can be concatenated with ac- cumulator B and jointly referred to as accumulator D where Ais the most-significant byte. Any operation which modifies the double accumulator wiil also modify accumulator A and/or B. Other registers are defined as follows Program Counter The program counter is a 16-bit register which always points to the next instruction Stack Pointer The stack pointer is a 16-bit register which contains the address of the next available location ina pushdown/pullup (LIFOQ) queue. The stack resides in ran- dom access memory at a location defined by the program- mer Index Register The index register is a 16 bit register which can be used to store data or provide an address for the indexed mode of addressing Accumulators The MPU contains two 8-bit accumu- lators, A and B, which are used to Store operands and results from the arithmetic logic unit (ALU). They can also be con- catenated and referred to as the D (double) accumulator Condition Code Registers The condition code register indicates the results of an instruction and includes the following five condition bits: negative (N}, zera (2), overflow (V), carry/ borrow from MSB (C), and half carry from bit 3 (H). These bits are testable by the conditional branch in- structions. Bit 4 is the interrupt mask (1 Oi) and infroits all maskable interrupts when set. The two unused bits, BE and B7, are read as ones FIGURE 24 SCI DATA FORMATS Output Clock NRZ Format Bi-Phase Format Idie Start Data: 01001101 ($4D) MOTOROLA MICROPROCESSOR DATA 3-117MC6801/6803 ADDRESSING MODES Six addressing modes can be used to reference mem- ory. Asummary of addressing modes for all instructions is present in Tables 9 through 12, where execution times are provided in E cycles. Instruction execution times are summarized in Table 13. With an input frequency of 4 MHz, E cycles are equivalent to microseconds. A cycle- by-cycle description of bus activity for each instruction is provided in Table 14 and a description of selected instructions is shown in Figure 25. Immediate Addressing The operand or immediate byte(s) is contained in the following byte(s) of the in- struction where the number of bytes matches the size of the register. These are two or three byte instructions. Direct Addressing The least-significant byte of the operand address is contained in the second byte of the instruction and the most-significant byte is assumed to be $00. Direct addressing allows the user to access $00 through $FF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 256-byte area is re- served for frequently referenced data. Extended Addressing The second and third bytes of the instruction contain the absoiute address of the operand. These are three byte instructions. Indexed Addressing The unsigned offset contained in the second byte of the instruction is added with carry to the index register and used to reference memory without changing the index register. These are two byte instructions. Inherent Addressing The operand(s) are registers and no memory reference is required. These are single byte instructions. Relative Addressing Relative addressing is used only for branch instructions. If the branch condition is true, the program counter is overwritten with the sum of a signed single byte displacement in the second byte of the instruction and the current program counter. This provides a branch range of 126 to - 129 bytes from the first byte of the instruction. These are two byte in- structions. TABLE 8 CPU INSTRUCTION MAP OP__MNEM MODE ~ #{|OP MNEM MODE ~ 4/]0P MNEM MODE ~ #] OP MNEM MODE ~ #]| OP MODE - # oo 34 OES INHER) 31 6B ASL NOXD 6 2] 9C OC PK OR 5 2/0 OR 30 2 O07 NOP INHER 2 1/36 1xS A 3 146s ROL 6 2]90 JSR 5 2] A 3 3 o2 A 3600 OSHA 3 16a vec 6 219 os a 2 {oz 3000 03s 37 PSHB ce ge sts) UR 4 2]5 BG o4 LSRD 3 1 | 38 PLLX 5 1 7 6c INC 6 2] Ac SJBA NOD 4 2] D4 3 2 05 = ASLD 3 1/38 ATS 5 1]6D tST 6 2] CMPA ff 4 2108 302 06 TAP 2 1] 3A ABK 3 11 6E IMP 3 2] AZ SBCA 4 2406 3 2 07 TPA 2 1|3B RT 1 01 d6F 0 CLR OUINDKD 66 2] a3 SUBD 6 2,07 3. 2 8 INX 3 yypac PSHX a 70 NEG EXTND 6 34 Aa ANDA 4 2 [De 3 2 09 DEX 3 1/30 MUL Ww lym oe AS BTA 4 2)09 32 OA CLV 2 1)/3 wa 9 1/72 6 46 LOAA 4 2] 04 3.2 og SEV 2 1/3F sw 12 3/73 COM 6 3) 47 STAA 4 2)08 3 2 oc CLC 2 1/40 Neca 2 741 SR 6 3/48 EORA 4 2]0 4 2 oD = SEC 2 1far + % 8 Ag = ADCA 4 2]00 | 202 OE CLI 2 1faz 4 76 ROR 6 3[4a .cRAA 4 2]06 7 a4 2 OF SEI 2 1 143 COMA 2 7? ASA 6 a) AB ADDA 4 cp OF OR 4 2 10. SBA 2 + fas LSRA 2 1178 ASL 6 3] ac cPx 6 2]&6 NDxXD 4 2? 11 CBA 2 1,45 79 ROL 6 3740 ISR 6 2]e1 A a 2 12008 46 RORA 2 1 fra pec 6 3] Ae Los v 5 2 [ee 42 13 . 47 ASRA 2 1 78 . AF STS INDAO 5 27e3 & 2 148 48 ASLA 2 1f7c ine 6 3 80 SUBA Ex'ND 4a 3]a a 2 16 . 4g ROLA 2 1 10 TST 6 34781 CMPA A 4 3 YES a 2 16 TAB 2 1 aA DECA 2 7E IMP 3 3 B2 SBCA a 3 J &6 4 2 7 TBA 2 1/)4B 7 CLR EXTND 6 3/83 SUBD 6 3fe 42 ee vy 4C INCA 2. 14780 SUBA IMMED 2 2784 ANDA 4 3 ]e8 4 2 19 DAA INHER 2 1 f4D TSTA 2 1/81 cMPA 2 2]685 Bita a 3 /e9 a2 1A * ae T Be S#CA 2 2 | B6 LDAA 4 3] t4 a 2 1B ABA INHER 2 1 7 4F CLRA 2 1/83 suBD 4 3]87 STaAA a 3 fe a Zz 1c e 50 NEGB 2 1 [84 ANDA 2 288 coRA a 3fec 5 2 ID Boe 8 -BITA 2 24/689 aApca 4 3]eD 5 2 1E oe 5208 86 LOAA 2 2/84 oRAa 4 3 /ke v 5 2 TF . 53 COMB 2 1 7 1-3 ADDA 4 3 7 EF INDXD 5 z 20 BRA REL 3 2]5a USRB 2 1/88 EcORA 2 2] 8c cPx 6 3 ]/FC SUBB EXTND 4 3 71 BRN 3 2]55 88 ADCA 2 2/80 sR 6 3 ]F) cMPB Og 4 3 227. BHI 3 2756 RORB 2 1 [8A ORAA 2 2)8 Ds Yv 5 3 ]F2 seca 4 3 23 BLS a 2757 asra 2? 1 [88 AoDA 2 2478F STS EXTIND 5 3]F3 adDD 6 3 24 BC a 2458 45.B 2 1 (8c cPx IMMED 4 3]CO SUBB IMMED 2 2]F4 ANDB 4 3 25 BCS 3. 2 ]59 ROB 2 1/80 BSR REL 6 2,c1 cMpB 2 2 /F5 BIB 4 3 26 BNE 3. 2454 vece 2 1/8 LDS IMMED 3 3)C2. sBCcB 2 2 /Fe x Das 4 3 27 BEA 3. 24/58 6 BF oe C3. ADOD 4 357 sTaB 43 28 BVC 3 2 [5c NCB 2 1190 SUBA DIR 3. 2]ca aNoB 2 24-8 EORB 4 3 79 -BVS 3. 2/90 TStB 2 1/91 cmPA 3. 2)cs pte z 249 ance 4 3 2A BPL 3 2 PSE T Vv 97 SBCA a 2 4c LOAB 2 2, FA ORAB 4 3 28 BMI 3. 2 [5F CLRB INHER 21 JB. SUBD 5 2]c7 e Fg ADB 4 3 20 -BGE 3. 2 |e NEG INDKD 6 2 |ga aANDA 3 2]ce eons z 2 fFc 10D 5 3 2D BLT 3 2fer 9 BTA 3. 2]c9 socB 2 2 ]Fo sto 53 2 BGT 3. 2 f62 9% LDAA 3. 2] cA oRAB 2 2]re ioe v 5 3 2F BLE REL 3 2 163 cOM 46 2 |r STAA 4 2 7>CB ANDAR 2 2 PFE STx FXTNT 5 4a 3G TSX INHER 3 1 }64 LSR 6 2 [38 EGRA 3 2qycc ob 3 a 31 INS 3. 1 fee oe 99 ADCA 3. 2]co . * UNDEF NED O CODE 32 PULA 4 1 [66 ROR 6 2194 OfAA 3 2 fce Lx MMAMES 3 3 33 PULB 4 1 j6) ASR INOXD 6 2 [9B 4004 3 2 per . NOTES 1. Addressing Modes INHER = Inherent REL = Relative INOXD = Indexed IMMED = Immediate EXTND Extended DIR =Direct 2. Unassigned opcodes are indicated by *' and should not be executed 3. Codes marked by "T force the PC to function as a 16-bit counter MOTOROLA MICROPROCESSOR DATA 3-118TABLE 9 INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS Condition Codes immed Direct Index Extnd Inherent Boolean/ 5;413],2},110 Pointer Operations MNEM/Op} ~| #] Op] |] # | Op] ~] #| Op] ~] #]Op| ~] 4 Arithmetic Operation HIITENTZ] Vc Compare Index Register cex |ac{4} 3} 9c}5] 2}facl 6} 2] acl6| 3 X=-M.M-+1 ove TT (ty tli Decrement Index Register DEX 09] 3] 1)x-1**x efele ll]. Decrement Stack Pointer OES 3/3] 1)/SP-1*SP eleleleleles Increment Index Register INX O8{ 3] 1)x+1 "x olelefT]e]s Increment Stack Pointer INS 31/3 }1]1SP+1SP eleleajelete Load Index Register cox [ce[3][ 3foel4 [2yeels] 2} Fels | 3 Mo XyiMs te Xp efel fi tial. Load Stack Pointer vos |@e[3] 3] 9e]4][2 facts] 2[8e[5] 3 M* SPHiM+11* SPL eleTfT[tlale Store Index Register STX DF] 4] 2;EF; 5] 2] FFI 5 | 3 Ky PMX, IM eT ele TT] [a]. Store Stack Pointer STS oF fa] 2 AFI 5) 21 BF] 5 | 3 SPE M.SPL iM ele li Tt]s]- index Reg Stack Pomnter TXS 35]3]1|]x-1"SP welefetslele Stack Pntr * index Register TSX 30];3]1)/SP+1x eleletiele le Add ABX BA} 3] 1) B+ xx olelelealeo fe Push Data PSHX 3C] 4 | 1 |X. * Mcp. SP- 1" Se eleleleleole Xug* Mop. SP-1* SP Pull Data PULX 38/5] t[SP+1* SP Mop xy elelelelele SP+1*SP Mop x, TABLE 10 ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2) Condition Codes Accumuiator and Immed Direct Index Extend Inher Boolean 51/4)/3];2]}1[0 Memory Operations MNEM[Op|~ | #] Op} ~ | #]Op|~| # [Op] ~ | # Op] ~ | # Expression HIE IN| ZEV EC Add Accumulators ABA ta{2|1;a-8A Te TPT ttt Add B to X ABX SA}3 [1 )0CB+x*x ealelefejefe Add with Carry ADcA {aa |2|2[ 93/3] 2]aal4] 2 [es[4]3 A=MsCA Tye (Pptptit ance (c9|2|2{o9'3]2fesfa| 2 [rela] 3 B-M-CB Tle (titT tit Add ADDA [as | 2 | 2/9843 | 2]AB| 41 2 [Bala | 3 A-MA Tye [titi tyt Aoos |ce|2|2/08}3]2\ee|4| 2 [refs | 3 B-Mo A TT. Gt [t[ tt Add Double apop|c3]4 [3fosts [2 /estie | 2 irafe [3 O-MM-1*9 ole Plt tt And ANDA {84 [2 [2/94 {3 [2 [as] 4] 2 [84]4 [3 AN ole ]iltfel- anos [ca[2 [2[o4]3 [2 [ea[a] 2 frala [3 Bates ele (Tftlal- Shift Left, Anthmetic ASL oe le|2 feels e[-(t[t]t]t ASLA eel YHOU ---eaitin ASLB se f2 fa c : {-(tit{t{ Shift Left Double ASLD 06 [3 ft eT TET ET Shift Right, Arithmetic ASR 67 46 | 2 177 16 3 CA = eis ASRA a7j2 |: QUT) [4 ASRB s7 {2 |: 5 o ls Bit Test BITA [85 {2 {2}9513 | 2 [a5[4 | 2 [as]a [3 Awl e fe [title]. aims fcs{2 12]/05][3 {2 le5|4] 2 ese |3 BoM fe [bitte [e Compare Accumulators CBA 142, 1A 8 t Tltlt Clear CLR er [6 | 2 [vr fe [3 oo le fe fs [es [A CLRA ae [2 [1 [oc a e {- fe ls fale CLR 5F 2 [1 focs ete je is[alr Compare CMPA 181} 2 }2{91 [3 [2 [Al [4 | 2 je1]4 13 aAoM el TTT TT compe [cr [2 [2for {3 f2 [er fa | 2 [ry [a | 3 8-M fe [tltytl{t 1's Complement cOM 63 [6 | 2 [73 [6 [3 MoM eye (titles COMA 43 ]2 fi |A A ete iE ]t}els COMB 53 [2 [1 [as fe it it [els MOTOROLA MICROPROCESSOR DATA 3-119MC6801/6803 TABLE 10 ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2) Accumulator and Decimal Adjust, A Decrement Exclusive OR increment Load Accumulators Load Double Logical Shift, Left Shift Right, Logical 2's Complement (Negate! No Operation inclusive OR Push Data Pull Data Rotate Left Rotate Right Subtract Accumulator Subtract with Carry Store Accumulators TO Subtract BA 8B Subtract Double AB BA Test, Zero or Minus Sst STA STB Transfer Accumulator Oirect Index Extend The condition code register notes are listed after Table 12 Inher Condition Codes Boolean sum to BCD M~1*M A-17*A B-1-*8 A@MA BeuM-B M+1*M A+1l*A B+i1-*B MA MB xBoO -M*M -ATTA ~BB +1* PC +MA +MmB Stack * Stack tack * A ~C -4 E- CIE -BA -=M-C*A -M-C8 Neen IOTOROLA MICROPROCESSOR DATA 3-120MC6801/6803 TABLE 11 JUMP AND BRANCH INSTRUCTIONS Condition Code Reg. Oirect Relative Index Extend Inherent 514] 3] 2/1] 0 Gperations MNEM/Op] 7 #) Op[ ] # /Op/ ~| # [Op] ~] # {Op} ~| # Branch Test HE EEN] ZT ViC Branch Always BRA 20) 3] 2 None efelfeteole;e Branch Never BRN 21)3] 2 None @elelelelajes Branch tf Carry Clear 6CcC 24,3] 2 c=0 @fetefefele Branch lf Carry Set BCS 25/312 C= efeleleleles Branch If= Zero BEQ 2713 | 2 Z=1 efeleletelse Branch If =Zero BGE 2C/ 3] 2 N@v=0 wlepejeleje Branch if >Zero BGT 2E|3{ 2 Z+IN @vi=0 eleletelele Branch If Higher BHI 2213 {2 C+Z=0 ejeleleolele Branch If Higher or Same BHS 24/342 c=0 elesteleleole Branch if <Zero BLE 2F|3 | 2 Z+iIN@ vial eleletelele Branch If Carry Set BLO 2513 |2 C=1 ejelelojelte Branch If Lower Or Same BLS 23)342 C+Z51 eleteltoleoete Branch If <Zero BLT 2D|3 | 2 N @v=1 elelelelele Branch If Minus BMI 28/3] 2 N=1 ojeteloepete Branch If Not Equal Zero BNE 2643] 2 zZ=0 eleleyelele Branch ff Overflow Clear BYC 28/342 V=0 efeleyeleole Branch If Overflow Set BVS 29;3 12 Vel ejeleltejeote Branch If Plus BPL 2A)3 | 2 N=0 eleyelelele Branch To Subroutine BSR 8D] 6 | 2 eleleyelele Jume JMP 6E)3]2)7E]3 43 See Speciat Operations-F.gure 25% |* fe |* |e te Jump To Subroutine JSR |S0}5 | 2 AD] 6 | 2 |BD|6 | 3 eo leletelelse No Operation NOP. o1y24y1 ete le jie lele Return From Interrupt RT 3B [10] 1 tyt TITTT t Return From Subroutine RTS 3915 | 1 |See Special Operations-Figure 25p* Fe te fe fe |e Software Interrupt Sw 3F 12] 1 @1]Slelele fe Wait For Interrupt WAI BE }9]1 ole le fe fete TABLE 12 CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS Condition Code Register Inherent 14,342 1 0 Operations MNEM | Op | ~ # | Boolean Operation | H I N]Zivyic Clear Carry CLC ac | 2 1 a-C . . . . e R Clear interrupt Mask cul OE | 2 1 Oo! e R e . . . Clear Overflow CLV OA | 2 1 Oo-vV . . . . R . Set Carry SEC oD | 2 1 1c . . . Ss Set Interrupt Mask SEl OF | 2 1 1] . Ss . . Set Overflow SEV OB | 2 1 Iv * . . . Ss . Accumulator A-* CCR TAP | 06 12/1 ACCR t}]tyr pry CCR-* Accumulator A TPA 07 | 2 1 CCR-*A . . . . . LEGEND CONDITION CODE SYMBOLS Op Operation Code (Hexadecimal) H Half-carry from bit 3 ~ Number of MPU Cycles | Interrupt mask Msp. Contents of memory location pointed to by Stack Pointer N Negative (sign bit} # Number of Program Bytes 2 Zero (byte) + Arithmetic Plus V Overflow, 2's complement Arithmetic Minus C Carry/Borrow from MSB * Boolean AND R Reset Always X Arithmetic Multiply S Set Always + Boolean Inclusive OR 1 Atfected e@ Boolean Exclusive OR Not Affected M Complement of M Transfer Into OQ Bit= Zero 00 Byte= Zero Oe | MOTOROLA MICROPROCESSOR DATA 3-121MC6801/6803 TABLE 13 INSTRUCTION EXECUTION TIMES IN E CYCLES @anejey COHHHSHOSHEOEH HOSE EE ESOS eO ESOS SECE COCO OOS wUesBYuY MOCCHHENINMENNEMe THAN NN ENN NOOO eee AANA MMOD w a z Ppexepu SMOT HH HOST HKDOTOOOHDK OS OT OOOOH celeeeeceee 9 z a a pepuesxg SOMOT HH HOCH COTOOCHOCKOSOT EBB HnHKT OB eeeereneS c a g yeng SCOOMTT TOSCO EM CHORE H OR OMNeeEem THEM Hele eeeeee e1UIpewuy) CHENIN MOOOEEO HNO CCR OE SOCK OOOO esenrveleeeenee aa x x 3 Sax qoux ees50SitrTiaist]_ ynatoo_s DOs Zz xsm a 58 ole = sf OM x maoddexng a0q0|n Oe w Y2nDaDO0O0CRFFmaaaoaEEP? ese zoe ee eee ROR eo EE 22 Sixemaoaxs saneiey | SSP SEH SOOM OM MAIN MeEMAMAMIMAMMMOMN| Dee 0000000000006 suese4yu NOSSPENM NO CHOCO RESCH EEO OOOO SENN NNN AN BANA M Oem w a 3 = pexepu| COT TOTOPOCCOHH CCE OCR OOS ROO LOD eee OdODeDeOT LS 9 z oO pepuaexg COT TOTC@OCeSCHSOC SOTO COS OCS EES EORIDa OHH OY ODODE OTLS a Q < eg COMMON ASSHSSHC CE BOE EOS ROEEBIORC ee eeM OD eee emee Syelpauruy SCONNTNEOOCHCHOC SCENE OF OOS E OE EOS ee OeNO TOR BON OS < voba 9 o/e x x sj TCOnNOWF/I_ NH = w qZaeofn - Onxa De OO eA DO ORO OE Te aE Z ae EGSISSLSSAS OKI GLE Soy tddqidc@ddnananadoonmaaalmonmawnolncoovdoosocoaoonZzZ MOTOROLA MICROPROCESSOR DATA 3-122MC6801/6803 SUMMARY OF CYCLE-BY-CYCLE OPERATION Table 14 provides a detailed description of the information present on the address bus, data bus, and the read/write (R/W) line during each cycle of each instruction. The information is useful in comparing actual with ex- pected results during debug of both software and hardware as the program is executed. The information is categorized in groups according to addressing mode and number of cycles per instruction. In general, instructions with the same ad- dressing mode and number of cycles execute in the same manner. Exceptions are indicated in the table. Note that during MPU reads of internal locations, the resultant value will not appear on the external data bus ex- cept in mode 0. High order byte refers to the most- significant byte of a 16-bit value. TABLE 14 CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5) Address Mode and Cycle R/W Instructions Cycles| # Address Bus Line Data Bus IMMEDIATE ADC EOR 2 1 Opcode Address 1 Opcode ADD LDA 2 Opcode Address + 1 1 Operand Data AND ORA BIT SBC CMP SUB LDS 3 1 Opcode Address 1 Opcode LDX 2 Opcode Address + 1 1 Operand Data (High Order Byte) LODO 3 Opcode Address + 2 1 Operand Data (Low Order Byte) CPX 4 1 Opcode Address 1 Upcode SUBD 2 Opcode Address + 1 1 Operand Data (High Order Byte) ADDD 3 Opcode Address + 2 1 Operand Data (Low Order Byte? 4 Address Bus FFFF 1 Low Byte of Restart Vector DIRECT ADC EOR 3 4 Opcode Address 1 Opcode ADD LDA 2 Opcode Address + 1 1 Address of Operand AND ORA 3 Address of Operand 1 Operand Data BIT SBC CMP SUB STA 3 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Destination Address 3 Destination Address 0 Data from Accumulator LDS 4 1 Opcode Address 1 Opcode LDX 2 Opcode Address + 1 1 Address of Operand LDD 3 Address of Operand 1 Operand Data (High Order Byte) 4 Operand Address + 1 1 Operand Data (Low Order Byte) STs 4 i Opcode Address 1 Opcode STX 2 Opcode Address + 1 1 Address of Operand STD 3 Address of Operand 0 Register Data (High Order Byte) 4 Address of Operand + 1 0 Register Data (Low Order Byte) CPX 5 1 Opcode Address 1 Opcode SUBD 2 Opcode Address + 1 1 Address of Operand ADDD 3 Operand Address 1 Operand Data (High Order Byte) 4 Operand Address+1 1 Operand Data (Low Order Byte) 5 Address Bus FFFF 1 Low Byte of Restart Vector JSR 5 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Subroutine Address 1 First Subroutine Opcode 4 Stack Pointer 0 Return Address (Low Order Byte) 5 Stack Pointer -1 0 Return Address (High Order Byte) MOTOROLA MICROPROCESSOR DATAMC6801/6803 TABLE 14 CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5) Address Mode and Cycle RW Instructions Cycles] # Address Bus Line Data Bus EXTENDED JMP. 3 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Jump Address (High Order Byte? 3 Opcode Address + 2 1 Jump Address 1Low Order Byte) ADC EOR 4 1 Opcode Address 1 Opcode ADD LDA 2 Opcode Address ~ 1 1 Address of Operand AND ORA 3 Opcode Address - 2 1 Address of Operand 'iow Order SB. BIT SBC 4 Address of Operand i Operand Data CMP SUB STA 4 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Destination Address 'High Order Byte! 3 Opcode Address + 2 1 Destination Address :Low Order 8. 4 Operand Destination Address 0 Data from Accumurator LDS 5 1 Opcode Address 1 Opcode LDX 2 Opcode Address+ 1 1 Address of Operand |High Orde: Q. te LDD 3 Opcode Address +2 1 Address of Operand 'Low Order Byte: 4 Address of Operand 1 Operand Data High Order Byte 5 Address of Operand + 1 1 Operand Data iLow Order B, te sTSs 5 1 Opcode Address 1 Opcode STX 2 Opcode Address + 1 1 Address of Operand High Order B.te STD 3 Opcode Address + 2 1 Address of Operand 'Low Order Byte: 4 Address of Operand 0 Operand Data (High Order Byte 5 Address of Operand+ 1 Qo Operand Data (Low Order Byte ASL LSR 6 1 Opcode Address 1 Opcode ASR NEG 2 Opcode Address + 1 1 Address of Operand High Order Byte! CLR ROL 3 Opcode Address + 2 1 Address af Operand Low Order Byte: COM ROR 4 Address of Operand 1 Current Operand Data DEC [si* 5 Address Bus FFFF 1 Low Byte of Restart Vector INC 6 Address of Operand Go New Operand Data CPX 6 1 Opcode Address 1 Opcode SUBD 2 Opcode Address + 1 Operand Address iHigh Order Byte! ADDD 3 Opcode Address+ 2 ] Operand Address Low Order Byte 4 Operand Address , Operand Data (High Order Byte! 5 Operand Address + 1 1 Operand Data (Low Order Byte? 6 Address Bus FFFF 1 Low Byte of Restart Vector JSR 6 1 Opcode Address 1 Opcade 2 Opcode Address+ 1 1 Address of Subroutine (High Order Byte 3 Opcode Address + 2 1 Address of Subroutine (Low Order Byte: 4 Subroutine Starting Address 1 Opcode of Next Instruction 5 Stack Pointer Cc Return Address (Low Order Byte! 6 Stack Pointer 1 0 Return Address (High Order Byte? *TST does not perform the write cycle during the sixth cycle The sixth cycle 1s another address bus = $F FFF MOTOROLA MICROPROCESSOR DATA 3-124MC6801/6803 TABLE 14 CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5) Address Mode and Cycle R/W Instructions Cycles] # Address Bus Line Data Bus INDEXED JMP 3 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector ABC EOR 4 1 Opcode Address 1 Opcode ADD LDA 2 Opcode Address + 1 1 Offset AND ORA 3 Address Bus FFFF 1 Low Byte of Restart Vector BIT SBC 4 Index Register Plus Offset 1 Operand Data CMP SUB STA 4 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Pius Offset 0 Operand Data LDS 5 1 Opcode Address 1 Opcode LDXx 2 Opcode Address + 1 1 Offset LDD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 1 Operand Data (High Order Byte 5 index Register Plus Oftset + 1 1 Operand Data {Low Order Byte) STS 5 1 Opcode Address 1 Opcode STX z Opcode Address + 1 1 Offset STD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 0 Operand Data (High Order Byte! 5 Index Register Plus Offset + 1 0 Operand Data {Low Order Byte} ASL LSR 6 1 Opcode Address 1 Opcode ASR NEG 2 Opcode Address + 1 1 Offset CLR ROL 3 Address Bus FFFF 1 Low Byte of Restart Vector COM ROR 4 Index Register Plus Offset 4 Current Operand Data DEC TST* 5 Address Bus FFFF 1 Low Byte of Restart Vector INC 6 Index Register Plus Offset 0 New Operand Data CPX 6 1 Opcode Address 1 Opcode SUBD 2 Opcode Address + 1 1 Offset ADDD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 index Register+ Offset 1 Operand Data (High Order Byte 5 Index Register + Offset+ 1 1 Operand Data {Low Order Byte} 6 Address Bus FFFF Low Byte of Restart Vector JSR 6 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register + Offset 1 First Subroutine Opcode 5 Stack Pointer Q Return Address tLow Order Byte) 6 Stack Pointer t+ oO Return Address (High Order Byte) *TST does not perform the write cycle during the sixth cycle The sixth cycle is another address bus= $FFFF MOTOROLA MICROPROCESSOR DATA 3-125MC6801/6803 TABLE 14 CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5) Address Mode and Cycle R/W Instructions Cycles] # Address Bus Line Data Bus INHERENT ABA DAA SEC] 2 1 Opcode Address ] Opcode ASL DEC SEI 2 Opcode Address + 1 1 Opcode of Next Instruction ASR INC SEV CBA LSR TAB CLC NEG TAP cli Nop TBA CLR ROL TPA CLV ROR TST COM SBA ABX 3 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Address Bus FFFF ] Low Byte of Restart Vector ASLD 3 1 Opcode Address 1 Opcode LSRD 2 Opcode Address + 1 1 {irrelevant Data 3 Address Bus FFFF 1 Low Byte of Restart Vector DES 3 1 Opcode Address ] Opcode INS 2 Opcode Address +1 1 Opcode of Next Instruction 3 Previous Stack Pointer Contents] 1 Irrelevant Data INX 3 1 Opcode Address 7 Opcode DEX 2 Opcode Address + 1 1 Opcode of Next Instruction 3 Address Bus FFFF 1 Low Byte of Restart Vector PSHA 3 1 Opcode Address 1 Opcode PSHB 2 Opcode Address+ 1 1 Opcode of Next Instruction 3 Stack Pointer 0 Accumulator Data TSX 3 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Opcode of Next Instruction 3 Stack Pointer 1 Irrelevant Data TS 3 1 Opcode Address 1 Opcode 2 Opcode Address +1 1 Opcode of Next Instruction 3 Address Bus FFFF 1 Low Byte of Restart Vector PULA 4 1 Opcode Address 1 Opcode PULB 2 Opcode Address + 1 1 Opcode of Next Instruction 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer+1 1 Operand Data from Stack PSHX 4 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Stack Pointer 0 Index Register (Low Order Byte) 4 Stack Pointer-1 0 index Register (High Order Byte} PULX 5 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 irrelevant Data 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer+1 1 Index Register {High Order Byte) 5 Stack Pointer +2 1 Index Register {Low Order Byte) RTS 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 (rrelevant Data 3 Stack Pointer 1 irrelevant Data 4 Stack Pointer+1 1 Address of Next Instruction (High Order Byte} 5 Stack Pointer+2 1 Address ot Next Instruction (Low Order Byte) WAT 9g 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Opcode of Next Instruction 3 Stack Pointer 0 Return Address !Low Order Byte! 4 Stack Pointer-1 0 Return Address (High Order Byte! 5 Stack Pointer2 0 Index Register (Low Order Byte) 6 Stack Pointer -3 0 Index Register (High Order Byte! 7 Stack Pointer 4 0 Contents of Accumulator A 8 Stack Pointer5 0 Contents of Accumulator B 9 Stack Pointer-6 0 Contents of Condition Code Register MOTOROLA MICROPROCESSOR DATA 3-126MC6801/6803 TABLE 14 CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5) Address Mode and Cycle R/W instructions Cycles| # Address Bus Line Data Bus INHERENT MUL 10 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Address Bus FFFF 4 Low Byte of Restart Vector 4 Address Bus FFFF 1 Low Byte of Restart Vector 5 Address Bus FFFF 1 Low Byte of Restart Vector 6 Address Bus FFFF 1 Low Byte of Restart Vector 7 Address Bus FFFF 1 Low Byte of Restart Vector 8 Address Bus FFFF 1 Low Byte of Restart Vector 9 Address Bus FFFF 1 Low Byte of Restart Vector 10 | Address Bus FFFF 1 Low Byte of Restart Vector RTI 10 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer + 1 1 Contents of Condition Code Register from Stack 5 Stack Pointer + 2 1 Contents of Accumulator B from Stack 6 Stack Pointer + 3 1 Contents of Accumulator A from Stack 7 Stack Pointer + 4 1 Index Register from Stack (High Order Byte) 8 Stack Pointer +5 1 index Register from Stack (Low Order Byte) 9 Stack Pointer + 6 1 Next Instruction Address from Stack (High Order Byte) 10 | Stack Pointer+7 1 Next Instruction Address from Stack (Low Order Byte? SWI 12 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Irrelevant Data 3 Stack Pointer 0 Return Address (Low Order Byte! 4 Stack Pointer -1 0 Return Address (High Order Byte! 5 Stack Pointer 2 0 index Register (Low Order Byte! 6 Stack Pointer 3 0 Index Register {High Order Byte) 7 Stack Pointer 4 0 Contents of Accumulator A 8 Stack Pointer 5 0 Contents of Accumutator B 9 Stack Pointer 6 0 Contents of Condition Code Register 10 | Stack Pointer7 1 Irrelevant Data 11. | Vector Address FFFA (Hex) 1 Address of Subroutine High Order Byte? 12 Vector Address FFFB (Hex) 1 Address of Subroutine !Low Order 8yte: RELATIVE BCC BHT BNE BLO 3 1 Opcode Address 1 Opcode BCS BLE BPL BHS 2 Opcode Address + 1 1 Branch Offset BEQ BLS BRA BRN 3 Address Buss FFFF 1 Low Byte of Restart Vector BGE BLT BVC BGT BMI BVS BSR 6 1 Opcode Address 1 Opcode 2 Opcode Address + 1 1 Branch Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Subroutine Starting Address 1 Opcode of Next Instruction 5 Stack Pointer a Returm Adaress !Low Order Bytet 6 Stack Pointer 1 0 Return Address (High Order Byte! MOTOROLA MICROPROCESSOR DATA 3-127MC6801/6803 UONSNIISU] IXdA) ssaippy xan = Ty sse.ppy 1x8N =Hy dW = 325 weiBog ue, TNLY HNL (1x) sarsiBey xepul (Hy) saysiBey xapu| v yoy Bwwoy @pon UaIpUOD 4981S INLY HWid (1x) saysiBey xapu] (Hx) sasiBay xapu| Vv Ayo g woy apo uoNpuos) 4081S t+d$ 9+dS Gt+d$ ptds E+dsS e+dS l+d$ d dS l-d e~-dS -ds e-dS G~-dS$ 9-dS Z-d dS uononnsuy xan pepuaix3 WasHO = 4 dP = 498 wesBoig ulew lL = 8$ wesBoug dna; IM = Jes wel6olg ule _ IMS = 4$ wei6oig ule QXONI 3d duinr "dwE 3d idqwalut wo wintay 14 Nid 3d idnsiayuy JOY We AA NVA, NIY 3d WdNwajU; BPMYCS |AAS INL HNL eS INLY HN1Y IES TNL HN 49215 SNOILVH3d0 WWIDddS $2 AUNDIS c+dS l+dS ds ds dS L-dS @-dS =e L-dS -dS = anjea pauBisun 1tq-g = UONNDEXg JAI) y JaUIOg OBIS = a ssalppy WMSY {0 d1Aq jUerjiUBIs sed = INLY ssaippy Wnjay 40 a}Aq JUedyUBIs IsoW = HN IY SLY =6ES aunnoiqns Jysu} WEY 1xeN lasyo=NF yS8 =d8$ wesBog uleW ISU] UIEW 1X8N Ippy 4ans =1 appy sans =HS ySr =aas wes6oig VIEW JISU] LIB) 1X3N) 498430 = > yuSf =avs wes6o1g view ssaippy 193119 = 4 ASU UIA X8N YSP = G6$ wesBoug Wie, BUNNOIQNS WOd) WN\ad UOdN payndaxa aq oO} welbog uleW Ul UONSNASUI IxBU JO SSUIPPY =N LY puabay od BuUNNOIANS wos wuMaYy SLY Niu dd aulnaiqns Oo) youelg YSg NlY ONLX3 3d N1Y OXanNi Od Niu paid 3d auNNaigns Oo} dwnr ysr MOTOROLA MICROPROCESSOR DATA 3-128MC6801/6803 ORDERING INFORMATION The following information is required when ordering a custom MCU. The information may be transmitted to Motorola using the following media: MDOS, disk file PC-DOS disk file (360K) EPROM(s) 2516, 2716, MC68701 To initiate a ROM pattern for the MCU, it is necessary to first contact the local field service office, sales person, or a Motorola representative. FLEXIBLE DISKS Several types of flexible disks (MDOS or PC-DOS disk file) may be submitted for pattern generation. They should be programmed with the customers program, using positive logic sense for address and data. The diskette should be clearly labeled with the customers name, date, project or product name, and the filename containing the pattern. In addition to the program pattern, a file containing the program source code listing can be included. This data will be kept confidential and used to expedite the process in case of any difficulty with the pattern file. MDOS Disk File MDOS is Motorolas Disk Operating System available on the EXORciser development system. The disk me- dia submitted must be a single-sided, single-density, 8- inch MDOS compatible floppy diskette. The diskette must contain the minimum set of MDOS system files in ad- dition to the pattern file. The .LO output of the M6801 cross assembler should be furnished. In addition, the file must be produced using the ROLLOUT command, so that it contains the absolute image of the M6801 memory. It is necessary to include the entire memory image of both program and data space. All unused bytes, including those in the user space, must be set in logic zero. PC-DOS Disk File PC-DOS is the IBM* Personal Computer Disk Oper- ating System. Disk media submitted must be standard density (360K), double-sided 5-1/4 inch compatible floppy diskette. The diskette must contain the object file code in Motorolas S-record format. The S-record format is a character-based object file format generated by M6801 cross assemblers and linkers on IBM PC style machines. EPROMS A single 2K EPROM is necessary to contain the entire MC6801 program. The EPROM is programmed with the customer program using positive logic sense for ad- dress and data. All unused bytes, including the user's space, must be set to zero. If the MC6801 MCU ROM pattern is submitted on a single 2516 or 2716 type EPROM, memory map ad- dressing is one-for-one. The data space ROM runs from EPROM address $000 to $7FF. If an MC68701 is used, the ROM map runs from $F800 to $FFFF. For shipment to Motoro!a, EPROMs should be placed in a conductive IC carrier and packed securely. Styro- foam is not acceptable for shipment. Verification Media All original pattern media, EPROMs or floppy disks, are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned along with a listing verification form. The listing should be thoroughly checked and the verifica- tion form completed, signed, and returned to Motorola. The signed verification form constitutes the contractual agreement for the creation of the customer mask. To aid tn the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the data file used to create the custom mask. ROM Verification Units (RVUs) Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units will have been mace using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs are unmarked, packaged in ceramic, and tested with five volts at room temperature. These RVUs are free with the minimum order quantity, but are not pro- duction parts. These RVUs are not guaranteed by Mo- torola Quality Assurance. Ordering Information The following table provides generic information per- taining to the package type and temperature for the MC6801/MC6803. This MCU device is available only in the 40-pin dual-in-line (DIP) package in the Cerdip and Plastic packages. MDOS is a trademark of Motorola tnc. MS-DOS is a trademark of Microsoft, Inc. EXORciser is a registered trademark of Motorola Inc. IBM is a registered trademark of International Business Machines Corporation. GENERIC INFORMATION Frequency | Temperature | Cerdip Package | Plastic Package | (MHz) (Degrees C) {S Suffix) {P Suffix) i 1.0 0 to 70 MC6801S1 MC6801P1 1.0 40to -85| MC6801CS1 MC6801CP1 1.25 0 to 70 MC6801S1-1 MC6801P1-1 1.25 -40 to +85) MC6801CS-1 MC6801CP-1 | 2.0 0 to 70 MC68B01S1 MC68B01P1 1.0 O0to70 | MC6803S MC6803P 1.0 40to ~85: MC6803CS MC6803CP 1.25 0 to 70 MC6803S-1 MC6803P-1 1.25 40 to +85| MC6803CS-1 MC6803CP-1 2.0 0 to 70 MC68B03S MC68B03P MOTOROLA MICROPROCESSOR DATA 3-129MC6801/6803 PIN ASSIGNMENT VssQ1 eo whe XTAL2 39fJsci EXTALQ3 3af]sc2 NMI O4 3717 P30 ROIs 36 [J P31 RESET G6 35] P32 Voc 7 34] P33 P20 8 33] P34 P2179 3211 P35 P22 M10 3110 P36 P23 911 300 P37 P24 12 29] P40 P10 913 26 [J P41 Pita 270) P42 P12 (16 26] P43 P1316 2571 p44 P1417 241) P45 P15 18 23] P46 P16 fi9 221) p47 P1720 2101 Ycc Standby MOTOROLA MICROPROCESSOR DATA 3-130