REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes IAW NOR 5962-R204-94. – jak 94-06-07
Monica L. Poelking
B
Changes IAW NOR 5962-R045-95. - jak
95-10-31
Monica L. Poelking
C
Update boilerplate to MIL-PRF-38535. Editorial changes throughout. – jak
00-11-29
Thomas M. Hess
D
Update boilerplate paragraphs to the current MIL-PRF-38535 requirements.
- LTG
09-03-24
Thomas M. Hess
REV
SHEET
REV D D D
SHEET 15 16 17
REV STATUS REV D D D D D D D D D D D D D D
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Joseph A. Kerby
CHECKED BY
Thanh V. Nguyen
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
APPROVED BY
Monica L. Poelking
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
94-01-18
MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR
CMOS, OCTAL EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH THREE-STATE OUTPUTS,
TTL COMPATIBLE INPUTS, MONOLITHIC
SILICON
AMSC N/A
REVISION LEVEL
D SIZE
A CAGE CODE
67268
5962-93220
SHEET 1 OF 17
DSCC FORM 2233
APR 97 5962-E217-09
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93220
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 - 93220 01 Q R A
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 54ABT574 Octal edge-triggered D-type flip-flop with three-state
outputs, TTL compatible inputs
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class Device requirements documentation
M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-
JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
R GDIP1-T20 or CDIP2-T20 20 Dual-in-line
S GDFP2-F20 or CDFP3-F20 20 Flat pack
2 CQCC1-N20 20 Square leadless chip carrier
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC).................................................................................. -0.5 V dc to +7.0 V dc
DC input voltage range (VIN)................................................................................ -0.5 V dc to +7.0 V dc 4/
DC output voltage range (VOUT)........................................................................... -0.5 V dc to +5.5 V dc 4/
DC input clamp current (IIK) (VIN < 0.0 V)............................................................. -18 mA
DC output clamp current (IOK) (VOUT < 0.0 V)....................................................... -50 mA
DC output current (IOL) (per output)..................................................................... +96 mA
Storage temperature range (TSTG)....................................................................... -65C to +150C
Lead temperature (soldering, 10 seconds)........................................................... +300C
Thermal resistance, junction-to-case (JC)........................................................... See MIL-STD-1835
Junction temperature (TJ) .................................................................................... +175C
Maximum power dissipation (PD)......................................................................... 500 mW
1.4 Recommended operating conditions. 2/ 3/ 5/
Supply voltage range (VCC).................................................................................. +4.5 V dc to +5.5 V dc
Input voltage range (VIN)...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC
Maximum low level input voltage (VIL).................................................................. 0.8 V
Minimum high level input voltage (VIH)................................................................. 2.0 V
Case operating temperature range (TC)............................................................... -55C to +125C
Maximum input rise or fall rate (t/V)................................................................. 5 ns/V
Maximum high level output current (IOH).............................................................. -24 mA
Maximum low level output current (IOL)................................................................ 48 mA
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages are referenced to GND.
3/ The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55C to +125C.
4/ The input and output negative voltage ratings may be exceeded provided that the input and output clamp current ratings are
observed.
5/ Unused inputs must be held high or low to prevent them from floating.
STANDARD
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APR 97
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Ground bounce test circuit and waveforms. The ground bounce test circuit and waveforms shall be as specified on
figure 4.
3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 127 (see MIL-PRF-38535, appendix A).
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TABLE I. Electrical performance characteristics.
Test and
MIL-STD-883 test
method 1/
Symbol Test condition 2/
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups
Limits 3/ Unit
Min Max
High level
output voltage
3006
VOH1 For all inputs affecting
output under test
VIN = 2.0 V or 0.8 V
IOH = -3 mA
All 4.5 V 1, 2, 3 2.5 V
V
OH2 For all inputs affecting
output under test
VIN = 2.0 V or 0.8 V
IOH = -3 mA
All 5.0 V 1, 2, 3 3.0
V
OH3 For all inputs affecting
output under test
VIN = 2.0 V or 0.8 V
IOH = -24 mA
All 4.5 V 1, 2, 3 2.0
Low level
output voltage
3007
VOL For all inputs affecting
output under test
VIN = 2.0 V or 0.8 V
IOL = 48 mA
All 4.5 V 1, 2, 3 0.55 V
Three-state output
leakage current
high
3021
IOZH
4/ 5/
For control inputs affecting
output under test VIN = VIH or VIL
VIH = 2.0 V
VIL = 0.8 V
VOUT = 2.7 V
All 5.5 V 1, 2, 3 10.0 A
Three-state output
leakage current
low
3020
IOZL
4/ 5/
For control inputs affecting
output under test VIN = VIH or VIL
VIH = 2.0 V
VIL = 0.8 V
VOUT = 0.5 V
All 5.5 V 1, 2, 3 -10.0 A
Negative input
clamp voltage
3022
VIC- For input under test IIN = -18 mA All 4.5 V 1, 2, 3 -1.2 V
Off-state leakage
current IOFF For output under test
VIN or VOUT = 4.5 V
All other pins at 0.0 V
All 0.0 V 1 100.0 A
High-state leakage
current ICEX For output under test
VOUT = 5.5 V
Outputs at high logic state
All 5.5 V 1, 2, 3 50.0 A
Input current high
3010 IIH For input under test
VIN = VCC All 5.5 V 1, 2, 3 +2.0 A
Input current low
3009 IIL For input under test
VIN = GND All 5.5 V 1, 2, 3 -2.0 A
Output current
3011 IOUT
6/ VOUT = 2.5 V All 5.5 V 1, 2, 3 -50.0 -180.0 mA
See footnotes at end of table.
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TABLE I. Electrical performance characteristics - Continued.
Test and
MIL-STD-883 test
method 1/
Symbol Test condition 2/
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups
Limits 3/ Unit
Min Max
Quiescent supply
current delta,
TTL input levels
3005
ICC
7/
For input under test, VIN = 3.4 V
For all other inputs
VIN = VCC or GND
All 5.5 V 1, 2, 3 2.5 mA
Quiescent supply
current, output
high
3005
ICCH
VIN = VCC or GND
IOUT = 0.0 A
All 5.5 V 1, 2, 3 250.0 A
Quiescent supply
current, output
low
3005
ICCL
VIN = VCC or GND
IOUT = 0.0 A
All 5.5 V 1, 2, 3 30.0 mA
Quiescent supply
current, output
three-state
3005
ICCZ
VIN = VCC or GND
IOUT = 0.0 A
All 5.5 V 1, 2, 3 250.0 A
Input capacitance
3012
CIN
See 4.4.1c
TC = +25C
All 5.0 V 4 8.5 pF
Output capacitance
3012
COUT
See 4.4.1c
TC = +25C
All 5.0 V 4 14.5 pF
Low level
ground bounce
noise
VOLP
8/
All 5.0 V 4 800 mV
Low level
ground bounce
noise
VOLV
8/
All 5.0 V 4 -1700 mV
High level VCC
bounce noise
VOHP
8/
All 5.0 V 4 1300 mV
High level VCC
bounce noise
VOHV
8/
VIH = 3.0 V
VIL = 0.0 V
TA = +25C
See figure 4
See 4.4.1d
All 5.0 V 4 -800 mV
All 4.5 V 7, 8 L H Functional test
3014 9/ VIL = 0.8 V
VIH = 2.0 V
Verify output VOUT
See 4.4.1b
All 5.5 V 7, 8 L H
All 5.0 V 9 1.5 6.2
tPLH
10/ 4.5 V
and
5.5 V
10, 11 1.5 7.0
ns
5.0 V 9 1.5 7.0
Propagation delay
time, CLK to
mQ output
3003
tPHL
10/
CL = 50 pF minimum
RL = 500
See figure 5
All 4.5 V
and
5.5 V
10, 11 1.5 7.4
ns
See footnotes at end of table.
STANDARD
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TABLE I. Electrical performance characteristics - Continued.
Test and
MIL-STD-883 test
method 1/
Symbol Test condition 2/
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups
Limits 3/ Unit
Min Max
tPZH All
5.0 V 9 1.0 5.5 ns
10/
4.5 V
and
5.5 V
10, 11 1.0 6.5
tPZL All
5.0 V 9 1.0 5.9 ns
Propagation delay
time, output enable
OE to mQ output
3003
10/
4.5 V
and
5.5 V
10, 11 1.0 7.2
tPHZ All
5.0 V 9 1.0 6.2 ns
10/
4.5 V
and
5.5 V
10, 11 1.0 7.2
tPLZ All
5.0 V 9 1.0 5.8 ns
Propagation delay
time, output disable,
OE to mQ output
3003
10/
4.5 V
and
5.5 V
10, 11 1.0 6.7
Maximum clock
frequency fMAX
11/ All 5.0 V 9, 10, 11 150 MHz
Pulse duration, CLK
high or low
tw
11/ All 5.0 V 9, 10, 11 3.3 ns
Setup time high,
data before clock
rising
ts1
11/
All
5.0 V 9, 10, 11 1.5 ns
Setup time low,
data before clock
rising
ts2
11/
All
5.0 V 9, 10, 11 2.0 ns
Hold time high or
low, data after
clock rising
th
11/
CL = 50 pF minimum
RL = 500
See figure 5
All
5.0 V 9, 10, 11 2.0 ns
1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure of 883 under the conditions
listed herein.
2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except for all ICC and ICC tests,
where the output terminals shall be open. When performing these tests, the current meter shall be placed in the circuit such
that all current flows through the meter. For input terminals not designated, VIN= GND or VIN = 3.0 V.
3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow respectively; the absolute value of the magnitude, not the sign, is relative to the minimum and
maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I at
4.5 V VCC 5.5 V.
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TABLE I. Electrical performance characteristics - Continued.
4/ This test shall be guaranteed, if not tested, to the limits specified in table I herein, when performed with control inputs that
affect the state of the output under test at VIN = 0.8 V or 2.0 V.
5/ Due to tester limitations, this test may be performed at VIH = 3.0 V but shall be guaranteed at VIH = 2.0 V.
6/ Not more than one output should be tested at one time and the duration of the test condition should not exceed one second.
7/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN =
V
CC -2.1 V (alternate method). Classes Q, and V shall use the preferred method. When the test is performed using the
alternate test method the maximum limit is equal to the number of inputs at a high TTL input level times 2.5 mA, and the
preferred method and limits are guaranteed.
8/ This test is for qualification only. Ground and VCC bounce tests are performed on a non-switching (quiescent) output and
are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is
performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500 of load
resistance and a minimum of 50 pF of load capacitance (see figure 4). Only chip capacitors and resistors shall be used.
The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever
possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parallel from VCC to
ground. The values of these decoupling capacitors shall be determined by the device manufacturer. The low and high
level ground and VCC bounce noise is measured at the quiet output using a 1 GHz minimum bandwidth oscilloscope with a
50 input impedance.
The device inputs shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then
be conditioned such that they switch simultaneously and the output under test remains at VOH as all other outputs possible
are switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest negative and
positive peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOL
to VOH.
The device inputs shall be conditioned such that all outputs are at a low nominal VOL level. The device inputs shall then be
conditioned such that they switch simultaneously and the output under test remains at VOL as all other outputs possible are
switched from VOL to VOH. VOLP and VOLV are then measured from the nominal VOL level to the largest positive and
negative peaks, respectively (see figure 4). This is then repeated with the same outputs not under test switching from VOH
to VOL.
9/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth
table in figure 2, herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. After incorporating allowable tolerances per MIL-STD-883, VIL = 0.4 V and VIH = 2.4 V. For outputs, L 0.8 V,
H 2.0 V.
10/ For propagation delay tests, all paths must be tested.
11/ This parameter shall be guaranteed, if not tested, to the limits specified in table I herein.
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Device type All
Case outlines R, S, 2
Terminal number Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
CLK
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
VCC
Pin description
Terminal symbol Description
mD (m = 1 to 8)
Data inputs
OE
Output enable control input (active low)
mQ (m = 1 to 8)
Outputs
CLK
Clock input (active rising edge)
FIGURE 1. Terminal connections.
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INPUTS OUTPUTS
OE CLK mD mQ
L H H
L L L
L L X Q0
H X X Z
H = High voltage level
L = Low voltage level
X = Irrelevant
Z = Disabled
= Low-to-high clock transition
Q0 = The value Q after the most recent positive transition of CLK
FIGURE 2. Truth table.
FIGURE 3. Logic diagram.
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NOTES:
1. CL includes a 47 pF chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance from the test jig
and probe.
2. RL = 450 1 percent, chip resistor in series with a 50 termination. For monitored outputs, the 50 termination shall
be the 50 characteristic impedance of the coaxial connector to the oscilloscope.
3. Input signal to the device under test:
a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN 1 MHz.
b. tr, tf = 3.0 ns 1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit
may be increased up to 10 ns, as needed, maintaining the 1.0 ns tolerance and guaranteeing the results at 3.0 ns
1.0 ns; skew between any two switching inputs signals (tsk) 250 ps.
FIGURE 4. Ground bounce test circuit and waveforms.
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FIGURE 5. Switching waveforms and test circuit.
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NOTES:
1. When measuring tPLZ and tPZL VTEST = 7.0 V.
2. When measuring tPHZ, tPZH, tPLH and tPHL: VTEST = open.
3. The tPZL and tPLZ reference waveform is for the output under test with internal conditions such that the output is at
VOL except when disabled by the output enable control. The tPZH and tPHZ reference waveform is for the output
under test with internal conditions such that the output is at VOH except when disabled by the output enable control.
4. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
5. RL = 500 or equivalent, RT= 50 or equivalent.
6. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 2.5 ns; tf 2.5 ns; tr and tf shall be
measured from 0.3 to 2.7 V and 2.7 V to 0.3 V, respectively; duty cycle = 50 percent.
7. Timing parameters shall be tested at a minimum input frequency of 1 MHz.
8 The outputs are measured one at a time with one transition per measurement.
FIGURE 5. Switching waveforms and test circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93220
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 14
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table II herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93220
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 15
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2) - - - - - - 1
Final electrical
parameters (see 4.2) 1/ 1, 2, 3, 7,
8, 9, 10, 11 1/ 1, 2, 3, 7,
8, 9, 10, 11 2/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4) 1, 2, 3, 4, 7,
8, 9, 10, 11 1, 2, 3, 4, 7,
8, 9, 10, 11 1, 2, 3, 4, 7,
8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3 1, 2, 3 1, 2, 3, 7, 8,
9, 10, 11
Group D end-point electrical
parameters (see 4.4)
1, 2, 3 1, 2, 3 1, 2, 3
Group E end-point electrical
parameters (see 4.4)
1, 7, 9 1, 7, 9 1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input
to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c. CIN and COUT, shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN and COUT shall be measured between the designated terminal and GND at a frequency of 1 MHz.
This test may be performed at 10 MHz and guaranteed, if not tested, at 1 MHz. The DC bias for the pin under test
(VBIAS) = 2.5 V or 3.0 V. For CIN and COUT, test all applicable pins on five devices with zero failures.
For CIN and COUT, a device manufacturer may qualify devices by functional groups. A specific functional group shall
be composed of function types that by design will yield the same capacitance values when tested in accordance with
table I, herein. The device manufacturer shall set a function group limit for the CIN and COUT tests. The device
manufacturer may then test one device functional group, to the limits and conditions specified herein. All other device
functions in that particular functional group shall be guaranteed, if not tested, to the limits and test conditions specified
in table I, herein. The device manufacturers shall submit to DSCC-VA the device functions listed in each functional
group and the test results for each device tested.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93220
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 16
DSCC FORM 2234
APR 97
d. Ground and VCC bounce tests are required for all device classes. These tests shall be performed only for initial
qualification, after process or design changes which may affect the performance of the device, and any changes to the
test fixture. VOLP, VOLV, VOHP, and VOHV shall be measured for the worst case outputs of the device. All other outputs
shall be guaranteed, if not tested, to the limits established for the worst case outputs. The worst case outputs tested
are to be determined by the manufacturer. Test 5 devices assembled in the worst case package type supplied to this
document. All other package types shall be guaranteed, if not tested, to the limits established for the worst case
package. The 5 devices to be tested shall be the worst case device type supplied to this drawing. All other device
types shall be guaranteed, if not tested, to the limits established for the worst case device type. The package type and
device type to be tested shall be determined by the manufacturer. The device manufacturer will submit to DSCC-VA
data that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VOLP,
VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of both a switching
output and the output under test.
Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is used, the device
manufacturer shall inform DSCC-VA of this change and test the 5 devices on both the new and old test fixtures. The
device manufacturer shall then submit to DSCC-VA data from testing on both fixtures, that shall include all measured
peak values for each device tested and detailed oscilloscope plots for each VOLP, VOLV, VOHP, and VOHV from one
sample part per function. The plot shall contain the waveforms of both a switching output and the output under test.
For VOHP, VOHV, VOLP, and VOLV, a device manufacturer may qualify devices by functional groups. A specific functional
group shall be composed of function types, that by design, will yield the same test values when tested in accordance
with table I, herein. The device manufacturer shall set a functional group limit for the VOHP, VOHV, VOLP, and VOLV tests.
The device manufacturer may then test one device function from a functional group, to the limits and conditions
specified herein. All other device functions in that particular functional group shall be guaranteed, if not tested, to the
limits and conditions specified in table I, herein. The device manufacturers shall submit to DSCC-VA the device
functions listed in each functional group and test results, along with the oscilloscope plots, for each device tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b. TA = +125C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table II herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,
after exposure, to the subgroups specified in table II herein.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-93220
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
D SHEET 17
DSCC FORM 2234
APR 97
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 09-03-24
Approved sources of supply for SMD 5962-93220 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9322001MRA
0C7V7
54ABT574DMQB
5962-9322001MSA
0C7V7
54ABT574FMQB
5962-9322001M2A
0C7V7
54ABT574LMQB
5962-9322001QRA 0C7V7
01295
54ABT574J-QML
SNJ54ABT574J
5962-9322001QSA 0C7V7
01295
54ABT574W-QML
SNJ54ABT574W
5962-9322001Q2A 0C7V7
01295
54ABT574E-QML
SNJ54ABT574FK
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE Vendor name
number and address
01295 Texas Instruments Incorporated
Semiconductor Group
8505 Forest Ln.
P.O. Box 660199
Dallas, TX 75243
Point of contact: U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
