Data Sheet U14590EJ1V0DS00
26
µ
µµ
µ
PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)
FlagMnemonic Operand Byte Clock Operation
ZACCY
A, #byte 2 4 A, CY ← A + byte × × ×
saddr, #by te 3 6 (saddr), CY ← (s addr) + byte × × ×
A, r 2 4 A ,CY ← A + r × × ×
A, s addr 2 4 A, CY ← A + (saddr) × × ×
A, ! addr16 3 8 A, CY ← A + (addr16) × × ×
A, [HL] 1 6 A, CY ← A + (HL) × × ×
ADD
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × ×
A, #byte 2 4 A, CY ← A + byte + CY × × ×
saddr, #by te 3 6 (saddr), CY ← (s addr) + byte + CY × × ×
A, r 2 4 A, CY ← A + r + CY × × ×
A, s addr 2 4 A, CY ← A + (saddr) + CY × × ×
A, ! addr16 3 8 A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 6 A, CY ← A + (HL) + CY × × ×
ADDC
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × ×
A, #byte 2 4 A, CY ← A – byte × × ×
saddr, #by te 3 6 (saddr), CY ← (s addr) – byte × × ×
A, r 2 4 A, CY ← A – r × × ×
A, s addr 2 4 A, CY ← A – (saddr) × × ×
A, ! addr16 3 8 A, CY ← A – (addr16) × × ×
A, [HL] 1 6 A, CY ← A – (HL) × × ×
SUB
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) × × ×
A, #byte 2 4 A, CY ← A – byt e – CY × × ×
saddr, #by te 3 6 (saddr), CY ← (saddr) – byte – CY × × ×
A, r 2 4 A, CY ← A – r – CY × × ×
A, s addr 2 4 A, CY ← A – (saddr) – CY × × ×
A, ! addr16 3 8 A, CY ← A – (addr16) – CY × × ×
A, [HL] 1 6 A, CY ← A – (HL) – CY × × ×
SUBC
A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY × × ×
A, #byte 2 4 A ← A ∧ byte ×
saddr, #by t e 3 6 (saddr) ← (s addr) ∧ byte ×
A, r 2 4 A ← A ∧ r×
A, saddr 2 4 A ← A ∧ (saddr) ×
A, !addr16 3 8 A ← A ∧ (addr16) ×
A, [HL] 1 6 A ← A ∧ (HL) ×
AND
A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×
Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control
register (PCC).