Alcatel 1964 TRX SDH / SONET integrated modules SERDES Transceiver STM-64 / OC-192 Description These SERDES Transceivers is intended to be used at 10 Gbit/s optical SDH and SONET bit rate and provide electrical accesses at lower 622 Mbit/s bit rate. The modules are housed in a space-saving 300-pin package, providing the same electrical access for overall applications. The transmitter side contains an in-house cooled EAILM laser with a laser driver and temperature control loop. The transmit path starts with 16 : 1 serializer Asic. The receiver contains an in-house III-V PIN detector with preamplifier in a front-end module, a main amplifier Asic, a clock and data recovery function with accurate decision circuit. The receive path ends with 1 : 16 deserializer Asic. The Alcatel 1964 TRX family is a range of SERDES transceivers modules, providing convenient and flexible optical interfaces for SDH / SONET systems operating at 9.96 Gbit/s and exceed the applicable ITU-T G.691, Telcordia GR-1377-Core and Optical Interworking Forum OIF99.102 standards. Features * New International Standard * Multisource Optical Interfaces * Upward compatibility with the different features * Applications: Intermediate-Reach (40 km) Short-Reach (20 km) * Optical 9.96 Gbit/s rate * Electrical 622 Mbit/s rate * Operating at 1.5 m wavelength * Full performance in operating case temperature from - 5 to + 65 C * Space-saving package 100 cm * Alcatel Reliability and Qualification Program for built in quality Transmitter: * EA-ILM 1.5 cooled laser * Up to +2 dBm optical output * 16x2 input data 622 Mbit/s LVDS * 1x2 ref. clock 155 or 622 MHz PECL compatible * Shut down command * Analog monitoring alarms * Power supplies: +5 V, - 5 V & + 3.3 V * Power consumption: 4.2 W typical Receiver: * InGaAs PIN-preamp detector * High typical sensitivity - 15 dBm * 16x2 output data 622 Mbit/s LVDS * 1x2 ref. clock 155 MHz PECL compatible * Analog monitoring alarms * Power supplies: +5 V, - 5 V & + 3.3 V * Power consumption: 2.8 W typical Applications Used in transmission systems from high-speed for intermediate-reach to long-reach applications, the Alcatel 1900 TRX family operates at SONET OC-192 rates as well as at ITU-T SDH STM-64 rates. Covering all types of SDH / SONET optical interfaces (tributaries and aggregates) the Alcatel 1900 TRX modules are suitable for line systems, Add Drop Multiplexers and digital cross-connects as well as ATM or IP switches and routers. As part of the global Alcatel 1900 TRX family, the Alcatel 1964 TRX ShortHaul module is the first version for all types of STM-64 (Very Short Reach, Intra-office, Short-Haul and Long-Haul) and OC-192 (Very Short Reach, ShortReach, Intermediate-Reach and LongReach) optical interfaces. These modules ensure ease of use and offer new flexibility to get 10 Gbit/s optical links to system designers. Optical characteristics Condition Target distance Optical budget Dispersion Path penalty Transmitter Center wavelength Optical output power Spectral width SMSR Extinction ratio Shutdown optical power Generated jitter Return loss Receiver Receiver sensitivity Receiver overload Generated jitter Reflectance Symb Note 1 Note 1 Note 1 Note 3 Note 4 Note 5 c SNOM Er SIDLE Min Typ Max I-64.2 / SR-2 20 0 6 400 1 2 1530 -4 30 8.2 1550 -2 10 -50 Note 2 Note 6 Note 6 Note 2 RNOM RNOM - 12 0 1565 0 1 Min Typ Max S-64.2 / IR-2 40 5 11 800 1.2 2 1530 -1 30 8.2 -40 0.1 24 - 13 - 14 -3 1550 0 10 -50 1565 +2 1 Km dB ps/nm dB -40 0.1 24 nm dBm nm dB dB dBm UIpp dB 0.1 - 27 dBm dBm UIpp dB - 15 0.1 - 27 Unit Note 1: Optical budgets are defined based on Telcordia GR-1377-Core & ITU-T G.691. Note 2: From 50 kHz to 80 MHz bandwidth and no jitter on TxREFCLK. Note 3: Measured at connector interface. Note 4: The maximum full width of the central wavelength peak; measured 20 dB down from the maximum amplitude under modulation condition NRZ at 9.95328 Gbit/s and PRBS 223-1. Note 5: Measured at connector interface under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1. Note 6: Measured at BER 10-12 and under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1 All parameters are specified End-of-Life within the overall relevant operating temperature range. The typical values are referenced to + 25 C, nominal power supply, beginning of life. Electrical characteristics Parameter Negative supply voltage Negative supply current 1st Positive supply voltage 1st Positive supply current 2nd Positive supply voltage 2nd Positive supply current Power dissipation Common mode LVDS input voltage Differential LVDS input swing LVDS output differential voltage LVDS differential input impedance LVTTL input low voltage LVTTL input high voltage LVTTL input low current LVTTL input high current LVTTL output low voltage LVTTL output high voltage LVPECL differential input voltage swing Condition Symbol VEE IEE VDD IDD VCC ICC Min - 4.94 LVDSVI LVDSVIDTH LVDSVOD LVDSRIN LVTTLVIL LVTTLVIH LVTTLIIL LVTTLIIH LVTTLVOL LVTTLVOH LVPECL VDIF 800 100 250 80 0 2.0 -500 3.13 4.75 Total Note 7 VIN = 0.5 V VIN = 2.4 V IOL = 4 mA IOH = -100 A Note 8 Typical - 5.2 900 3.3 760 5.0 130 7.0 Max - 5.45 1300 3.47 2000 5.25 200 14 1700 600 120 0.8 3.3 50 0.6 2.2 300 930 Unit V mA V mA V mA W mV mV mVpp V V A A V V mV Note 7: Peak to peak single ended voltage. Note 8: Internally AC coupled All parameters are specified End-of-Life within the overall relevant operating temperature range. The typical values are referenced to + 25 C, nominal power supply, beginning of life. Outline drawing Framer to Transceiver clocking Clocking definition TxREFCLK STM-64/OC-192 SERDES TRX SDH/SONET Framer TxREFCLK Transmitter Reference Clock Input: Differential clock PECL compatible input, internally AC coupled with 50 terminated. TxDin Transmitter Parallel Data Input: Differencial 622 Mbit/s LVDS input, internally 100 differential terminated. TxPICLK Transmitter Reference Parallel Clock Input: Differencial clock LVDS input, internally 100 differential terminated. TxPCLK Transmitter Reference Parallel Clock Output: Differencial clock LVDS output. RxDout Receiver Parallel Data Output: Differencial 622 Mbit/s LVDS output. RxPIOLK Receiver Reference Parallel Clock Output: Differential clock LVDS output. RxREFCLK Receiver Reference Clock Input: Differencial clock PECL compatible input. TxDin TxPICLK TxPCLK RxDout RxPOCLK RxREFCLK Pin out from customer line card K 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 H G F Rx+5VA Rx+5VA FFU Rx3.3VA Rx3.3VA RxRESET TBD TBD FFU Rx-5.2VA Rx-5.2VA FFU Rx-5.2VA Rx-5.2VA FFU FFU TBD NUC TBD TBD NUC TBD TBD NUC TBD TBD NUC TBD FFU NUC FGND FGND TBD FGND FGND TBD RxAGND RxAGND TBD RxAGND RxAGND TBD RxAGND RxAGND TBD RxDout12P RxDout12N RxDigGND RxDout13P RxDout13N RxDigGND RxDout14P RxDout14N RxDigGND RxDout15P RxDout15N RxDigGND TBD TBD RxDigGND FFU FFU Tx+5VA Tx+5VA FFU Tx3.3VA Tx3.3VA FFU Tx3.3VA Tx3.3VA TxRESET Tx-5.2VA Tx-5.2VA FFU Tx-5.2VA Tx-5.2VA FFU FFU TBD NUC TBD TBD NUC TBD TBD NUC TBD TBD NUC FFU FFU NUC TxAGND TxAGND FFU TxAGND TxAGND FFU TxAGND TxAGND FFU FGND FGND TBD FGND FGND FFU TxDin12P TxDin12N TxDigGND TxDin13P TxDin13N TxDigGND TxDin14P TxDin14N TxDigGND TxDin15P TxDin15N TxDigGND TxPICLKP TxPICLKN TxDigGND Receiver power & GND supplies Receiver d.c. signals 622 differential signals Receiver pin description RxDout##P RxPOCLKN RxREFCLKP C B A Rx3.3VD Rx3.3VD FFU Rx3.3VD Rx3.3VD FFU Rx-5.2VD Rx-5.2VD FFU Rx-5.2VD Rx-5.2VD NIC RxDout4P RxDout4N RxDigGND RxDout5P RxDout5N RxDigGND RxDout6P RxDout6N RxDigGND RxDout7P RxDout7N RxDigGND RxMCLKP RxMCLKN RxDigGND RxDigGND RxDigGND TBD RxDigGND RxDigGND FFU RxDigGND RxDigGND RxLCKREFN RxDigGND RxDigGND FFU RxDigGND RxDigGND RxLOCKERR RxDout0P RxDout0N RxDigGND RxDout1P RxDout1N RxDigGND RxDout2P RxDout2N RxDigGND RxDout3P RxDout3N RxDigGND RxREFCLKP RxREFCLKN RxDigGND FFU FFU LsBIASMON Tx3.3VD Tx3.3VD LsENABLE Tx3.3VD Tx3.3VD LsBIASALM Tx-5.2VD Tx-5.2VD LsTEMPALM Tx-5.2VD Tx-5.2VD TxREFSEL0 TxDin8P TxDin8N TxDigGND TxDin9P TxDin9N TxDigGND TxDin10P TxDin10N TxDigGND TxDin11P TxDin11N TxDigGND TxPCLKP TxPCLKN TxDigGND TxDigGND TxDigGND LsPOWMON TxDigGND TxDigGND LsTEMPMON TxDigGND TxDigGND NIC TxDigGND TxDigGND NIC TxDigGND A TxDigGND FFU TxDin4P TxDin4N TxDigGND TxDin5P TxDin5N TxDigGND TxDin6P TxDin6N TxDigGND TxDin7P TxDin7N TxDigGND Tx155MCKP Tx155MCKN TxDigGND TxDigGND TxDigGND TxSKEWSEL0 TxDigGND TxDigGND TxSKEWSEL1 TxDigGND TxDigGND TxPCLKSEL TxDigGND TxDigGND TxPICLKSEL TxDigGND TxDigGND TxLOCKERR TxDin0P TxDin0N TxDigGND TxDin1P TxDin1N TxDigGND TxDin2P TxDin2N TxDigGND TxDin3P TxDin3N TxDigGND TxREFCLKP TxREFCLKN TxDigGND NUC TBD FFU NIC No User Connection To Be Determined (spare) RxLOPMON Transmitter power & GND supplies Transmitter d.c. signals 622 differential signals RxREFCLKN Receiver NRZ Data Output Positive: 622 Mbit/s LVDS output signal. Data are RxMCLKP synchronized at the output of the module with the output clock RxPOCLK signal. RxDout15 is the most significant RxMCLKN bit and first bit received. Receiver Parallel Output Clock Positive: 622 MHz LVDS output. Regenerated clock synchronized to the data. The falling edge of RxRESET RxPOCLKP is in the middle of the data pattern. Receiver Parallel Output Clock Negative: 622 MHz output RxLOPMon signal. Regenerated clock synchronized to the data. The rising edge of RxPOCLKN is in the middle of the data pattern. Receiver Reference Clock Positive: 155 MHz PECL, compatible, internally AC coupled 50 terminated. D RxDigGND RxDigGND TBD RxDigGND RxDigGND TBD RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDigGND RxDigGND FFU RxDout##N Receiver NRZ Data Output Negative: 622 Mbit/s LVDS output signal. Data are RxLCKREF synchronized at the output of the module with the output clock RxPOCLK signal. RxDout15 is the most significant bit and first bit received. RxPOCLKP E RxDout8P RxDout8N RxDigGND RxDout9P RxDout9N RxDigGND RxDout10P RxDout10N RxDigGND RxDout11P RxDout11N RxDigGND RxPOCLKP RxPOCLKN RxDigGND Transmitter 2 J Receiver 1 Reserve For Future Use No Internal Connection Receiver Reference Clock Negative: 155 MHz PECL , compatible, internally AC coupled 50 terminated. RxLOCKERR Receiver Loss of Clock Error: LVTTL output alarm. Set to logic low when the clock recovery is not locked onto the optical data stream. Set to logic high in Receiver Monitor Clock Positive: normal operation. 622 MHz LVDS output signal. FFU Reserve For Future Use. This signal represents the PLL VC0 clock. TBD To Be Determined. Receiver Monitor Output Clock NUC Negative: 622 MHz LVDS NIC output signal. This signal represents the PLL VC0 clock. Receiver Lock Clock Reference: LVTTL input command. Selects the reference frequency mode of RxPOCLK. When is at logic low, the RxPOCLK is forced to lock to the RxREFCLK. When at logic high, the RxPOCLK is locked to the CDR reference clock. Receiver deserializer RESET: LVTTL input command. When at logic low, the deserializer function is reinitialized. Receiver Loss of Power Monitoring: analog output monitor. This voltage is proportional to the mean optical input power. Typical slope is 0.5 V / mW from guaranteed overload to guaranteed sensitivity. No User Connection. No Internal Connection Transmitter pin description TxDin##P TxDin##N TxPICLKP TxPICLKN TxPCLKP TxPCLKN TxREFCLKP TxREFCLKN Transmitter NRZ Data Input Positive: 622 Mbit/s LVDS input signal. Data are retimed at the input of the module by the input clock TxPICLK signal. TxDin15 is the most significant and the first bit transmitted TxMCLKP Transmitter NRZ Data Input Negative: 622 Mbit/s LVDS input signal. Data are retimed at the input of the module by the input clock TxPICLK signal. TxMCLKN TxDin15 is the most significant and the first bit transmitted. Transmitter Parallel Input Clock Positive: 622 MHz or 311 MHz LVDS input signal. When TxPICLKSEL TxPICLKSEL is at logic low, the frequency has to be 622 MHz and the rising edge of TxPICLKN is in the middle of the data pattern. When TxPICLKSEL is at logic high, the frequency has to be 311 MHz and the rising/falling edges of TxREFSEL0 TxPICLKN are in the middle of the data crossing point. Transmitter Reference Clock LsTEMPALM Laser Temperature Alarm: Negative: 622 MHz or 155 LVTTL output alarm. When at MHz PECL compatible input logic low, the laser temperature signal. When TxREFSEL0 is at is approximately 3C above or logic low, the frequency is 155 below the normal operating. MHz. When RxREFSEL0 is at When at logic high, the laser is logic high, the frequency is 622 in normal operating. MHz. LsBIASMon Laser Bias Monitoring: analog Transmitter Monitor Clock output monitor. This voltage is Positive: 155 MHz LVDS clock proportional to the laser output signal. This signal current. The typical slope is 20 represents the synthesized mV / mA. frequency of the serializer. LsPOWMon Laser Power Monitoring: Transmitter Monitor Clock Negative: 155 MHz LVDS clock output signal. This signal represents the synthesized frequency of the serializer. analog output monitor. This voltage is proportional to the laser output power. Normalized at 0.5 V at the beginning of life, the 50 % drift in output power correlates to a 50 % variation in output voltage. Transmitter Parallel Clock Select: LVTTL input command. Selects the reference frequency LsTEMPMon Laser temperature Monitoring: mode of TxPICLK. When at analog output monitor. This logic low, the frequency has to voltage represents the laser be 622 MHz. When at logic temperature deviation. high, the frequency has to be Normalized at the beginning of 311 MHz. life to 0.5 V at 25 C. Transmitter Reference clock Select 0: LVTTL input command. Selects the reference frequency mode of TxREFCLK. When at logic low, the frequency is 155 MHz. When at logic high, the frequency is 622 MHz. FFU TBD Transmitter Parallel Input Clock NUC Negative: 622 MHz or 311 MHz LVDS input signal. When TxPICLKSEL is at logic low, the NIC frequency has to be 622 MHz and the falling edge of TxSKEWSEL0 Transmitter Adjusts Skew of TxPICLKN is in the middle of TxPICLK Select: LVTTL input the data pattern. When command. This LSB digital logic TxPICLKSEL is at logic high, the input allows delaying internally frequency has to be 311 MHz the TxPICLK in the 311 MHz and the falling edge of mode. TxPICLKN is in the middle of TxSKEWSEL1 Transmitter Adjusts Skew of the data crossing point. TxPICLK Select: LVTTL input Transmitter Parallel Clock command. This MSB digital output Positive: 622 MHz LVDS logic input allows delaying output signal. Reference clock internally the TxPICLK in the generated from the TxREFCLK 311 MHz mode. signal. Usable to synchronize TxRESET Transmitter serializer RESET: the output data stage of the LVTTL input command. When framer ASIC. at logic low, the serializer Transmitter Parallel Clock function is reinitialized. output Negative: 622 MHz Laser Enable: LVTTL input LVDS output signal. Reference LsENABLE command. When at logic high, clock generated from the the laser is disabled. When at TxREFCLK signal. Usable to logic low, the laser is enabled. synchronize the output data stage of the framer ASIC. TxLOCKERR Transmitter Lock Error: LVTTL output alarm. When at logic Transmitter Reference Clock low, it indicates that the Positive: 622 MHz or 155 MHz serializer is not locked on the PECL compatible input signal. TxREFCLK. When at logic high, When TxREFSEL0 is at logic the serializer is in normal low, the frequency is 155 MHz. operating. When RxREFSEL0 is at logic high, the frequency is 622 LsBIASALM Laser Bias Alarm: LVTTL output MHz. alarm. When at logic low, the laser has reached its end of life condition. When at logic high, the laser is in normal operating. Reserved for further additional features. To be defined. No User Connection. This pin has to be left open. No Internal Connection. Allows optional feature. September 2000 Copyright (c) 2000 Alcatel Optronics Absolute maximum ratings Parameter Symbol Maximum optical output power Maximum optical input power Negative supply voltage VEE 1st Positive supply voltage VDD 2nd Positive supply voltage VCC Control input voltage Digital output voltage Analog output voltage Alarm output voltage Storage temperature TSTG Storage 72h max Operating case temperature TOP Min TBD -6 0 0 0 0 0 0 - 20 - 40 -5 Max +2 0 + 3.6 +6 VDD VDD VDD VDD + 70 + 85 + 65 Unit mW dBm V V V V V V V C C C Customized versions are available for large quantities. Performance figures contained in this document must be specifically confirmed in writing by Alcatel Optronics before they become applicable to any particular order or contract. Alcatel Optronics reserves the right to make changes to the products or information contained herein without notice. Ordering information Alcatel 1964 TRX I-64.2 / SR-2 S-64.2 / IR-2 Options 3CN xxxxx Dispersion (ps/nm) 400 800 xA FC/PC xB SC/PC Span (km) 20 40 Part Number 3CN 00468 AA 3CN 00434 AA Ax With heat sink Bx Without heat sink Standards Compliant with ITU-T G.691 Telcordia GR-1377-CORE Optical Interworking Forum OIF99.102 Optical fiber according to ITU-T G.652 Environment according to IEC 68-2 and MIL STD 883 Telcordia TR-EOP-000063 LASER RADIATION AVOID EXPOSURE TO BEAM Class 1 laser product ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC DISCHARGE SENSITIVE DEVICES EUROPE Route de Villejust F-91625 NOZAY CEDEX Tel : (+33) 1 64 49 49 10 Fax : (+33) 1 64 49 49 61 USA 12030 Sunrise Valley Drive RESTON - VA 22091-3495 Tel : (+1) 703 715 3922 Fax : (+1) 703 860 1183 CANADA 45, De Villebois, suite 200 Gatineau (PQ) Canada, J8T 8J7 Tel : (+1) 703 715 3922 Fax : (+1) 703 860 1183 JAPAN Dai-Tokyo Kasai Shinjuku Building 13F 3-25-3, Yoyogi, Shibuya-Ku TOKYO 151 - 0053 Tel : (+81) 3 5302 4341 Fax : (+81) 3 5302 4331