Note: Tab is GND for both packages
1
KTT PACKAGE
(TOP VIEW)
2 3 4 5
ENABLE
IN
GND
OUT
DDPAK
RESET
1
2
3
4
5
DCQ PACKAGE
OUT
GND
IN
ENABLE
SOT223-5
(TOP VIEW)
RESET
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
LOW INPUT VOLTAGE,
1-A LOW-DROPOUT LINEAR REGULATORS
WITH SUPERVISOR
Check for Samples: TPS726126,TPS72615,TPS72616,TPS72618,TPS72625
1FEATURES DESCRIPTION
• 1-A Low-Dropout Regulator Supports Input
Voltages Down to 1.8-V The TPS726xx family of 1-A low-dropout (LDO) linear
regulators has fixed voltage options available that are
• Available in 1.26-V, 1.5-V, 1.6-V, 1.8-V, 2.5-V commonly used to power the latest DSPs, FPGAs,
• Stable With Any Type/Value Output Capacitor and microcontrollers. The integrated supervisory
• ±2% Output Voltage Tolerance Over Line, circuitry provides an active low RESET signal when
Load, and Temperature (–40°C to +125°C) the output falls out of regulation. The no
capacitor/any capacitor feature allows the customer
• Integrated Supervisor (SVS) With 200-ms to tailor output transient performance as needed.
RESET Delay Time Therefore, compared to other regulators capable of
• Low 170-mV Dropout Voltage at 1 A providing the same output current, this family of
(TPS72625) regulators can provide a stand alone power supply
• Low 210-mA Ground Current at Full Load solution or a post regulator for a switch mode power
supply.
• Less than 1-mA Standby Current
• Integrated UVLO with Thermal and These regulators operate over a wide range of input
voltages (1.8 V to 6 V) and have very low dropout
Overcurrent Protection (170 mV at 1-A). Ground current is typically 210 µA at
• 5-Lead SOT223 or DDPAK Surface-Mount full load and drops to less than 80 µA at no load.
Package Standby current is less than 1 µA.
Unlike some regulators that have a minimum current
APPLICATIONS requirement, the TPS726xx family is stable with no
• PCI Cards output load current. The low noise capability of this
• Modem Banks and Telecom Boards family, coupled with its high current operation and
• DSP, FPGA, and Microprocessor Power ease of power dissipation, make it ideal for telecom
Supplies boards, modem banks, and other noise sensitive
• Portable, Battery-Powered Applications applications.
• 1.26-V Core Voltage for the Following DSPs: The TPS726xx is available in either a SOT223 or
– TMS320vC5501 DDPAK package. The TPS726126 is available in a
SOT223 package only.
– TMS320vC5502
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
TPS726xx xyyy zXXX is nominal output voltage (for example, 126 = 1.26V, 15 = 1.5V).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Input voltage, VI(2) –0.3 to 7 V
Voltage range at EN –0.3 to VI+ 0.3 V
Voltage on RESET VIN + 0.3 V
Voltage on OUT 6 V
ESD rating, HBM 2 kV
Continuous total power dissipation See Dissipation Rating Table
Operating junction temperature range, TJ–50 to 150 °C
Maximum junction temperature range, TJ150 °C
Storage temperature, Tstg –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE BOARD RqJC RqJA
DDPAK High K(1) 2 °C/W 23 °C/W
SOT223 Low K(2) 15 °C/W 53 °C/W
(1) The JEDEC high K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.
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Line regulation (mV) +(%ńV) VOǒ5.5 V *VIminǓ
100 1000
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range VI= VO(typ) + 1 V, IO= 1 mA, EN = IN, CO= 1 µF, CI= 1 µF (unless
otherwise noted). Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI(1) Input voltage 1.8 6 V
IOContinuous output current 0 1 A
Bandgap voltage reference 1.177 1.220 1.263 V
TPS726126 0 µA < IO< 1 A 1.8 V ≤VI≤5.5 V 1.222 1.26 1.298
TPS72615 0 µA < IO< 1 A 1.8 V ≤VI≤5.5 V 1.47 1.5 1.53
VOOutput voltage TPS72616 0 µA < IO< 1 A 2.6 V ≤VI≤5.5 V 1.568 1.6 1.632 V
TPS72618 0 µA < IO< 1 A 2.8 V ≤VI≤5.5 V 1.764 1.8 1.836
TPS72625 0 µA < IO< 1 A 3.5 V ≤VI≤5.5 V 2.45 2.5 2.55
IO= 0 µA 75 120
I Ground current µA
IO= 1 A 210 300
Standby current EN < 0.4 V 0.2 1 µA
VnOutput noise voltage BW = 200 Hz to 100 kHz CO= 10 µF 150 µV
PSRR Ripple rejection f = 1 kHz, Co= 10 µF 60 dB
Current limit(2) 1.1 1.6 2.3 A
Output voltage line regulation VO+ 1 V < VI≤5.5 V –0.15 0.02 0.15 %/V
(ΔVO/VO)(3)
Output voltage load regulation 0 µA < IO< 1 A –0.25 0.05 0.25 %/A
VIH EN high level input 1.3 V
VIL EN low level input –0.2 0.4
IIEN input current EN = 0 V or VI0.01 100 nA
UVLO threshold VCC rising 1.45 1.57 1.70 V
UVLO hysteresis VCC rising 50 mV
UVLO deglitch VCC rising 10 µs
UVLO delay VCC rising 100 µs
TPS72625 IO= 1 A 170 280
VDO Dropout voltage (4) mV
TPS72618 IO= 1 A 210 320
Minimum input voltage for valid 1.3 V
RESET (VRES)
Trip threshold voltage 90 93 96 %VO
Hysteresis voltage 10 mV
RESET t(RESET) delay time 100 200 300 ms
Rising edge deglitch 10 µs
Output low voltage (at 700 µA) –0.3 0.4 V
Leakage current 100 nA
TJOperating junction temperature –40 +125 °C
(1) Minimum VIN is 1.800 V or VO+ VDO, whichever is greater.
(2) Test condition includes, output voltage VO= VO– 15% and pulse duration = 10 ms.
(3) VImin = (VO+ 1) or 1.8 V whichever is greater.
(4) Dropout voltage is defined as the differential voltage between VOand VIwhen VOdrops 100 mV below the value measured with
VI= VO+ 1 V.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
TPS726126/15/16
OUT
IN
GND
EN
Vref
Current Limit
/ Thermal
Protection
0.93 × Vref
Deglitch
and
Delay
RESET
1.220
NOTES:A. VRES is the minimum input voltage for a valid RESET.
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
IN
VRES
(see Note A) VRES
t
t
t
OUT
Threshold
Voltage
RESET
Output 200 ms
Delay 200 ms
Delay
Output
Undefined
Output
Undefined
VIT+
VIT−
VIT+
VIT−
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Terminal Functions
TERMINAL DESCRIPTION
NAME NO.
GND 3 Ground
ENABLE 1 Enable input
IN 2 Input supply voltage
RESET 5 This terminal is the RESET output. When used with a pull-up resistor, this open-drain output provides the active low
RESET signal when the regulator output voltage drops more than 5% below its nominal output voltage. The RESET
delay time is typically 200 ms.
OUT 4 Regulated output voltage
RESET TIMING DIAGRAM
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1.785
1.795
1.805
−40−25−10 5 20 35 50 65 80 95 110 125
1.790
1.800
VI = 2.8 V
Co = 1 µF
TJ − Junction Temperature − °C
− Output Voltage − V
VO
IO = 1 A
IO = 0 mA
0 0.2 0.4 0.8
IO − Output Current − A
− Output Voltage − V
VO
10.6
VI = 2.8 V
Co = 1 µF
TJ = 25° C
1.7985
1.799
1.7995
1.8
1.8005
1.801
1.8015
0
50
100
150
200
250
−40−25−10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Ground Current − Aµ
IO = 0 mA
VI = 2.8 V
Co = 1 µF
TJ = 25° CIO = 1 A
−40−25−10 5 20 35 50 65 80 95 110 125
IO = 1 A
IO = 10 mA
VO = 1.7 V
Co = 1 µF
TJ − Junction Temperature − °C
− Dropout Voltage − mV
VDO
0
50
100
150
200
250
300
0
25
50
75
100
125
150
175
200
0.01 0.1 1 10 100 1000
IO − Output Current − mA
Ground Current − Aµ
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
TYPICAL CHARACTERISTICS
TPS72618 TPS72618
TPS72618 OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS72618 TPS72625 TPS72618
GROUND CURRENT DC DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
VO = 2.8 V
Co = 10 µF
Ci = 1 µF
− Output Current − AOutput Voltage − mV
VO
∆
IO
− Change in
t − Time − µs
0 5 10 15 20 25 30 35 40 45 50
0
0.5
1
−100
0
100
t − Time − µs
100
−100
0 50 100 150 200 250 300
2.8
350 400 450 500
3.8
0
IO = 1 A
Co = 10 µF
− Input Voltage − V− Output Voltage − mVVOVI
1.5
2
2.5
3
3.5
4
4.5
1.5 2 2.5 3 3.5 4 4.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
− Minimum Required Input Voltage − V
VO − Output Voltage − V
VI
IO
t − Time − µs
0 15105 20 25 3530 40 45 50
− Output Current − A
VI = 2.8 V
Co = 1 µF
CI = 1 µF
1
0.5
0
−100
100
0
Output Voltage − mV
VO
∆− Change in
160
2
VO
t − Time − µs
0 604020 80 100 140120 180 200
− Output Voltage − V
VI = 2.8 V
IO = 1 A
Co = 10 µF
Enable Voltage − V
1
1
0
0
1.5
2
3
0.5
t − Time − µs
1
0 100 200 300 400 500 600
− Input Voltage − V
3
700 800 900 1000
5
0
− Output Voltage − VVOVI
4
2
VO
VI
RL = 1.8 Ω
Co = 1 µF
Ci = 1 µF
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
MINIMUM REQUIRED
INPUT VOLTAGE TPS72618 TPS72618
vs LINE TRANSIENT LOAD TRANSIENT
OUTPUT VOLTAGE RESPONSE RESPONSE
Figure 7. Figure 8. Figure 9.
TPS72618
OUTPUT VOLTAGE,
ENABLE VOLTAGE
TPS72618
LOAD TRANSIENT vs TPS72618
RESPONSE TIME (START-UP) POWER UP/POWER DOWN
Figure 10. Figure 11. Figure 12.
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0
0.5
1
1.5
2
2.5
3
3.5
10 100 1 k 10 k 100 k
f − Frequency − Hz
IO = 1 mA
VI = 2.8 V
Co = 10 µF
IO = 1 A
V/ HzOutput Spectral Noise Density − µ
50
30
20
010 100 1 k 10 k
Ripple Rejection − dB
70
90
f − Frequency − Hz
100
100 k 1 M
80
60
40
10
10 µF / 1mA
10 µF / 1A
VI= 2.8 V,
VO = 1.8 V,
CO = 10 µF
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
TJ = 25°C
VI − Input voltage − V
Current Limit − A
TJ = −40°C
TJ = 125°C
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VI − Input Voltage − V
− Dropout Voltage − mV
VDO
TJ = 25°C
TJ = −40°C
TJ = 125°C
0
100
200
300
400
500
600
0123456
I = 0 A
VI − Input Voltage − V
Ground Current − Aµ
I = 1 A
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
TYPICAL CHARACTERISTICS (continued)
TPS72618
OUTPUT SPECTRAL NOISE TPS72618
DENSITY RIPPLE REJECTION CURRENT LIMIT
vs vs vs
FREQUENCY FREQUENCY INPUT VOLTAGE
Figure 13. Figure 14. Figure 15.
TPS72615
GROUND CURRENT DROPOUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 16. Figure 17.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
VO
VIOUT
RESET
10kW
GND
EN
IN
TPS726xx
1mF
CO
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
APPLICATION INFORMATION
The TPS726xx family of low-dropout (LDO) regulators have numerous features that make it apply to a wide
range of applications. The family operates with very low input voltage (≥1.8 V) and low dropout voltage (typically
200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode
power supplies. Both the active low RESET and 1-A output current, make the TPS726xx family ideal for
powering processor and FPGA supplies. The TPS726xx family also has low output noise (typically 150 µVRMS
with 10-µF output capacitor), making it ideal for use in telecom equipment.
External Capacitor Requirements
A 1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS726xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, an
additional 10-µF or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may be
necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the
power source, especially if the minimum input voltage of 1.8 V is used.
Although an output capacitor is not required for stability, transient response and output noise are improved with a
10-µF output capacitor.
Figure 18. TPS726xx Fixed Output Typical Application Diagram
Regulator Protection
The TPS726xx pass element has a built-in back diode that safely conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS726xx also features internal current limiting and thermal protection. During normal operation, the
TPS726xx limits output current to approximately 1.6 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the
device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below
145°C, regulator operation resumes. THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)
above which normal operation is not assured. A system designer must design the operating environment so that
the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two
main environmental variables that a designer can use to improve thermal performance are air flow and external
heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment
for a linear regulator that is operating at a specific power level.
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Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
PDmax +ǒVI(avg) *VO(avg)Ǔ IO(avg) )VI(avg)x I(Q)
A
B
C
TJ
A
RθJC
TC
B
RθCS
TA
C
RθSA
(a) (b)
DDPAK Package
SOT223 Package
CIRCUIT BOARD COPPER AREA
B
A
C
TJ+TA)PDmax x ǒRθJC )RθCS )RθSAǓ
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
(1)
Where:
• VI(avg) is the average input voltage.
• VO(avg) is the average output voltage.
•O(avg) is the average output current.
• I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the
ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case ®qJC), the case to heatsink ®qCS), and the heatsink to ambient
®qSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object's thermal resistance.
Figure 19 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and
(b) a DDPAK package mounted on a JEDEC high-K board.
Figure 19. Thermal Resistances
Equation 2 summarizes the computation:
(2)
The RqJC is specific to each regulator as determined by its package, lead frame, and die size provided in the
regulator's data sheet. The RqSA is a function of the type and size of heatsink. For example, black body radiator
type heatsinks can have RqCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small
heatsinks. The RqCS is a function of how the package is attached to the heatsink. For example, if a thermal
compound is used to attach a heatsink to a SOT223 package, RqCSof 1°C/W is reasonable.
Even if no external black body radiator type heatsink is attached to the package, the board on which the
regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the
DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane
for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used
to compute very accurate approximations of an integrated circuit's thermal performance in different operating
environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows,
etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between
junction and ambient ®qJA). This RqJAis valid only for the specific operating environment used in the computer
model.
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
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TJ+TA)PDmax x RθJA
RθJA +TJ–TA
PDmax
PDmax +(5*2.5)V x 1 A +2.5 W
RθJAmax +(125 *55)°Cń2.5 W +28°CńW
15
20
25
30
35
40
0.1 1 10 100
Copper Heatsink Area − cm2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
150 LFM
250 LFM
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
Equation 2 simplifies into Equation 3:
(3)
Rearranging Equation 3 gives Equation 4:
(4)
Using Equation 3 and the computer model generated curves shown in Figure 20 and Figure 23, a designer can
quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power
dissipation, and operating environment.
DDPAK Power Dissipation
The DDPAK package provides an effective means of managing power dissipation in surface mount applications.
The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the
package.
To illustrate, the TPS72625 in a DDPAK package was chosen. For this example, the average input voltage is 5
V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is
150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,
the maximum average power is:
(5)
Substituting TJmax for TJinto Equation 4 gives Equation 6:
(6)
From Figure 20,DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm2for
the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 20
consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The
package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane.
Figure 21 shows the side view of the operating environment used in the computer model.
Figure 20. DDPAK Thermal Resistance vs Copper Heatsink Area
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Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
2 oz. Copper Solder Pad
with 25 Thermal Vias
Thermal Vias, 0,3 mm
Diameter, 1,5 mm Pitch
− Maximum Junction Temperature − 125
TJM C
°
1
2
3
4
5
0.1 1 10 100
− Maximum Power Dissipation − W
PD
Copper Heatsink Area − cm2
TA = 55°C
No Air Flow
150 LFM
250 LFM
PDmax +(3.3 *2.5)V x 1 A +800 mW
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
Figure 21. DDPAK Thermal Resistance
From the data in Figure 22 and rearranging Equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed.
Figure 22. Maximum Power Dissipation vs Copper Heatsink Area
SOT223 Power Dissipation
The SOT223 package provides an effective means of managing power dissipation in surface mount applications.
The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the
package.
To illustrate, the TPS72625 in a SOT223 package was chosen. For this example, the average input voltage is
3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow is
present, and the operating environment is the same as documented below. Neglecting the quiescent current, the
maximum average power is:
(7)
Substituting TJmax for TJinto Equation 4 gives Equation 8:
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RθJAmax +(125 *55)°Cń800 mW +87.5°CńW
0
100
120
140
160
180
PCB Copper Area − in2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
80
60
40
20
0.1 1 10
0
1
2
3
6
0 25 50 75 100 150
− Maximum Power Dissipation − W
PD
125
TA = 25°C
TA − Ambient Temperature − °C
4
5
4 in2 PCB Area
0.5 in2 PCB Area
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
SLVS403H –MAY 2002–REVISED JUNE 2010
www.ti.com
(8)
From Figure 23,RqJA vs PCB Copper Area, the ground plane needs to be 0.55 in2for the part to dissipate 800
mW. The operating environment used to construct Figure 23 consisted of a board with 1 oz. copper planes. The
package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1
oz. ground plane.
Figure 23. SOT223 Thermal Resistance vs PCB AREA
From the data in Figure 23 and rearranging Equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed (as shown in Figure 24).
Figure 24. SOT223 Power Dissipation
12 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
TPS726126
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403H –MAY 2002–REVISED JUNE 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (May 2006) to Revision H Page
• Deleted Figure 14, Output Impedance vs Frequency ........................................................................................................... 7
• Added Figure 18 ................................................................................................................................................................... 8
Copyright © 2002–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS726126DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS726126DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS726126DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS726126DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72615DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72615DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72615DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72615DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72615KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72615KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72615KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72615KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72615KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72616DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72616DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72616DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72616DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS72616KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72616KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72616KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72616KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72616KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72618DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72618DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72618KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72618KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72618KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72618KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72618KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72625DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS72625KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72625KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72625KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72625KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72625KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS726126DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS72615DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS72615KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72615KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72616DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS72616KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72616KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72618DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS72618KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72618KTTT DDPAK/
TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72625DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS72625KTTR DDPAK/
TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TPS72625KTTT DDPAK/ KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TO-263
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS726126DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS72615DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS72615KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS72615KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS72616DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS72616KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS72616KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS72618DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS72618KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS72618KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
TPS72625DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS72625KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0
TPS72625KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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