128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Features DDR SDRAM Unbuffered DIMM MT8VDDT3232U - 128MB MT8VDDT6432U - 256MB MT8VDDT12832U - 512MB For DDR SDRAM component specifications, please refer to the Micron(R) Web site: www.micron.com/ Features Figure 1: * 100-pin, dual in-line memory module (DIMM) * Fast data transfer rate: PC2100 and PC2700 * Utilizes 266 MT/s or 333 MT/s DDR SDRAM components * 128MB (16 Meg x 32), 256MB (32 Meg x 32), 512MB (64 Meg x 32) * VDD = +2.5V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture * Differential clock inputs CK and CK# * Four internal device banks for concurrent operation * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Serial Presence Detect (SPD) with EEPROM * Programmable READ CAS latency * Auto Refresh and Self Refresh Modes * 15.625s (128MB), 7.8125s (256MB, 512MB) maximum average periodic refresh interval * Gold edge contacts * Dual rank pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_1.fm - Rev. G 5/05 EN 100-Pin DIMM (MO-161) Options * Package 100-pin DIMM (standard) 100-pin DIMM (lead-free)1 * Operating Temperature Range Commercial (ambient) Industrial (ambient) * Frequency/CAS Latency2 6ns/167 MHz (333MT/s) CL = 2.5 7.5ns/133 MHz (266 MT/s) CL = 2 7.5ns/133 MHz (266 MT/s) CL = 2.5 Marking G Y None I -6 -75Z1 -75 Notes: 1. Contact Micron for product availability. 2. CL = CAS (READ) latency. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Features Table 1: Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing Table 2: MT8VDDT3232U MT8VDDT6432U MT8VDDT12832U 4K 4K (A0-A11) 4 (BA0, BA1) 128Mb (16 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 8K (A0-A12) 4 (BA0, BA1) 256Mb (32 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 8K (A0-A12) 4 (BA0, BA1) 512Mb (64 Meg x 8) 1K (A0-A9, A11) 2 (S0#, S1#) Part Numbers and Timing Parameters Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Bit Rate Latency (CL - tRCD - tRP) 128MB 16 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT3232UG-6__ 128MB 16 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT3232UY-6__ 128MB 16 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT3232UG-75Z__ 128MB 16 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT3232UY-75Z__ 128MB 16 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT3232UG-75__ 128MB 16 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT3232UY-75__ 256MB 32 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT6432UG-6__ 256MB 32 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT6432UY-6__ 256MB 32 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT6432UG-75Z__ 256MB 32 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT6432UY-75Z__ 256MB 32 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT6432UG-75__ 256MB 32 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT6432UY-75__ 512MB 64 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT12832UG-6__ 512MB 64 Meg x 32 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT8VDDT12832UY-6__ 512MB 64 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT12832UG-75Z__ 512MB 64 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT8VDDT12832UY-75Z__ 512MB 64 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT12832UG-75__ 512MB 64 Meg x 32 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT8VDDT12832UY-75__ All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3232UG-75B1. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_1.fm - Rev. G 5/05 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Serial Presence-Detect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DLL Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Parameter Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Serial Presence Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UTOC.fm - Rev. G 5/05 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: 100-Pin DIMM (MO-161) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Module Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Extended Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Derating Data Valid Window tQH - t(DQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Acknowledge Response From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 100-Pin DIMM Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32ULOF.fm - Rev. G 5/05 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CAS Latency (CL) Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Commands Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DM Operation Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 IDD Specifications and Conditions - 128MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IDD Specifications and Conditions - 256MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 IDD Specifications and Conditions - 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Capacitance (All Modules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Component Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . .21 EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32ULOT.fm - Rev. G 5/05 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 3: Pin Assignment 100-Pin DIMM Front 100-Pin DIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 DQ0 VSS DQ1 DQS0 VDD DQ2 DQ3 VDD DQ8 DQ9 VSS DQS1 DQ10 14 15 16 17 18 19 20 21 22 23 24 25 VDD DQ11 VSS CK0 CK0# VDD CKE1 NC/A12 NC A9 A7 VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 A5 A3 A1 A10 VDD BA0 WE# S0# DQ16 VSS DQ17 DQS2 VDD 39 40 41 42 43 44 45 46 47 48 49 50 DQ18 DQ19 VDD DQ24 DQ25 VSS DQS3 DQ26 VSS DQ27 SA0 VREF 51 52 53 54 55 56 57 58 59 60 61 62 63 DQ4 VSS DQ5 DM0 VDD DQ6 DQ7 VDD DQ12 DQ13 VSS DM1 DQ14 64 65 66 67 68 69 70 71 72 73 74 75 VDD DQ15 VSS CK1 CK1# VDD CKE0 A11 A8 A6 A4 VSS 76 77 78 79 80 81 82 83 84 85 86 87 88 A2 A0 BA1 RAS# VDD CAS# S1# DNU DQ20 VSS DQ21 DM2 VDD 89 90 91 92 93 94 95 96 97 98 99 100 DQ22 DQ23 VDD DQ28 DQ29 VSS DM3 DQ30 VSS DQ31 SDA SCL Note: Figure 2: Pin 21 is No Connect for the 128MB module, or A12 for the 256MB or 512MB modules. Module Layout Back View Front View U1 U2 U3 U6 U4 U7 U8 U9 U5 PIN 1 PIN 23 PIN 50 PIN100 Indicates a VDD or VDDQ pin pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 6 PIN 73 PIN 51 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Pin Assignments and Descriptions Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Figure 3 on page 6 for more information Pin Numbers Symbol Type Description 32, 79, 81 WE#, CAS#, RAS# Input 17, 18, 67, 68 CK0, CK0#, CK1, CK1# Input 20, 70 CKE0, CKE1 Input 33, 82 S0#, S1# Input 31, 78 BA0, BA1 Input 21 (256MB, 512MB), 23, 24, 26-29, 71-74, 76, 77 A0-A11 (128MB) A0-A12 (256MB, 512MB) Input 4, 12, 37, 45 DQS0-DQS3 Input/ Output 54, 62, 87, 95 DM0-DM3 Input 1, 3, 6, 7, 9,10, 13, 15, 34, 36, 39, 40, 42, 43, 46, 48, 51, 53, 56, 57, 59, 60, 63, 65, 84, 86, 89, 90, 92, 93, 96, 98 49 DQ0-DQ31 Input/ Output Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWERDOWN (row ACTIVE in any device bank).CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Data Write Mask. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation. Data I/Os: Data bus. SA0 Input pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Pin Assignments and Descriptions Table 4: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Figure 3 on page 6 for more information Pin Numbers Symbol Type Description 99 SDA Input/ Output 100 SCL Input 50 5, 8, 14, 19, 30, 38, 41, 55, 58, 64, 69, 80, 88, 91 2, 11, 16, 25, 35, 44, 47, 52, 61, 66, 75, 85, 94, 97 83 VREF VDD Supply Supply Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. SSTL_2 reference voltage. Power Supply: +2.5V 0.2V. VSS Supply Ground. DNU -- 21 (128MB), 22 NC -- pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Do Not Use: This pin is not connected on these modules, but is an assigned pin on other modules in this product family. No Connect: These pins should be left unconnected. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Functional Block Functional Block All resistor values are 22 unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); and MT46V64M8TG (512MB). Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); and MT46V64M8TG (512MB). Figure 3: Functional Block Diagram S1# S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U8 DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ U4 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ DQS1 DM1 DQS2 DM2 DQS3 DM3 SPD RAS# RAS#: DDR SDRAMs CAS# CAS#: DDR SDRAMs CKE0 CKE0: DDR SDRAMs U1-U4 CKE1 CKE1: DDR SDRAMs U5-U8 WE# WE#: DDR SDRAMS VDD SPD A0-A11 (128MB) A0-A11: DDR SDRAMs VDD A0-A12 (256MB, 512MB) A0-A12: DDR SDRAMs DDR SDRAMs (VDD and VDDQ) DDR SDRAMs SCL WP U5 A1 A2 SA0 BA0 BA0: DDR SDRAMs VREF BA1 BA1: DDR SDRAMs VSS pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN A0 DDR SDRAMs, SPD 9 SDA 120 CK0 CK0# DDR SDRAM x4 120 CK1 CK1# DDR SDRAM x4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM General Description General Description The MT8VDDT3232U, MT8VDDT6432U, and MT8VDDT12832U are high-speed CMOS, dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in x32 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select devices bank; A0-A11 select device row for 128MB module, A0-A12 select device row for 256MB and 512MB modules). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access (BA0, BA1; A0-A9 for 128MB and 256MB, or A0-A9, A11 for 512MB). DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheets. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Mode Register Definition bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 12. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (128MB, 256MB) or A7- A12 (512MB) specify the operating mode. Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9 (128MB, 256MB) or A1-A9, A11 (512MB) when the burst length is set to two, by A2-A9 (128MB, 256MB) or A2-A9, A11 (512MB) when the burst length is set to four and by A3-A9 (128MB, 256MB) or A3-A9, A11 ( 512MB) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5, Burst Definition Table, on page 13. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram, on page 14. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Mode Register Definition If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 4: Mode Register Definition Diagram 128MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length 0* 0* Address Bus Mode Register (Mx) * M13 and M12 (BA1and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). 256MB, 512MB Module Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Mode Register (Mx) Burst Length M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Address Bus M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - 12 All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Mode Register Definition Table 5: Burst Definition Table Burst Length Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 2 4 A2 0 0 0 0 1 1 1 1 8 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Notes: 1. For a burst length of two, A1-Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-data-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (128MB, 256MB) i = 9, 11 (512MB) Table 6: CAS Latency (CL) Table Allowable Operating Clock Frequency (MHz) pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Speed CL = 2 CL = 2.5 -6 -75Z -75 75 f 133 75 f 133 75 f 100 75 f 167 75 f 133 75 f 133 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Extended Mode Register Figure 5: CAS Latency Diagram T0 T1 T2 READ NOP NOP T2n T3 T3n CK# CK COMMAND NOP CL = 2 DQS DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (128MB, 256MB), or A7-A12 (512MB) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (128MB, 256MB), or A7 and A9-A12 (512MB) each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11 (128MB, 256MB), or A7-A12 (512MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Extended Mode Register The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. Figure 6: Extended Mode Register Definition Diagram 128MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 01 11 8 7 6 5 4 Operating Mode 3 2 1 0 Address Bus Extended Mode Register (Ex) DS DLL 256MB and 512MB Modules Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 4 3 2 1 0 DS DLL Address Bus Extended Mode Register (Ex) E0 DLL 0 Enable 1 Disable E1 Drive Strength 0 Normal E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 Valid Normal Operation - - - - - - - - - - - All other states reserved Notes: 1. BA1 and BA0 (E13 and E12 for 128MB, or E14 and E13 for 256MB, 512MB) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. QFC# is not supported. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Commands Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet. Table 7: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved Name (Function) CS# RAS# H L L L L L L L L X H L H H H L L L DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CAS# WE# X H H L L H H L L X H H H L L L H L Address Notes X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 Notes: 1. DESELECT and NOP are functionally interchangeable. 2. BA0-BA1 provide device bank address and A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide row address. 3. BA0-BA1 provide device bank address; A0-A9 (128MB, 256MB) or A0-A9, A11 (512MB) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide the op-code to be written to the selected mode register. Table 8: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data Name (Function) WRITE Enable WRITE Inhibit pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 16 DM DQs L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Parameter Tables Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V Operating Temperature, TA (commercial - ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0C to +70C TA (industrial - ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Table 9: DC Electrical Characteristics and Operating Conditions Notes: 1-5, 14, 48; notes appear on pages 23-27; 0C TA +70C Parameter/Condition Symbol Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) VDD VDD VREF VTT VIH (DC) VIL (DC) Command/ Address, RAS#, CAS#, WE# CKE0, CKE1, S0#, S1# CK, CK# DM DQ, DQS OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDD) OUTPUT LEVELS High Current (VOUT = VDD-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) Table 10: Min Max 2.3 2.7 2.3 2.7 0.49 x VDD 0.51 x VDD VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -16 Units Notes V V V V V V 32 32, 39 6, 39 7, 39 25 25 A 47 16 II -8 8 IOZ -4 -10 4 10 A 47 IOH IOL -16.8 16.8 - - mA mA 33, 34 AC Input Operating Conditions Notes: 1-5, 14, 48, 49; notes appear on pages 23-27; 0C TA +70C; VDD = +2.5V 0.2V Parameter/Condition Symbol Min Max Units Notes Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage VIH (AC) VIL (AC) VREF (AC) VREF + 0.310 - 0.49 x VDD - VREF - 0.310 0.51 x VDD V V V 12, 25, 35 12, 25, 35 6 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Table 11: IDD Specifications and Conditions - 128MB DDR SDRAM components only Notes: 1-5, 14, 48; notes appear on pages 23-27; 0C TA +70C; VDD = +2.5V 0.2V Max Parameter/Condition Symbol -6 -75Z/ -75 Units Notes 512 432 mA 20, 42 IDD0a OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD1a 552 492 mA 20, 42 OPERATING CURRENT: One device bank; Active -Read Precharge; t t t t Burst = 2; RC = RC (MIN); CK = CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD2Pb 24 24 mA 21, 28, 44 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks t t idle; Power-down mode; CK = CK (MIN); CKE = (LOW) IDD2Fb 360 320 mA 45 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD3Pb 200 160 mA 21, 28, 44 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW 400 360 mA 41 IDD3Nb ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX);tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 572 512 mA 20, 42 IDD4Ra OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA 572 492 mA 20 IDD4Wa OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) IDD5b 2,120 1,760 mA 20, 44 AUTO REFRESH CURRENT tREFC = 15.625s IDD5Ab 40 40 mA 24, 44 IDD6b 24 16 mA 9 SELF REFRESH CURRENT: CKE 0.2V a DD7 1,432 1,312 mA 20, 43 I OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Table 12: IDD Specifications and Conditions - 256MB DDR SDRAM components only Notes: 1-5, 14, 48; notes appear on pages 23-27; 0C TA +70C; VDD = +2.5V 0.2V Max Parameter/Condition Symbol -6 -75Z/ -75 Units Notes 516 496 mA 20, 42 IDD0a OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD1a 696 596 mA 20, 42 OPERATING CURRENT: One device bank; Active -Read Precharge; t t t t Burst = 4; RC = RC (MIN); CK = CK (MIN); IOUT= 0mA; Address and control inputs changing once per clock cycle IDD2Pb 32 32 mA 21, 28, 44 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks t t idle; Power-down mode; CK = CK (MIN); CKE = (LOW) IDD2Fb 400 360 mA 45 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN= VREF for DQ, DQS, and DM IDD3Pb 240 200 mA 21, 28, 44 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW 480 400 mA 41 IDD3Nb ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 716 616 mA 20, 42 IDD4Ra OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA 716 616 mA 20 IDD4Wa OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) IDD5b 2,040 1,880 mA 20, 44 AUTO REFRESH CURRENT tREFC = 7.8125s IDD5Ab 48 48 mA 24, 44 IDD6b 32 32 mA 9 SELF REFRESH CURRENT: CKE 0.2V a DD7 1,656 1,416 mA 20, 43 I OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Table 13: IDD Specifications and Conditions - 512MB DDR SDRAM components only Notes: 1-5, 14, 48; notes appear on pages 23-27; 0C TA +70C; VDD = +2.5V 0.2V Max Parameter/Condition Symbol -6 -75Z/ -75 Units Notes 540 480 mA 20, 42 IDD0a OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD1a 660 600 mA 20, 42 OPERATING CURRENT: One device bank; Active -Read Precharge; t t t t Burst = 4; RC = RC (MIN); CK = CK (MIN); IOUT= 0mA; Address and control inputs changing once per clock cycle IDD2Pb 40 40 mA 21, 28, 44 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks t t idle; Power-down mode; CK = CK (MIN); CKE = (LOW) IDD2Fb 360 320 mA 45 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN= VREF for DQ, DQS, and DM IDD3Pb 280 240 mA 21, 28, 44 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW 400 360 mA 41 IDD3Nb ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 680 600 mA 20, 42 IDD4Ra OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA 720 560 mA 20 IDD4Wa OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) IDD5b 2,320 2,240 mA 20, 44 AUTO REFRESH CURRENT tREFC = 7.8125s IDD5Ab 80 80 mA 24, 44 IDD6b 40 40 mA 9 SELF REFRESH CURRENT: CKE 0.2V a DD7 1,640 1,420 mA 20, 43 I OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands a: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b: Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Table 14: Capacitance (All Modules) Note: 11; notes appear on pages 23-27 Parameter Symbol Min Max Units CIO CI1 CI2 8 16 8 10 24 12 pF pF pF Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#; CK/CK#; CKE Table 15: Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1-5, 12-15, 29, 48; notes appear on pages 23-27; 0C TA +70C; VDD = +2.5V 0.2V AC Characteristics -6 Parameter Access window of DQ from CK/CK# CK high-level width CK low-level width Clock cycle time Min Max Min Max tAC (2.5) (2) tDH -0.7 0.45 0.45 6 7.5 0.45 +0.7 0.55 0.55 13 13 -0.75 0.45 0.45 7.5 7.5/10 0.5 +0.75 0.55 0.55 13 13 tDS 0.45 tDIPW 1.75 -0.6 0.35 0.35 tCL DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Symbol tCH CL = 2.5 CL = 2 -75Z/-75 tCK tCK tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS t DSH tHP 0.45 0.75 0.2 IHF ISF tIH S tIS S tIPW t MRD t QH t tRAP tRC t RFC 21 42 15 60 72 ns 23, 27 27 0.5 ns ns tCK tCK ns 1.25 tCK +0.75 t +0.75 -0.75 0.90 0.90 1 1 2.2 15 t HP tQHS 0.6 70,000 40 20 65 75 tCK 22, 23 tCK tCH,tCL +0.70 ns tCK ns ns ns 0.2 -0.7 0.75 0.75 0.8 0.8 2.2 12 t HP tQHS tQHS tRAS 0.75 0.2 tCH,tCL HZ t 1.25 0.2 t tLZ 1.75 -0.75 0.35 0.35 Notes 26 26 40, 46 40, 46 23, 27 0.5 +0.6 Units 0.75 120,000 CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 30 16, 37 16, 37 12 12 12 12 22, 23 31, 49 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Parameter Tables Table 15: Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval 128MB 256MB, 512MB Average periodic refresh interval 128MB 256MB, 512MB Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN -6 Symbol t RCD t RP t RPRE tRPST tRRD t Min 15 15 0.9 0.4 12 -75Z/-75 Max 1.1 0.6 Min 20 20 0.9 0.4 15 Max 1.1 0.6 Units ns ns t CK tCK ns 0.25 0 0.4 0.6 15 1 tQH -tDQSQ 140.6 70.3 15.6 7.8 0 75 t tXSNR 0.25 0 0.4 0.6 15 1 tQH -tDQSQ 140 70.3 15.6 7.8 0 75 tXSRD 200 200 tCK WPRE tWPRES tWPST tWR tWTR na tREFC tREFI tVTD 22 CK ns tCK ns tCK ns s s s s ns ns Notes 38 38 18, 19 17 22 21 21 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Notes Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT Output (VOUT) 50 Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (AC) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDD/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDD/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -75Z and CL = 2.5 for -6 and -75 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT (DC) = VDD/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -6, slew rates must be 0.5 V/ns. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDD is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Notes 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the "Don't Care" state after completion of the postamble is that the DQSdriven signal should either be HIGH, LOW, or High-Z and that any signal transition within the input switching region must follow valid input requirements. If DQS transitions HIGH, above DC VIH (MIN) then it must not transition LOW, below DC VIH, prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an average refresh rate of 15.625s (128MB) or 7.8125s (256MB, 512MB). However, an AUTO REFRESH command must be asserted at least once every 140.6s (128MB) or 70.3s (256MB, 512MB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), t DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window tQH - t(DQSQ), shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 26. JEDEC specifies CK and CK# input slew rate must be 1 V/ns (2 V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For -6, slew rates must be 0.5 V/ns. 28. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Notes Figure 7: Derating Data Valid Window tQH - t(DQSQ) 3.8 3.750 3.700 3.6 3.650 3.600 3.550 3.500 3.4 3.450 3.400 3.350 3.2 3.300 3.250 -75/-75Z @ tCK = 10ns -75/-75Z @ tCK = 7.5ns N/A -6 @ tCK = 6ns ns 3.0 2.8 2.6 2.500 2.463 2.425 2.388 2.4 2.350 2.313 2.275 2.238 2.200 2.163 2.2 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch to the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9 volts maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts minimum, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Notes 34. 35. 36. 37. 38. 39. 40. Figure 8: e. The full variation in the ratio of the maximum to minimum pull-up and pulldown current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VDD + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. t HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. During initialzation, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0.0V, provided a minimum of 42 of series resistance is used between the VTT supply and the input pin. During initialization, VDD, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDD are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Pull-Down Characteristics pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Notes Figure 9: Pull-Up Characteristics 41. 42. 43. 44. 45. 46. 47. 48. 49. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN For the -6 and -75 IDD3N is specified to be 35mA per DDR SDRAM device at 100 MHz. Random addressing changing and 50 percent of data changing at every transfer. Random addressing changing and 100 percent of data at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. IDD2N specifies the DQ and DQS to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. The -6 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Initialization Initialization To ensure device operation the DRAM must be initialized as described below: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN Simultaneously apply power to VDD and VDDQ. Apply VREF and then VTT power. Assert and hold CKE at a LVCMOS logic low. Provide stable CLOCK signals. Wait at least 200s. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. Perform a PRECHARGE ALL command. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Issue a PRECHARGE ALL command. Wait at least tRP time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL Reset) and any READ command. 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Initialization Figure 10: Initialization Flow Diagram Step pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 1 VDD and VDDQ Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 200us 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for tRP time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 Configure Load Mode Register and reset DLL 12 Assert NOP or DESELECT for tMRD time 13 PRECHARGE ALL 14 Assert NOP or DESELECT for tRP time 15 Issue AUTO REFRESH command 16 Assert NOP or DESELECT commands for tRFC 17 Issue AUTO REFRESH command 18 Assert NOP or DESELECT for tRFC time 19 Optional LMR command to clear DLL bit 20 Assert NOP or DESELECT for tMRD time 21 DRAM is ready for any valid command 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Serial Presence Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 13, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure 11: Data Validity SCL SDA DATA STABLE pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN DATA CHANGE 30 DATA STABLE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Figure 12: Definition of Start and Stop SCL SDA START BIT Figure 13: STOP BIT Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Table 16: EEPROM Device Select Code The most significant bit (b7) is sent first Device Type Identifier Memory Area Select Code (two arrays) Protection Register Select Code Table 17: RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW EEPROM Operating Modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write Figure 14: Chip Enable RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0' SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/condition Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICC 2.3 VDD x 0.7 -1 - - - - - 3.6 VDD + 0.5 VDD + 0.3 0.4 10 10 30 2 V V V V A A A mA SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz Table 19: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDD = +2.3V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Symbol Min Max Units Notes tAA 0.2 1.3 200 0.9 s s ns ns s s s ns s s KHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA tSU:STO tWRC 100 0.6 0.6 10 2 2 3 4 Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Table 20: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 35 Byte Description Entry (Version) 0 1 2 3 4 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on Dimm Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (tCK) (CAS Latency = 2.5) 128 256 DDR SDRAM 12, 13 10, 11 80 08 07 0C 0A 80 08 07 0D 0A 80 08 07 0D 0B 2 32 0 SSTL 2.5V 6ns (-6) 7.0ns (-75Z) 7.5ns (-75) 0.7ns (-6) 0.75ns (-75Z/-75) None 15.62s, 7.8s/SELF 8 02 20 00 04 60 70 75 70 75 00 80 08 02 20 00 04 60 70 75 70 75 00 82 08 02 20 00 04 60 70 75 70 75 00 82 08 None 1 clock 00 01 00 01 00 01 2, 4, 8 4 0E 04 0E 04 0E 04 2, 2.5 0 1 Unbuffered/Diff. Clock Fast/Concurrent AP 7.5ns (-6) 7.5ns (-75Z) 10ns (-75) 0.7ns (-6) 0.75ns (-75Z/-75) N/A 0C 01 02 20 0C 01 02 20 0C 01 02 20 C0 75 75 A0 70 75 00 C0 75 75 A0 70 75 00 C0 75 75 A0 70 75 00 N/A 00 00 00 18ns (-6) 20ns (-75Z/-75) 12ns (-6) 15ns (-75Z/-75) 18ns (-6) 20ns (-75Z/-75) 48 50 30 3C 48 50 48 50 30 3C 48 50 48 50 30 3C 48 50 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SDRAM Access From Clock (tAC) (CAS Latency = 2.5) Module Configuration Type Refresh Rate/Type Sdram Device Width (Primary DDR SDRAM) Error-Checking DDR SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on DDR SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes 22 23 SDRAM Device Attributes: General SDRAM Cycle Time, tCK (CAS Latency = 2) 24 SDRAM Access from Clock, tAC (CAS Latency = 2) SDRAM Cycle Time, tCK (CAS Latency = 1.5) SDRAM Access From Clock, tAC (CAS Latency = 1.5) Minimum Row Precharge Time, tRP (see note 3) Minimum Row Active to Row Active, tRRD Minimum RAS# to CAS# Delay, tRCD (see note 3) 25 26 27 28 29 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 34 MT8VDDT3232U MT8VDDT6432U MT8VDDT12832U Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Serial Presence Detect Table 20: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 35 Byte 30 31 Description Entry (Version) t Minimum RAS# Pulse Width, RAS (See note 1) Module Rank Density 34 Address and Command Setup Time, tIS (See note 2) Address and Command Hold Time, tIH (See note 2) Data/Data Mask Input Setup Time, tDS 35 Data/Data Mask Input Hold Time, tDH 32 33 36-40 Reserved 41 Min Active Auto Refresh Time tRC 42 43 Minimum Auto Refresh to Active/Auto Refresh Command Period, tRFC SDRAM Device Max Cycle Time, tCKMAX 44 SDRAM Device Max DQS-DQ Skew Time, tDQSQ 45 SDRAM Device Max Read Data Hold Skew Factor, tQHS 46 Reserved 47 DIMM Height 48-61 Reserved 62 SPD Revision 63 Checksum For Bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code Manufacturing Location Module Part Number (ASCII) Pcb Identification Code Identification Code (Continued) Year Of Manufacturein BCD Week Of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) 42ns (-6) 45ns (-75Z/-75) 64MB, 128MB, 256MB 0.8ns (-6) 1.0ns (-75Z/-75) 0.8ns (-6) 1.0ns (-75Z/-75) 0.45ns (-6) 0.5ns (-75Z/-75) 0.45ns (-6) 0.5ns (-75Z/-75) 60ns (-6) 65ns (-75Z/-75) 72ns (-6) 75ns (-75Z/-75) 12ns (-6) 13ns (-75Z/-75) 0.45ns (-6) 0.5ns (-75Z/-75) 0.55ns (-6) 0.75ns (-75Z/-75) Release 1.0 -6 -75Z -75 MICRON (Continued) 01-12 1-9 0 MT8VDDT3232U MT8VDDT6432U MT8VDDT12832U 2A 2D 10 2A 2D 20 2A 2D 40 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 C5 95 D5 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 D8 A8 E8 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 09 C9 F9 2C FF 01-0C Variable Data 01-09 00 Variable Data Variable Data Variable Data - Notes: 1. The value of tRAS used for -75 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns. 2. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worstcase (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 3. The value of tRP, tRCD and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Module Dimensions Module Dimensions All dimensions are in inches (millimeters); MAX or typical where noted. MIN Figure 15: 100-Pin DIMM Dimensions FRONT VIEW 0.157 (4.0) MAX 3.557 (90.34) 3.545 (90.04) 0.079 (2.00) R (2X) U1 U2 U3 U4 1.206 (30.63) 1.196 (30.37) 0.118 (3.0) DIA (2X) U5 0.70 (17.8) TYP 0.118 (3.0) TYP PIN 1 0.039 (1.0) R (2X) PIN 50 0.039 (1.0) TYP 0.039 (1.0) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) 2.85 (72.39) TYP BACK VIEW U6 0.084 (2.13) TYP PIN 100 U8 U7 U9 1.0 (25.4) TYP 0.118 (3.0) TYP PIN 51 1.765 (44.83) TYP Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004, 2005 Micron Technology, Inc. All rights reserved.