Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1
Copyright © 2000
Rev. 1.1, 2006-02-27
WWW.Microsemi .COM
LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
DESCRIPTION
The LX1689 is the latest generation
Direct Drive CCFL (Cold Cathode
Fluorescent Lamp) Controller. It uses
new circuit design techniques (patents
pending) and combin es digital and linear
circuits with an advanced BiCMOS
process to create a more complete
controller in a small package.
When compared to the original
LX1686 design, identical module
applications use from 12 to 30 less
components. New functions and
enhancements have been added to make
the LX1689 even easier to use.
The on-chip PLL circuit used to
synchronize the digital dimming burst
frequency to the video frame rate, as
used in the LX1686, is replaced with a
programmable counter. This counter can
divide the video controller horizontal
sync pulse, other external clock source
or the internal chip clock source to
generate the burst frequency.
The brightness control input allows the
use of either a DC voltage or a PWM
input to simplify design. Programmable
polarity brightness control is retained,
except in the case of externally clocked
digital dimming. Two onboard LDO
regulators extend the input voltage range
of the IC up to 28 Volts without using
external circuitry as was required with our
previous controllers. The LX1689
includes a new lamp strike detection
scheme that saves a package pin and three
external components. Internal circuits
monitor lamp current pulses at the I_SNS
input to determine if the lamp strikes and
if it stays ignited once operational.
Integrating full wave rectifiers for
each of three lamp inputs has significantly
reduced the lamp feedback component
count. In addition the controller features
include auto shutdown for open or broken
lamps, and a lamp fault detection with a
status reporting output.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
Protected By U.S. Patents: 5,615,093; 5,923,129; 5,930,121; 6,198,234; Patents Pending
KEY FEATURES
3 to 28 Volt Single Fixed (±20%)
Supply Operating Range
Selectable Analog/Digital
Dimming Modes
Digital Dimming Can Synch to
External Or Internal Clocks
User Programmable Digital
Dimming Burst Frequency
252 mS Power On Delay
Flexible Lamp Current
Compensation Input
Open Lamp Shutdown and Fault
Output Indicator
“On Chip” Full Wave Lamp
Current & Voltage Rectifiers
20 Pin TSSOP Package
BENEFITS
Low Component Count /
Module Cost / Size
High “Nits/Watt” Efficiency
Operates Directly From 1 to 6
Li_Ion Cells
Lamp Current Compensation
Input Makes Indoor/Outdoor
And Wide Temperature Range
Applications Easy to Design
PRODUCT HIGHLIGHT
LX1689 CCFL Inverter Layouts Examples*
*As Shown in Figure 1 (Typical Application)
Bill of Materials
1 LX1689CPW
1 Transformer
1 Dual FET
2 Connectors
7 Resistors
9 Capacitors
21 Total Count
PACKAGE ORDER INFO
PW Plastic TSSOP
20-PIN
TJ (°C) MIN VDD MAX VDD
RoHS Compliant / Pb-free Transition DC: 0442
0 to 70 3V 28V LX1689CPW
-40 to 85 3V 28V LX1689IPW
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1689CPW-TR)
L
LX
X1
16
68
89
9
2.64in.
(
67mm
)
1.38in. (35mm)
.870 in.
(22mm)
.397 in.
(
10mm
)
A
ctual Inverter Size
A
ctual Inverter Size
OR
Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
Copyright © 2000
Rev. 1.1, 2006-02-27
WWW.Microsemi .COM
LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V_BATT).................................................................................................30V
Digital Input (ENABLE).....................................................................................-0.3V to 7V
Analog Inputs Transient Peak (I_SNS, OC_SNS, OV_SNS)..............................-25V to +25V
Analog Inputs (BRITE_IN, EA_IN)..................................................................-0.3V to 5.5V
Digital Inputs (DIM_CLK,DIM_MODE, DIV_248) .........................................-0.3V to 5.5V
Digital Output (AOUT, BOUT).................................................................-0.3V to VDD_P +0.5V
Analog Outputs (BRITE_C, I_R, BRITE_OUT, BRITE_R, EA_OUT)...-0.3V to VDD_A_ +0.5V
Storage Temperature Range........................................................................-65°C to 150°C
Maximum Operating Junction Temperature...............................................................150°C
RoHS / Pb-free Peak Package Solder Reflow Temperature
(40 second maximum exposure).....................................................................260°C (+0,-5)
Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
PACKAGE PIN OUT
AOUT
V_BATT
OV_SNS
I_SNS
ENABLE
VDD_P
BRITE_R
DIM_MODE
BRITE_IN
DIM_CLK OC_SNS
EA_IN
BRITE_C
GND
VDD_A
BOUT
DIV_248
EA_OUT
BRITE_OUT
I_R
120
19
18
17
16
15
14
13
12
1110
9
8
7
6
5
4
3
2
PW PACKAGE
(Top View)
RoHS / Pb-free 100% Matte Tin Lead Finish
THERMAL DATA
PW Plastic TSSOP 20-Pin
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 144°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
FUNCTIONAL PIN DESCRIPTION
PIN NAME DESCRIPTION
GND Ground
VDD_P
Power VDD_P Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_P LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally 5.3V
and is used only to drive the output buffers at AOUT and BOUT. The external capacitor will be a 100 to 1000nF
ceramic dielectric. Up to 5mA DC additional load may be imposed by external circuitry. External load must be
reduced if the combination of output current and input voltage exceeds power dissipation capability of the die.
AOUT A buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
VDD_A
Analog VDD_A Supply Output. This output pin is used to connect an external capacitor to stabilize and filter the
on chip VDD_A LDO regulator. The input of the LDO is the switched V_BATT supply. LDO output is normally
2.95V and is used to drive all circuitry except the output buffers at AOUT and BOUT. Average internal load is
6mA. Up to 5mA DC additional load may be imposed by external circuitry. External load must be reduced if the
combination of output current and input voltage exceeds power dissipation capability of the die. The external
capacitor will be a 100 to 1000nF ceramic dielectric type.
BOUT B buffer N-FET driver output. The pin includes a internal 10K pull down resistor.
V_BATT
Voltage Input, 3 to 28V input range. V_BATT is switched (see ENABLE) to remove power from chip. Two LDO
regulators follow the switch, one generates VDD_P (see VDD_P) and the other VDD_A (see VDD_A). Care
must be taken in power distribution design to minimize transients and noise coupling from the VDD_P output to
the VDD_A output. The external capacitor will be a 100 to 1000nF ceramic dielectric type.
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 3
Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
PIN NAME DESCRIPTION
DIM_CLK
Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for
external Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the
dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition
(Analog Dimming Mode) the DIM_CLK input should be connected to VDD_A for conventional dimming polarity
or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with
increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing
voltage.
OC_SNS
Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high
voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital
comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a
pulse by pulse basis.
Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels should be under
max ±1.8VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transients under fault conditions can reach ± 25VPK.
DIM_MODE
Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming
Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is
selected.
If connected to VDD_A, Digital Dimming with a external clock source applied to the DIM_CLK input is
selected to the burst timing generator. If connected to Ground, Digital Dimming with a internal clock is selected.
The internal clock is equivalent to the frequency at AOUT divided by two, both the internal or external clock
frequency can be divided down by setting the DIV_248 pin. (see DIV_248)
OV_SNS
Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp
voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to
cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis.
Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels should be under
±1.8VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions.
Transients under fault conditions can reach ± 25VPK.
The input has a 10K pull down resistor that serves as a DC restorer to the external capacitor that divides
down lamp voltage.
DIV_248
Divide Digital Dimming clock by 2, 4, or 8. This three state input pin causes the internal or external digital
dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of
three possible burst rates for any given external or internal clock source. A high (VDD_A) selects divide by 2,
open selects divide by 4, and ground selects divided by 8. We advise keeping burst above 95Hz and below
about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components.
I_SNS
Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current.
The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error
amplifier through a 100K resistor.
Frequency range of the input signal is 10KHz to 500KHz. Normal operating voltage levels will be in the range
of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault
conditions. Transient under fault conditions can reach ± 25VPK. We strongly recommend a 10K resistor be
placed in series with the pin to limit current from voltage spikes that can occur by intermittent lamp connectors,
or arcing from a faulty high voltage transformer. This resistor will eliminate the possibility of IC damage under
these fault conditions.
The open lamp fault logic monitors the I_SNS pin voltage and number of lamp current cycles. If the number
of lamp current cycles with amplitude below fault threshold are less than 8 in a given fault checking period then
the strike latch will not be reset and a fault is declared, which shuts down the A/B outputs. In the strike mode, if
no lamp current is detected after 15 attempts a fault is likewise declared. ( See further LX1689 operation
section)
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
FUNCTIONAL PIN DESCRIPTION (CONTINUED)
PIN NAME DESCRIPTION
BRITE_C
BRITE Filter Capacitor and FAULT Output. Used to convert higher frequency digital PWM inputs to proportional
DC currents at the BRITE_OUT pin. The capacitor forms a low pass filter with an internal 200K resistor. This
pin will be driven to VDD_A if a lamp fault is detected by the LX1689. If no fault is present the voltage at this pin
will vary from 50mV to 1.05V as BRITE_IN varies from 0 to 2V. A CMOS gate may be connected to this pin to
sense the fault condition. TTL gates or other low impedance (less than 20 megohm) must not be connected to
this node as their DC resistance will load the internal 200K resistor and create error in the BRITE_OUT current
level.
EA_IN
Error Amp Inverting Input. Frequency Compensation input for the Error Amplifier. See EA_OUT below. A
100K, negative TC on chip resistor connected between the inverting input of the error amplifier and the output of
the I_SNS full wave rectifier is the resistor in an R/C loop compensation network.
BRITE_R Dedicated Bias resistor for BRITE_OUT current source.
EA_OUT
Error Amp Output. Error amplifier is a GM type and does not require a external capacitor for stability. An
external capacitor is connected from this pin to EA_IN to adjust the loop response of the inverter module. This
capacitor value can vary from 100pF to 5000pF in various applications. This capacitor may also be connected
from the EA_OUT to ground.
BRITE_IN
Brightness Control Input. The input signal can be a DC voltage, a low frequency pulse width modulated digital
signal, or a high frequency pulse width modulated digital signal. Active DC voltage range is 0.5 to 2.0V. Signals
above 2V are clipped and signals below 0.5V make output current from the BRITE_OUT pin near zero. Low
frequency digital PWM signals up to 500Hz can be applied to affect Digital Dimming. Higher frequency PWM
signals, up to 100KHz are filtered to an equivalent DC current at the BRITE_OUT pin by adding a capacitor at
the BRITE_C pin. On chip signal conditioning amplifiers clip inputs above 2V so that lamp current amplitude is
not sensitive to the voltage level variations of a digital PWM input signal.
BRITE_OUT
Brightness Reference Current Output. This variable current source is the mirror of BRITE_R current multiplied
by the voltage at BRITE_C (0 to 1.0V) when analog dimming is selected, or by 1.0V when digital dimming is
selected. It becomes the reference voltage to the lamp current error amplifier when applied to an external
precision resistor connected from the BRITE_OUT pin to ground. BRITE_OUT current:
Mode) Dimming (Digital 1.0II BRITE_RBRITE_OUT ×=
Mode) Dimming (Analog VII BRITE_CBRITE_RBRITE_OUT ×=
BRITE_OUTBRITE_RBRITE_OUT RIV ×=
BRITE_R
BRITE_R R
1.00V
I=
ENABLE
Chip Enable Input. If logic high, all functions are enabled. If logic low, internal power is disconnected from the
V_BATT pin, disabling all functions. Logic threshold is about 1.2V. Maximum current into V_BATT when
ENABLE < 0.3V, V_BATT <28V, is 28 µA. ENABLE may be connected to V_BATT through a series resistor if
the disable function is not used. Resistor tolerance is ± 10%; and R value is:
Amp30x10
1.5V][V_BATT
R6
MIN
−
−
=
The Enable pin can be connected directly to 3.3/5V logic.
I_R
Current Reference Resistor Input. Connects to an external resistor that determines the magnitude of internal
bias currents. The nominal lamp frequency can be adjusted by varying this resistor value in the range of 10K to
150K Ohms.
I_R
I_R R
1.00V
I=
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
RECOMMENDED OPERATING CONDITIONS
LX1689
Parameter Min Typ Max
Units
Supply Voltage (V_BATT) 3 28 V
Digital Input (ENABLE) 0 6.5 V
Analog Inputs (I_SNS, OC_SNS, OV_SNS) -3 3 VPK
BRITE_IN Linear DC Voltage Range 0.5 2 V
BRITE_IN PWM Logic Signal Voltage Range 0 5 V
Digital Inputs (DIM_MODE, DIV_248,DIM_CLK) 0 5.5 V
Maximum Output Gate Charge (AOUT, BOUT) 10 20 nC
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature: LX1689CPW: 0°C≤ TA
≤
70°C,
LX1689IPW: -40°C≤TA≤85°C, except where otherwise noted.
Test conditions: V_BATT =3.3 to 28 VDC, I_R =80.6KΩ, BRITE_R = BRITE_OUT = 10KΩ, BRITE_C =open, ICOMP =100pf
LX1689
Parameter Symbol Test Conditions Min Typ Max
Units
` POWER
Regulator Output Voltage VDD_P V
_BATT = 6 to 28 V, I Load = 0 – 5mADC 5.05 5.3 5.55 V
VDD_P Drop Out Voltage ∆VDD_P ∆VDD_P = -1% , I Load = 5mADC; TA = 25°C 50 mV
Regulator Output Voltage VDD_A V
_BATT = 3.5 to 28V, I Load = 0 – 5mADC 2.75 2.95 3.15 V
VDD_A Dropout Voltage ∆VDD_A ∆VDD_A = -1% , I Load = 5mADC; TA = 25°C 100 mV
VBATT Static Current IBATT 5.5 9 mA
VBATT Dynamic Current IBATT C
AOUT = CBOUT = 1000pF 10 17 mA
Sleep Mode Current IBATT_SLEEP V
ENABLE ≤ 0.4V; VBATT = 5V 2.8 5 µA
Sleep Mode Current IBATT_SLEEP V
ENABLE ≤ 0.4V; VBATT = 28V 22 35 µA
` ENABLE INPUT
Run Threshold VTH_ENRUN 1.1 1.4 V
Shutdown Threshold VTL_ENSHDN 0.4 1.1 V
Input High Current IIH_ENABLE ENABLE = 2V 2 12 µA
Input High Current IIH_ENABLE ENABLE = 5V 35 80 µA
Input Low Current IIL_ENABLE ENABLE = 0V -1 0 1 µA
` UNDER VOLTAGE LOCKOUT
Startup Threshold Run Mode 2.55 2.8 V
UVLO Threshold VT_UVLO Shutdown Mode 2.1 2.35 V
UVLO Hysteresis VH_UVLO 200 mV
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 6
Copyright © 2000
Rev. 1.1, 2006-02-27
WWW.Microsemi .COM
LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1689
Parameter Symbol Test Conditions Min Typ Max
Units
` RAMP GENERATOR
Max Strike / Run Frequency Ratio FRAMP_STK Ratio to run frequency, I_SNS = OV_SNS = 0V 4 5 6
Maximum Lamp Run Frequency FRAMP_RUNMAX Lamp is ignited; I_R=10K 250 450 KHz
Lamp Run Frequency FLAMP_RUN Lamp is ignited ;TA = 25°C 63 65 67 KHz
Lamp Run Frequency FLAMP_RUN Lamp is ignited 61 65 69 KHz
Lamp Run Frequency Regulation over
V_BATT FLAMP_REG 3.3 < VBATT < 28V 0.1 %
DIV_248 = VDD_A, DIM_MODE = 0V 254 Hz
DIV_248 = Floating, DIM_MODE = 0V 127 Hz
Internal Digital Dimming
Burst Frequency FBURST
DIV_248 = Gnd, DIM_MODE = 0V 63.5 Hz
` BIAS BLOCK
Voltage at Pin I_R V_IR V
BATT = 2.8V to 28V, IOUT = 0 to 100uA, TA = 25°C 0.95 1.0 1.05 V
Pin I_R Max Source Current IMAX_IR I_R = 0V 100 700 µA
Voltage Reference Voltage
(Internal node) V2P0 T
A = 25°C, reference use only 1.99 2 2.01 V
` PWM BLOCK
Error Amp Transconductance GM_EAMP 90 180 µmho
Error Amp Output Source Current IS_EAMP 5 12 µA
Error Amp Output Sink Current ISK_EAMP 5 12 µA
Error Amp Output High Voltage VH_EAMP BRITE_OUT – EA_IN = 50mV 2.5 2.9 V
Error Amp Output Low Voltage VL_EAMP EA_IN – BRITE_OUT = 50mV 0.015 0.5 V
Error Amp Input Offset Voltage VOS_EAMP 70 mV
Max Duty Cycle DCMAX 44 %
Ramp Valley Voltage RVV 200 mV
Ramp Peak Voltage RPV 1.95 V
` OUTPUT BUFFER BLOCK
Output Sink Current ISK_OUTBUF V
AOUT, VBOUT = VDD_P 100 mA
Output Source Current IS_OUTBUF V
AOUT, VBOUT = 0V 100 mA
Output Rise Time TR C
OUT = 1000pF 25 200 nS
Output Fall Time TF C
OUT = 1000pF 25 200 nS
` DIM_CLK INPUT
Pull-up Resistance To VDDA 50 KΩ
Input High Threshold VTH_DIM_CLK Conventional Dimming 0.9 1.4 V
Input Low Threshold VTL_DIM_CLK Reverse Dimming 0.4 0.9 V
Input High Current IIH_DIM_CLK DIM_CLK = 5V 45 70 µA
Input Low Current IIL_DIM_CLK DIM_CLK = 0V -65 -100 µA
` TRI-STATE LOGIC INPUTS (DIM_MODE,DIV_248)
Low State VTL_TRI_ 0.4 0.6 V
Floating State VTF_TRI 1.2 1.35 1.8 V
High State VTH_TRI 2.1 2.8 V
Input High Current IIH_TRI DIM_MODE = DIV_248 = 5V 70 120 µA
Input Low Current IIL_TRI DIM_MODE = DIV_248 = 0V -25 -50 µA
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
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D
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TM ®
ELECTRICAL CHARACTERISTICS (CONTINUED)
LX1689
Parameter Symbol Test Conditions Min Typ Max
Units
` ANALOG DIMMER BLOCK
BRITE_IN Input Current BRITE_IN II BRITE_IN = 0 to 5V -1 1 µA
BRITE_IN < 0.45V 20 52 100 mV
BRITE_IN > 2.05V; TA = 25°C 0.96 1.04 1.12 V
Conventional Dimming
BRITE_OUT
BRITE_IN > 2.05V 0.94 1.04 1.14 V
BRITE_IN < 0.45V; TA = 25°C 0.98 1.06 1.14 V
BRITE_ IN < 0.45V 0.96 1.06 1.16 V
Reverse Dimming
BRITE_OUT
BRITE_IN > 2.05V 10 62 120 mV
` DIGITAL DIMMER BLOCK
Minimum Duty Cycle; BRITE_IN ≤ 0.55V 2 10 15 %
Maximum Duty Cycle; BRITE_IN =1.90V 85 92 100 %
Conventional Dimming
Duty Cycle
Maximum Duty Cycle; BRITE_IN ≥ 1.95V 100 %
Maximum Duty Cycle; BRITE_IN ≤ 0.55V 100 %
Maximum Duty Cycle; BRITE_IN = 0.6V 85 92 100 %
Reverse Dimming
Duty Cycle
Minimum Duty Cycle; BRITE_IN ≥ 1.95V 2 10 15 %
` TIMING GENERATOR BLOCK
Number of Lamp Return Current
Cycles before Run Mode NIGNITE To switch to Run Mode 8 Cycles
I_SNS Run Mode Checking Interval Lamp return current cycles, 8192 x 1 /fO 126 mS
Fault Comparator Threshold Voltage I_ SNS Open Lamp Fault Detect, TA =25°C 250 305 350 mVPK
Number of Strike sweep Attempts
Before Fault Shutdown NSTRK_FAULT FLAMP Sweep Cycles, I_SNS = 0V_SNS = 0V 15
Power On Delay Before Strike TD_PWRON 16384 X Lamp Run Period 252 ms
Number of Sweeping Strike Frequency
Steps per Attempt 1024 Steps
Number of Output Pulses per Striking
Step 16 Cycles
` LAMP FEEDBACK CONDITIONING BLOCK
I_SNS =10V 80 150 µA
I_SNS Input Current I_SNSIIN I_SNS = -10V -200 -350 µA
OV_SNS Input High Threshold VTH_OV_SNS Active Over Voltage Protection ± 2 ± 2.2 VPK
OV_SNS Input Low Threshold VTL_OV_SNS Inactive Over Voltage Protection ± 1.8 ± 2 VPK
OV_SNS = 10V 260 400 µA
OV_SNS Input Current OV_SNSIIN OV_SNS = -10V -320 -450 µA
OC_SNS Input High Threshold VTH_OC_SNS Active Over Current Protection ± 2 ± 2.2 VPK
OC_SNS Input Low Threshold VTL_OC_SNS Inactive Over Voltage Protection ± 1.8 ± 2 VPK
OC_SNS = 10V 45 80 µA
OC_SNS Input Current OC_SNSIIN OC_SNS = -10V -110 -180 µA
I_SNS = 0.3VDC, TA = 25°C 0.27 0.31 0.35 V
I_SNS = 2.0VDC, TA = 25°C 1.95 2 2.05 V
I_SNS = -0.3VDC, TA = 25°C 0.24 0.3 0.36 V
Full Wave Rectifiers RMS Transfer I_SNSRMS
I_SNS = -2.0VDC, TA = 25°C 1.75 1.9 2.05 V
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Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
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D
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TM ®
BLOCK DIAGRAM
V_BATT
ENABLE
VDD_A
VDD_P
I_R
BRITE_IN
BRITE_OUT
BRITE_R
DIM_CLK
DIM_ MODE
DIV_248
GND
OV_SNS
OC_SNS
I_SNS
EA_IN
EA_OUT
BOUT
AOUT
SLEEP
SHUTDOWN
DUAL LDO
UVLO BIAS
75K 50K
100K100K
50K
+
+
+
-
-
-
2.0V
0.5V
0.5V
0.5V
BRITE_C
200K
VDD_A
FAULT
+
-
3 STATE
DECODER
3 STATE
DECODER
MUX
&
DIV
6BIT
VDAC
6 BIT
COUNTER
RS
1V
RESET
EXT
ANLG
INT
Q
Q
DQS
R
DIGITAL DIM
ANALOG DIM
10K
OUTPUT
STEERING
LOGIC
10K
RAMP_D
FAULT
+
-
RAMP_C
+
-
BRITE_OUT
DIM CLOCK
IGNITE
DIGITAL DIM
100K
LSNS
RECTIFIER
OC_SNS
RECTIFIER
OV_SNS
RECTIFIER
200K
RUN MODE
FAULT DET
STRIKE MODE
FAULT DET
RAMP
GENERATOR
20 BIT
COUNTER &
POW ER ON
RESET LOGIC
10 BIT
REGISTER
10 BIT
IDAC
RAMP_C
RMP_D OUT
F EXT
DDIM
FAULT
IGNITE
5.3V
2.95V
2.0V
REF
PWR_GD
R
+
+
+
-
-
-
2.0V
ANADIM
N
ERROR
AMP
DIMMING
CONTROL
BLOCK
TIMMING
GENERATOR
BLOCK
STRIKE
DETECTION
BLOCK
LAMP FEEDBACK
CONDITIONING BLOCK
OUTPUT DRIVERS BLOCK
PWM CONTROL
BLOCK
ENABLE & BIAS
GENERATOR
BLOCK
+
-
VDD_A
I1
I1
+
-
300mV
FIGURE 1 – Simplified Block Diagram
B
BL
LO
OC
CK
K
D
DI
IA
AG
GR
RA
AM
M
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
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HEET
TM ®
TYPICAL APPLICATION
R6
120
C5
470pF 16V
R2
51.1K
1%
R3
4.99K 1%
C4
100nF 16V
C3
100nF 16V
C6
100µF
10V 20%
TANT
C8
100nF
50V
C9*
2pF
C10
1.5nF
25V 5%
COG
R7
255Ω1
%
C1
100nF 16V
C2
100nF 16V
R1
6.65K 1%
VBATT
GND
BRITE
ENABLE
Lam
p
Lam
p
GND
I_R
EA_OUT
EA_IN
BRITE_OUT
I_SNS
OV_SNS
OC_SNS
VBATT
VDD_A
VDD_P
ENABLE
BRITE_IN
BRITE_R
BRITE_C
DIV_248
DIM_MODE
DIM_CLK
AOUT
BOUT
+
3.0V < VBATT < 5V
C7
1nF
16V
T1 SGE2697-1
MICROSEMI
1:53
LMT1410
275VRMS
±
IOUT = 3.5
m
100kHz
Nominal 3.2V to 4.2V
N.C.
U2 FDC6305N
FAIRCHILD
*C9 PCB CAPACITOR COPPER AREAS TO EQUAL
APPROXIMATELY 342MM FOR 0.80MM THICK PCB
PCB CAP AREA FORMULA (K TYPICIALLY = 5.35)
AREA(MM²) = D(mm) x C x 113097 E+9 / K
R4
10K
R5
10
VDD_A
C11
1.0uF 10V
10%
VDD_A
Enable input
Logic Level: 2.5V to 3.3V
ON: Logic 'HI' = >1.5V
OFF: Logic 'LOW' =< 0.8V
BRITE Input Control Range
(Linear DC)
Min. Brite 'LO' <= 0.50V
Max. Brite 'HI' >= 2.00V
(2.5V to 3.3V Logic PWM)
Min. Brite Pos Duty <= 1.6%
Max. Brite Pos Duty >= 92%
PWM freq 7.5Khz to 100Khz
Burst Rate Freq: 195Hz ± 4%
Alternate Maximum Lamp Current Table
Lamp current | R1 value | R7 Value
4.0mArms | 6.65K 1% | 221 1%
3.5mArms | 6.65K 1% | 255 1%
3.0mArms | 6.65K 1% | 294 1%
2.5mArms | 11.8K 1% | 200 1%
2.0mArms | 11.8K 1% | 249 1%
1.5mArms | 11.8K 1% | 332 1%
LX1689CPW
1
3
6
4
2,5
1
3
2
4,5
6
FIGURE 2 – LX1689 Typical 1W Application
DIMMING TABLE
DIM_MODE DIM_CLK DIMMING MODE DIMMING POLARITY*
VDD_A External Clock Source
External Burst
Dimming from divided
DIM_CLK input
Conventional
Floating or VDD_A/2 VDD_A Analog Dimming Conventional
Floating or VDD_A/2 GND Analog Dimming Reverse
GND VDD_A
Internal Burst
Dimming from divided
Run Frequency
Conventional
GND GND
Internal Burst
Dimming from Divided
Run Frequency
Reverse
* Conventional polarity means that the lamp brightness increases with increasing voltage on the BRITE_IN pin.
Reverse polarity means that brightness decreases with increasing voltage.
A
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PP
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NS
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
APPLICATION
SLEEP
VIN
VIN
GND
GND
BRITE
C1
100nF 20%
25V
R1 10Ω
V_BATT
R2 10K 1%
C7 100nF 16V
x
VDD_A
BOUT
AOUT
R12 39Ω
R11 39Ω
C4 1.0µF 20% 16V
C5 470nF 20% 10V
C6 470nF 20% 10V
VDD_P
VDD_A
V_BATT
R3 64.9K 1%
C8
4.7nF
16V
x
R4
12.7K 1%
R6 4.99K
1%
I_LMP
R5 10K
I_SNS
R7
680Ω
OV_SNS
C9
1.0nF
25V
R8
1.0K
C3
22µF 20%
25V TANT
C2
22µF 20%
25V TANT
R9 39Ω
R10 39Ω
AOUT
BOUT
LMT2110
1:32
LMT2110
1:32
C13
100nF
20% 50V
C14
2.0pF
(PCB cap)
C15
2.7nF
5% 25V
COG R17
47K
R18 270K
VDD_P
OV_SNS
OV_SNS
R14 150Ω
OC_SNS
D1
BAV70WT1
R13 150Ω
D2
BAW56WT1
VDD_P
VDD_P
R15
47K C12
2.7nF
5% 25V
COG
C11
2.0pF
(PCB Cap)
C10
100nF
20% 50V
CN2
Lamp LO
Lamp HI
CN3
Lamp LO
Lamp HI
R20
274Ω
1%
R19
274Ω
1%
D4
BAW56WT1
D3
BAW56WT1
I_LMP
D5
BAV70WT1
VDD_P
R23
1.0M
R21
1.0M
R24 4.7K
C17
100nF
16V
R22 4.7K
+
-
U4B
LMV393MM
R25 10K
R26 2.2K
+
-
U4A
LMV393MM
VDD_A
I_SNS
x
x
VDD_P
C16
100nF
16V
F1 2A 24V
OC_SNS
U2 Si9945AEY
VISHAY
U2 Si9945AEY
VISHAY
T2 SGE2682-1
MICROSEMI
T1 SGE2682-1
MICROSEMI
Q2
MBT3904DW1T1
C11 & C14 PCB Cap. copper
areas to equal approximately
442mm for 1.0mm thick PCB
CN2 & CN3 Operational RMS
lamp condition @ 6.5mA,
80kHz: 535V ± 15%
Alternate Maximum Lamp Current Table:
VIN power input
functional:12V ±15%
Nominal: 12V ±10%
SLEEP input
(2.5V t 3.3V Logic Level)
ON: Logic "HI" > 1.5V
OFF: Logic "LO" < 0.8V
BRITE Control Range
(Linear DC)
Min. Bright: "LO" < 0.50V
Max. Bright: "HI" > 2.0V
(2.5V to 3.3V PWM Logic)
Min. Bright Positive Duty Cycle: 0%
Max. Bright Positive Duty Cycle: 100%
PWM Freq: 7.5kHz to 100kHz
Burst Rate Freq: 156Hz ±4%
1
2
3
45
6
7
8
1
2
3
4
56
7
1
2
4
3
5
6
7
8
1
2
3
4
56
7
LX1689CPW
GND
AOUT
BOUT
DIM_CLK
DIM_MODE
DIV_248
BRITE_C
BRITE_R
BRITE_IN
ENABLE I_R
EA_IN
EA_OUT
I_SNS
OV_SNS
OC_SNS
BRITE_OUT
V_BATT
VDD_A
VDD_P
FIGURE 3 – Typical Dual 4 Watt Application
A
AP
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PL
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ON
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Integrated Products
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Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
DESCRIPTION
FEATURE REVIEW
On-Chip LDO Regulators
Two LDO regulators extend the input voltage range of the IC up
to 28 Volts without using external circuitry as was required with
our previous controllers.
Under Voltage Lockout
If the battery input voltage is too low for the controller to
function properly, it will turn itself off, preventing spurious
operation. If the battery voltage falls to less than 1V where UVLO
is no longer guaranteed, 10K pull down resistors on the AOUT and
BOUT pins insure the external power FETs cannot be biased on.
Power On Delay
A power up reset delays AOUT and BOUT turn on for
approximately 16384 x 1/fO milliseconds after power is applied.
This gives extra time for the BRITE_IN source voltage to stabilize
so the lamp is not inadvertently powered up at high brightness and
then suddenly lowered, creating an undesirable light flash.
Enhanced BRITE Conditioning Circuitry
The BRITE_IN input is now enhanced to accept either DC
voltage or logic PWM signals. When PWM signals are input, their
levels are clipped at 2V and 0.5V so lamp current will not be
affected by variations in logic signal level. In addition, the
BRITE_C pin permits filtering DC inputs and converting high
frequency PWM inputs to DC voltages with the addition of only a
single external capacitor. A low frequency (less than 500Hz)
PWM signal can be used to directly modulate the duty cycle of the
lamp current. In this case the capacitor at BRITE_C is not
installed.
Digital or Analog Dimming Modes
A DIM_MODE input pin selects either Analog or Digital mode.
In Analog mode DC voltage at BRITE_IN controls lamp current
amplitude. In Digital mode it controls digital dimming duty cy cle
with amplitude fixed at a value set by the external current scaling
resistor (BRITE_R). When in Digital mode, the dimming burst
frequency can be synchronous to lamp current by selecting internal
clocking, or to an external clock that may be a multiple of the
video vertical frame rate. With an external clock source, three burst
rate selections are available by programming the DIV_248 input to
divide the source clock by 2,4, or 8. This clock source is further
divided by 64 generating the internal burst ramp waveform. Using
the internal clock as source the DIV_248 input changes to divide
by 4, 8, or 16. This feature allows the designer to set a burst
frequency in the range of 100 to 500Hz. The external clock source
must not be interrupted unless the BRITE_IN is set > 2V or the
lamp will extinguish.
Brightness Polarity Control
In Analog dimming mode or internal Digital Dimming, the IC
can be programmed to either increase or decrease lamp current
amplitude as a function of increasing signal at the BRITE_IN pin
by simply connecting the DIM_CLK input to ground or VDD_A
or open(see Dimming Table). If External Digital dimming mode is
used, lamp current amplitude is constant and its duty cycle is
always directly proportional to DC input voltage and / or PWM
duty cycle at the BRITE_IN pin.
Lamp Current Compensation
The BRITE_OUT pin outputs a precision current that is
proportional to the BRITE_IN signal. This current can be applied to
a precision resistor to develop the brightness control voltage at the
error amplifiers non-inverting input. Since the output is constant
current, designers can easily compensate lamp current with respect
to temperature, input voltage, ambient or lamp light output, and
combinations of these conditions by using various temperature or
light sensitive components in combination with resistors. This
capability is very useful in automotive and outdoor applications
where operating temperatures and ambient light vary over wide
ranges. See functional pin description for details.
Strike Voltage Generation
Improved strike voltage generation circuits ramp strike voltage to
5X fO and repeats it’s cycle unless excessive high voltage is sensed
at OV_SNS. If OV_SNS is detected during strike, strike voltage
will not ramp and will hold the current voltage until total strikes
lamp cycles numbers reach 245,760. Strike potential is removed
immediately when the lamp strikes or if the time limit is reached.
Strike Detection
The LX1689 includes a new lamp strike detection scheme that
saves a package pin and three external components. Internal circuits
monitor lamp current pulses at the I_SNS input to determine if the
lamp strikes and if it stays ignited once operational.
Fault Time Out
If the lamp fails to ignite with in approximately 1.6 seconds
(depending on Run Frequency) at maximum strike potential, or if it
extinguishes while enabled, or the external clock frequency at the
DIM_CLK pin terminates, the output drive is shut down and the
BRITE_C pin is driven high. This pin can be monitored with a
CMOS gate to obtain a logical indication that a lamp fault has
occurred. It is especially useful in multiple lamp applications or for
system diagnostic input.
The voltage on pin BRITE_C will vary directly with BRITE
input voltage, but does not exceed 1.2V unless a fault condition
occurs.
On Chip Rectifier
Integrating full wave rectifiers for each of three lamp inputs has
significantly reduced lamp feedback component count. Current
Sense (I_SNS), Over Current Sense (OC_SNS) and Over Voltage
Sense (OV_SNS) signals are now detected using only one external
scaling resistor or capacitor each. Rectification accuracy is
improved with high performance on chip rectifiers to provide better
lamp current and voltage regulation.
Complete Fault Protection
In addition to the faulty lamp time out, lamp open, lamp shorted,
and either lamp terminal shorted to ground are detected. Open
circuit voltage can never go higher than the preset maximum strike
potential and total current from the circuit is safely limited with a
scaling resistor. UL safety specifications can now be easily met in
any application.
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Microsemi
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Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
DESCRIPTION (CONTINUED)
LX1689 OPERATION
Four operating modes: Power On Delay, Strike, Run, and Fault
modes are employed by the LX1689. Upon power up or ENABLE
going true, Power On Delay is automatically invoked.
Immediately after termination of Power On Delay, or ENABLE
going true, strike mode is entered. After a successful strike, e.g.
lamp is ignited, run mode is entered. If ignition is unsuccessful, or
if the lamp extinguishes while running, Fault mode is entered.
Lamp ignition is determined by monitoring the lamp current
feedback voltage at pin I_SNS. Lamp current cycles are counted
from the beginning of Strike mode. If 8 or more complete cycles
occur the lamp is declared ignited. If less than 8, the lamp is
considered not ignited and Strike mode continues until ignition is
detected or strike time out is reached.
After run mode is entered lamp current cycles are sampled every
8192 x 1/fO to determine that the lamp has not inadvertently
extinguished. If at least 8 lamp current pulses are counted in each
sample, Run mode is maintained. Otherwise, Fault mode is
entered. Strike mode can be entered only once for each on/off cycle
of either V_BATT or ENABLE. This insures that even
intermittent lamp failures cannot cause the module to continuously
output maximum strike voltage.
Power ON Delay Mode
All functions are activated except that AOUT and BOUT are
inhibited. Delay is 16384 x 1/fO determined by counting Ramp
clocks. The first of 16 sweeps is decoded as the power on delay
period. The subsequent 15 sweeps are used for controlling the
Ramp generator during Strike Mode. Power on delay is activated
at every V_BATT power up sequence and ENABLE sequence.
Strike Mode
Entered from Power On Delay, or upon an ENABLE sequence.
Control of the Ramp Generator frequency is switched to a DAC
output. Frequency is increased in a saw tooth fashion from normal
run value to as high as five times that value, for up to 15 sweeps.
If while strike frequency is ramping up, the over voltage set point
at OV_SNS is detected, strike frequency will freeze at that value
until either the lamp strikes or the timeout is reached. Strike Mode
is terminated by reaching 15 sweep counts or by detecting lamp
ignition. If strike is successful, Run Mode is entered. If
unsuccessful, Fault mode is entered, a fault is declared and the A &
B outputs are shut off.
The purpose of sweeping lamp frequency up during strike is to
operate at the unloaded resonant frequency of the transformer and
lamp load. This generates the high lamp striking voltage required,
since at resonance, output voltage from the transformer will
increase to any value needed to cause ignition. A capacitive
voltage divider provides output voltage feedback to the OV_SNS
pin, which freezes Strike Frequency to limit maximum output
voltage to a safe value.
Since strike frequency is held constant once the LX1689 senses
maximum safe output voltage, maximum strike potential is
continuously impressed across the lamp for the entire strike period.
Because strike frequency is ramped up rather than simply
stepped, the entire range of possible self-resonant frequencies is
covered. Transformer manufacturing is simplified and parasitic
panel capacitance values are no longer critical. The 5:1 strike
frequency range easily covers the self-resonant frequency of all
practical lamp assembly and transformer combin a ti ons.
The only way to re-initiate the strike process is to either cycle
V_BATT or ENABLE off and on.
If ignition is successful, ramp frequency immediately returns to
its normal run value.
Run Mode
Entered only by detection of a successful Strike. Ramp generator
frequency control is immediately switched from DAC output to a
fixed reference that sets the normal run frequency. During Run
mode, the Fault Detect Counter is reset approximately every 8192 x
1/fO. The lamp current cycle counter is monitored to insure at least
8 current cycles received during each period. If less than 8, the
lamp is considered extinguished and the Fault Mode is entered.
Fault Mode
Fault Mode may be entered from either Strike or Run Mode as
described above. In Fault Mode, the A & B output drivers are
forced low and the BRITE_C pin is driven to VDD_A to indicate
the fault condition. Fault mode may be cleared by cycling
ENABLE off then on, or by removing and applying V_BATT.
External load on the BRITE_C pin is limited to a filter capacitor and
single CMOS gate input.
DESIGN PROCEDURE
Selecting the I_R resistor value
This resistor determines the frequency of the on chip oscillator.
The output of the oscillator, RAMP_C, controls all timing functions.
It must be chosen first, and will be in the range of 10K to 150K
ohms. The output frequency approximated by the following
formula : RI_R = 5.24E9 / FLAMPOUT(Hz)
RAMP_C frequency is twice lamp output current frequency.
Driving the BRITE_IN Input
BRITE_IN can be a DC voltage, a low frequency PWM signal
that produces direct digital dimming, or a higher frequency PWM
signal that is converted to a proportional DC level by adding a filter
capacitor at the BRITE_C pin. 100% duty cycle corresponds to 1.1
volt, and 0% duty cycle corresponds to zero volts at the BRITE_C
pin. Maximum BRITE_IN input frequency for PWM inputs is 100
KHz, but when converting frequencies above 25 KHz to DC, some
accuracy is lost. The BRITE_IN input circuitry includes on-chip
active voltage clamps that ignore input voltage greater than 2.0V
and less than 0.5V. This allows the use of digital PWM input
signals where brightness is dependent only on duty cycle, with no
contribution
D
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Microsemi
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Copyright © 2000
Rev. 1.1, 2006-02-27
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LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
DESCRIPTION (CONTINUED)
due to varying input signal amplitude. Input impedance is very
high so BRITE_IN can also be driven from a 100K potentiometer
with no offset error.
BRITE_R and BRITE_OUT Resistor values.
The BRITE_OUT pin is the output from the BRITE_IN signal
processor. It is a linear current source that varies from 0 to the
current value established at pin BRITE_R multiplied by the DC
voltage at pin BRITE_C. The optimum value for BRITE_R is
usually 10K ohms. The BRITE_OUT voltage range can be scaled
from 300mV to 2.0V. However, it is recommended that the
scaling of BRITE_OUT (including Analog mode BRITE_IN
range) be within 400mV to 1.2V. Maximum voltage correlates to
full brightness settings. It is the ratio of the two resistors
multiplied by the voltage at BRITE_C:
V BRITE_OUT = V BRITE_C (RBRITE_OUT / RBRITE_R_)
In some applications, a precision 10K resistor is connected from
BRITE_OUT and BRITE_R to ground to develop 1.0V to
represent maximum lamp brightness. In Analog mode the
BRITE_OUT voltage potential is proportional to BRITE_IN. The
minimum brightness setting at BRITE_IN corresponds to the
minimum voltage at BRITE_OUT. In digital mode, BRITE_IN
has no effect on BRITE_OUT.
Because the BRITE_OUT output is a linear current source, you
can place other components, such as a thermistor or photo resistor,
at this pin to generate complex functions for controlling brightness.
For example; use a PWM input at the BRITE_IN pin to control
dimming, and boost analog lamp current amplitude at cold lamp
temperature with a thermistor at the BRITE_OUT pin. This will
help warm the lamp faster at start up so final brightness is reached
sooner.
SETTING THE OUTPUT CURRENT.
Referring to the application examples figures 2 and 3. The
current setting resistor(s) are R7, and R19 and R20 respectively.
The value these resistor(s) are in the range of 200 to 400ohms. The
following formula can be used to determine the current setting
resistor value. Use 1180 for Digital mode and 1260 for analog dim.
RSNS = 1180 or 1260 x RBRITE_OUT / IOUT(mARMS) x RBRITE_R
In the 1W burst dimming application example shown in figure 2 the
output current is set for nominally 3.5mA. RSNS is calculated
using the formula above as follows:
RSNS = 1180 x 4990 / 3.5 x 6550 = 256.8 ohms
A standard value of 255 ohms was chosen. It is recommended to
keep the value of the sense resistor in the range of 200 to 400 ohms
as stated above. If calculated value exceeds 400 ohms its best to
increase the value of the RBRITE_R resistor.
MECHANICAL DRAWING
PW 20-Pin Thin Small Shrink Outline (TSSOP)
c
123
E
D
E1
e
A2
A1
A
L
b
SEATING PLANE
1
MILLIMETERS INCHES
Dim MIN MAX MIN MAX
A - 1.10 - 0.043
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.031 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.008
D 6.40 6.60 0.252 0.260
E 6.25 6.55 0.246 0.258
E1 4.30 4.50 0.169 0.177
e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.018 0.030
Θ1 0° 8° 0° 8°
*LC - 0.10 - 0.004
* Lead Coplanarity
Note:
1. Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm(.006”) on any side.
Lead dimension shall not include solder coverage.
M
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Microsemi
Integrated Products
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 14
Copyright © 2000
Rev. 1.1, 2006-02-27
WWW.Microsemi .COM
LX1689
Third Generation CCFL Controller
P
RODUCTION
D
ATA
S
HEET
TM ®
NOTES
PRODUCTION DATA – Information contained in this document is proprietary to
Microsemi and is current as of publication date. This document may not be modified in
any way without the express written consent of Microsemi. Product processing does not
necessarily include testing of all parameters. Microsemi reserves the right to change the
configuration and performance of the product and to discontinue product at any time.
N
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