2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
IDT5T93GL161
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
FSEL
PD
GND
Q13
Q13
Q14
Q14
V
DD
SEL
Q15
Q15
Q16
Q16
V
DD
V
DD
GND
G1
A1
V
DD
GND
GND
V
DD
Q1
Q1
Q2
Q2
Q3
GND
Q3
Q4
Q4
A1
GND
GND
V
DD
Q12
Q12
Q11
Q11
Q10
GND
Q10
Q9
Q9
V
DD
A2
A2
G2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GL
V
DD
nc
GND
V
DD
V
DD
Q5
Q5
Q6
Q6
Q7
GND
Q7
Q8
Q8
nc
General Description
The IDT5T93GL161 2.5V differential clock buffer is a
user-selectable differential input to sixteen LVDS outputs. The
fanout from a differential input to sixteen LVDS outputs reduces
loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL161 can act as a translator
from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V
/ 2.5V LVTTL input can also be used to translate to LVDS outputs.
The redundant input capability allows for a glitchless change-over
from a primary clock source to a secondary clock source.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable LOW for up to three clock cycles of the
previously-selected input clock. The outputs will remain LOW for
up to three clock cycles of the newly-selected clock, after which
the outputs will start from the newly-selected input. A FSEL pin
has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL161 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the
value selected by the GL pin. Multiple power and grounds reduce
noise.
Applications
•Clock distribution
Features
•Guaranteed low skew: <75ps (maximum)
•Very low duty cycle distortion: <100ps (maximum)
•High speed propagation delay: <2.2ns (maximum)
•Up to 450MHz operation
•Selectable inputs
•Hot insertable and over-voltage tolerant inputs
•3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
•Selectable differential inputs to sixteen LVDS outputs
•Power-down mode
•At power-up, FSEL should be LOW
•2.5V VDD
•-40°C to 85°C ambient operating temperature
•Available in TQFP package
Pin Assignment
IDT5T93GL161
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
To p V i ew
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Block Diagram
GL
G1
PD
A1
A1
A2
G2
A2
SEL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q2
Q2
Q1
Q1
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
OUTPUT
CONTROL
Q12
Q12
Q14
Q14
Q15
Q15
Q16
Q16
Q13
Q13
Q11
Q11
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q10
Q10
OUTPUT
CONTROL
1
0
FSEL
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Table 1. Pin Descriptions
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)
NOTE: This parameter is measured at characterization but not tested.
Name Type Description
A[1:2] Input Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2] Input Adjustable (1, 4)
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].
For LVTTL single-ended operation, A[1:2] should be set to the desired toggle
voltage for A[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G1 Input LVTTL
Gate control for differential outputs Q1 and Q1 through Q8 and Q8. When G1 is
LOW, the differential outputs are active. When G1 is HIGH, the differential
outputs are asynchronously driven to the level designated by GL(2).
G2 Input LVTTL
Gate control for differential outputs Q9 and Q9 through Q16 and Q16. When G2
is LOW, the differential outputs are active. When G2 is HIGH, the differential
outputs are asynchronously driven to the level designated by GL(2).
GL Input LVTTL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and
"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW
and "complementary" outputs disable HIGH.
Q[1:16] Output LVDS Clock outputs.
Q{1:16} Output LVDS Complementary clock outputs.
SEL Input LVTTL Reference clock select. When LOW, selects A2 and A2.
When HIGH, selects A1 and A1.
PD Input LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into LOW
power mode. Inputs and outputs are disabled. Both "true" and "complementary"
outputs will pull to VDD. Set HIGH for normal operation.(3)
FSEL Input LVTTL At a rising edge, FSEL forces select to the input designated by SEL.
Set LOW for normal operation. At power-up, FSEL should be LOW.
VDD Power Power supply for the device core and inputs.
GND Power Ground.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 3pF
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Function Tables
Table 3A. Gate Control Output Table
Table 3B. Input Selection Table
Control Outputs Outputs
GL G Q[1:16] Q[1:16]
0 0 Toggling Toggling
01 LOW HIGH
1 0 Toggling Toggling
11 HIGH LOW
Selection SEL pin Inputs
0A2/A2
1A1/A1
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Recommended Operating Range
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics(1), TA = -40°C to 85°C
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
NOTE 2: The true input is held LOW and the complementary input is held HIGH.
Item Rating
Power Supply Voltage, VDD -0.5V to +3.6V
Input Voltage, VI-0.5V to +3.6V
Output Voltage, VO
Not to exceed 3.6V -0.5 to VDD +0.5V
Storage Temperature, TSTG -65°C to +150°C
Junction Temperature, TJ150°C
Symbol Description Minimum Typical Maximum Units
TAAmbient Operating Temperature -40 +25 +85 °C
VDD Internal Power Supply Voltage 2.3 2.5 2.7 V
Symbol Parameter Test Conditions Minimum Typical(2) Maximum Units
IDDQ
Quiescent VDD
Power Supply Current
VDD = Max.,
All Input Clocks = LOW(2); Outputs enabled 350 mA
ITOT
Total Power
VDD Supply Current
VDD = 2.7V;
FREFERENCE Clock = 450MHz 360 mA
IPD
Total Power Down
Supply Current PD = LOW 5 mA
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Table 4B. LVTTL DC Characteristics(1), TA = -40°C to 85°C
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.
NOTE 3: For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics(1), TA = -40°C to 85°C
NOTE 1: See Recommended Operating Range table.
NOTE 2: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and
VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW
input. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3: VCM specifies the maximum allowable range of (VTR + VCP) /2.
NOTE 4: Typical values are at VDD = 2.5V, +25°C ambient.
Symbol Parameter Test Conditions Minimum Typical(2) Maximum Units
IIH Input High Current VDD = 2.7V ±5 µA
IIL Input Low Current VDD = 2.7V ±5 µA
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA -0.7 -1.2 V
VIN DC Input Voltage -0.3 3.6 V
VIH DC Input High Voltage 1.7 V
VIL DC Input Low Voltage 0.7 V
VTHI DC Input Threshold Crossing Voltage VDD/2 V
VREF Single-Ended Reference Voltage (3) 3.3V LVTTL 1.65 V
2.5V LVTTL 1.25 V
Symbol Parameter Test Conditions Minimum Typical(2) Maximum Units
IIH Input High Current VDD = = 2.7V ±5 µA
IIL Input Low Current VDD = = 2.7V ±5 µA
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA -0.7 -1.2 V
VIN DC Input Voltage -0.3 3.6 V
VDIF DC Differential Voltage(3) 0.1 V
VCM DC Common Mode Input Voltage 0.05 VDD V
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Table 4D. LVDS DC Characteristics(1), TA = -40°C to 85°C
NOTE 1: See Recommended Operating Range table.
NOTE 2: Typical values are at VDD = 2.5V, +25°C ambient.
AC Electrical Characteristics
Table 5A. HSTL Differential Input AC Characteristics, TA = -40°C to 85°C
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Symbol Parameter Test Conditions Minimum Typical(2) Maximum Units
VOT(+)
Differential Output Voltage for the
True Binary State 247 454 mV
VOT(–)
Differential Output Voltage for the
False Binary State 247 454 mV
∆VOT
Change in VOT Between Complementary
Output States 50 mV
VOS
Output Common Mode Voltage
(Offset Voltage) 1.125 1.2 1.375 V
∆VOS
Change in VOS Between Complementary
Output States 50 mV
IOS Outputs Short Circuit Current VOUT+ and VOUT– = 0V 12 24 mA
IOSD Differential Outputs Short Circuit Current VOUT+ = VOUT– 612mA
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 750 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR / tFInput Signal Edge Rate(4) 2V/ns
IDT5T93GL161
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Table 5B. eHSTL AC Differential Input Characteristics, TA = -40°C to 85°C
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, TA = -40°C to 85°C
NOTE 1.The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment
(ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results
in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5D. LVDS Differential Input AC Characteristics, TA = -40°C to 85°C
NOTE 1.The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment
(ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
NOTE 2.A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 900 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR / tFInput Signal Edge Rate(4) 2V/ns
Symbol Parameter Maximum Units
VDIF Input Signal Swing(1) 732 mV
VXDifferential Input Cross Point Voltage(2) LVEPECL 1082 mV
LVPECL 1880 m
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR / tFInput Signal Edge Rate(4) 2V/ns
Symbol Parameter Maximum Units
VDIF Input Signal Swing(1) 400 mV
VXDifferential Input Cross Point Voltage(2) 1.2 V
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR / tFInput Signal Edge Rate(4) 2V/ns
IDT5T93GL161
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Table 5E. AC Differential Input Characteristics(1), TA = -40°C to 85°C
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has
been met or exceeded.
NOTE 2.VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3.IVCM specified the maximum allowable range of (VTR + VCP) /2.
Table 5F. AC Characteristics(1,5), TA = -40°C to 85°C
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.
NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and
load conditions on any one device.
NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any single differential output pair under
identical input and output interfaces, transitions and load conditions on any one device.
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two
devices, given identical transitions and load conditions at identical VDD levels and temperature.
NOTE 5. All parameters are tested with a 50% input duty cycle.
NOTE 6. Guaranteed by design but not production tested.
Symbol Parameter Minimum Typical Maximum Units
VDIF AC Differential Voltage(2) 0.1 3.6 V
VIX Differential Input Cross Point Voltage 0.05 VDD V
VCM Common Mode Input Voltage Range(3) 0.05 VDD V
VIN Input Voltage -0.3 3.6 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
tsk(o) Same Device Output Pin-to-Pin Skew (2) 75 ps
tsk(p) Pulse Skew(3) 100 ps
tsk(pp) Part-to-Part Skew(4) 300 ps
tpLH Propagation Delay, Low-to-High A/A Crosspoint to Qn/Qn
Crosspoint
1.5 2.2 ns
tpHL Propagation Delay, High-to-Low 1.5 2.2 ns
fo Frequency Range(6) 450 MHz
tPGE
Output Gate Enable Crossing
VTHI-to-Qn/Qn Crosspoint 3.5 ns
tPGD
Output Gate Disable Crossing
VTHI-to-Qn/Qn Crosspoint Driven to
GL Designated Level
3.5 ns
tPWRDN PD Crossing VTHI-to-Qn = VDD, Qn = VDD 100 µS
tPWRUP
Output Gate Disable Crossing VTHI to
Qn/Qn Driven to GL Designated Level 100 µS
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) = |tpHL – tpLH|
Note that the tpHL and tpLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time
the G signal to avoid this problem.
tPLH tPHL
tSK(O) tSK(O)
Qn - Qn
Qm - Qm
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
A[1:2] -A[1:2]
+VDIF
VDIF =0
-V
DIF
1/fo
t
PLH
GL
Gx
Qn - Qn
t
PGD
t
PGE
V
IH
V
THI
V
IL
V
IH
V
THI
V
IL
+ V
DIF
V
DIF
= 0
- V
DIF
A
[1:2]
- A
[1:2]
+ V
DIF
V
DIF
= 0
- V
DIF
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Glitchless Output Operation with Switching Input Clock Selection
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays
LOW for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
FSEL Operation for When Current Clock Dies
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When
this happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will
start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that
the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
A1-A1
A2-A2
SEL
Qn - Qn
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
VIH
VTHI
VIL
+VDIF
VDIF =0
-V
DIF
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FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state.
When this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after
a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that
the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart
with the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output
will be driven LOW and will restart with the input clock selected by the SEL pin.
A2-A2
A1-A1
FSEL VTHI
VIH
VIL
+VDIF
VDIF=0
-VDIF
VTHI
VIH
VIL
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
Qn - Qn
SEL
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Power Down Timing
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is
shown when Qn/Qn goes to VDIF = 0.
Gx
Qn - Qn
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
PD
A1 - A1
A2 - A2
VTHI
VIH
VIL
VTHI
VIH
VIL
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IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Test Circuits and Conditions
Test Circuit for Differential Input
Table 6A. Differential Input Test Conditions
Symbol VDD = 2.5V ± 0.2V Unit
VTHI Crossing of A and A V
VDD/2
D.U.T.
A
A
Pulse
Generator
~50
Transmission Line
~50
Transmission Line
VIN
VIN
-VDD/2
Scope
50
50
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Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
Table 6B. Differential Input Test Conditions
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.
Symbol VDD = 2.5V ± 0.2V Unit
CL
0(1) pF
8(1,2) pF
RL50 Ω
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator RL
RL
VOS VOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator 50
50
Z=50
Z=50
SCOPE
CL
-VDD/2
CL
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
16
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Package Outline
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
17
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Package Dimensions
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
18
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Ordering Information
Table 7. Ordering Information
IDT XXXXX
Package
Device Type
5T93GL161 2.5V LVDS 1:16 Glitchless Clock Buffe
r
Terabuffer II
Thin Quad Flat Pack
TQFP - Green
PF
PFG
XX
Process
X
-40 C to +85 C (Industrial)
I
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
19
IDT5T93GL161 REV. A SEPTEMBER 12, 2008
Revision History Sheet
Rev Table Page Description of Change Date
A
T3A
T3B
4
4
16
17
Added Gate Control Output Table.
Added Selection Table.
Added Package Outline.
Added Package Dimensions.
Updated datasheet format.
9/12/08
IDT5T93GL161
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
www.IDT.com
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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+408-284-8200 (outside USA)
Contact Information:
www.IDT.com
