DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT02
Quad 2-input NOR gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
FEATURES
•Output capability: standard
•ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT02 provide the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi + ∑ (CL×VCC2×fO) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
∑(CL×VCC2×fo) = sum of outputs
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay nA, nB to nY CL= 15 pF; VCC =5V 7 9 ns
C
Iinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1 and 2 22 24 pF
December 1990 3
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 10, 13 1Y to 4Y data outputs
2, 5, 8, 11 1A to 4A data inputs
3, 6, 9, 12 1B to 4B data inputs
7 GND ground (0 V)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
INPUTS OUTPUT
nA nB nY
L
L
H
H
L
H
L
H
H
L
L
L
December 1990 4
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB to nY
25
9
7
90
18
15
115
23
20
135
27
23 ns 2.0
4.5
6.0 Fig.6
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0 Fig.6
December 1990 5
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Notes to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
INPUT UNIT LOADCOEFFICIENT
nA, nB 1.50
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HCT UNIT VCC
(V) WAVEFORMS
+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nA, nB to nY 11 19 24 29 ns 4.5 Fig.6
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
HC: VM= 50%; VI= GND to VCC
HCT: VM= 1.3 V; VI= GND to 3 V.
