MC74HC574A Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS The MC74HC574A is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Data meeting the set-up time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HC574A is identical in function to the HC374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout. http://onsemi.com SOIC-20 DW SUFFIX CASE 751D * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 266 FETs or 66.5 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable These Devices are Pb-Free and are RoHS Compliant D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 Q0 OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND Q2 Q3 NONINVERTING OUTPUTS Q4 Q5 1 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK 20 20 HC 574A ALYWG G HC574A AWLYYWWG 1 SOIC-20 A WL, L YY, Y WW, W G or G 20 74HC574A AWLYWWG 1 TSSOP-20 SOEIAJ-20 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package Q6 (Note: Microdot may be in either location) Q7 FUNCTION TABLE 11 OUTPUT ENABLE 1 2 3 4 5 6 7 8 9 10 MARKING DIAGRAMS 1 Q1 SOEIAJ-20 F SUFFIX CASE 967 PIN ASSIGNMENT Features * * * * * TSSOP-20 DT SUFFIX CASE 948E Inputs PIN 20 = VCC PIN 10 = GND OE L L L H Figure 1. Logic Diagram Output Clock D Q L,H, X H L X X H L No Change Z X = Don't Care Z = High Impedance ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. (c) Semiconductor Components Industries, LLC, 2014 August, 2014 - Rev. 15 1 Publication Order Number: MC74HC574A/D MC74HC574A Value Units Internal Gate Count* 66.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW 0.0075 pJ Design Criteria Speed Power Product *Equivalent to a two-input NAND gate. MAXIMUM RATINGS Symbol VCC Parameter Value Unit -0.5 to +7.0 V -0.5 to VCC + 0.5 V -0.5 to VCC + 0.5 V DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current 20 mA IOK DC Output Diode Current 35 mA IO DC Output Sink Current 35 mA ICC DC Supply Current per Supply Pin 75 mA IGND DC Ground Current per Ground Pin 75 mA TSTG Storage Temperature Range -65 to +150 _C (Note 1) TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C TJ Junction Temperature under Bias +150 _C qJA Thermal Resistance SOIC TSSOP 96 128 _C/W PD Power Dissipation in Still Air at 85_C SOIC TSSOP 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup Level 1 Oxygen Index: 30% - 35% ESD Withstand Voltage Latchup Performance UL 94 V-0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) > 4000 > 300 > 1000 V 300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI, VO Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 2) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 _C 0 0 0 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level. http://onsemi.com 2 MC74HC574A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC V Guaranteed Limit -55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V |Iout| 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage Vin = VIH |Iout| 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VOH Minimum High-Level Output Voltage Vin = VIH 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 V VOL Maximum Low-Level Output Voltage Vin = VIL |Iout| 20 mA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA Vin = VIL Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 mA IOZ Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 0.5 5.0 10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA http://onsemi.com 3 MC74HC574A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns) Symbol VCC V Parameter Guaranteed Limit -55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5) 2.0 3.0 4.5 6.0 6.0 15 30 35 4.8 10 24 28 4.0 8.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures 2 and 5) 2.0 3.0 4.5 6.0 160 105 32 27 200 145 40 34 240 190 48 41 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) 2.0 3.0 4.5 60 140 90 28 24 175 120 35 30 210 140 42 36 ns tTLH, tTHL Maximum Output Transition Time, any Output (Figures 2 and 5) 2.0 3.0 4.5 6.0 60 27 12 10 75 32 15 13 90 36 18 15 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three-State Output Capacitance, Output in High-Impedance State 15 15 15 pF Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 24 pF *Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC -55 to 25_C Figure Volts Min Max 85_C Min Max 125_C Min Max Unit tsu Minimum Setup Time, Data to Clock 4 2.0 3.0 4.6 6.0 50 40 10 9.0 65 50 13 11 75 60 15 13 ns th Minimum Hold Time, Clock to Data 4 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock 2 2.0 3.0 4.5 6.0 75 60 15 13 95 80 19 16 110 90 22 19 ns Maximum Input Rise and Fall Times 2 2.0 3.0 4.5 6.0 tr, tf http://onsemi.com 4 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns MC74HC574A SWITCHING WAVEFORMS tr CLOCK tf VCC 90% 50% 10% tw VM GND GND 1/fmax tPLH Q VCC OUTPUT ENABLE 90% 50% 10% tPLZ tPZH tPHZ HIGH IMPEDANCE VM Q tPHL tPZL 10% VOL 90% VOH Q tTLH MC74HC574A: VM = VOH x 0.5 MC74HCT574A: VM = 1.3 V @ VCC = 3 V tTHL Figure 2. Figure 3. TEST POINT OUTPUT VALID VCC DATA DEVICE UNDER TEST 50% GND tsu th CL * VCC CLOCK 50% GND *Includes all probe and jig capacitance. Figure 4. Figure 5. D0 D1 D2 TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CL * D3 CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D4 D5 *Includes all probe and jig capacitance. D6 2 C Q D 19 3 C Q D 18 4 C Q D 17 5 C Q D 16 6 C Q D 15 7 C Q D 14 8 C Q D 13 9 C Q D 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Figure 6. Test Circuit D7 CLOCK OUTPUT ENABLE 11 1 Figure 7. Expanded Logic Diagram http://onsemi.com 5 Q7 MC74HC574A ORDERING INFORMATION Package Shipping MC74HC574ADWG SOIC-20 WIDE (Pb-Free) 38 Units / Rail MC74HC574ADWR2G SOIC-20 WIDE (Pb-Free) 1000 Tape & Reel MC74HC574ADTR2G TSSOP-20 (Pb-Free) 2500 Tape & Reel NLV74HC574ADTR2G* TSSOP-20 (Pb-Free) 2500 Tape & Reel MC74HC574AFELG SOEIAJ-20 (Pb-Free) 2000 Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable. http://onsemi.com 6 MC74HC574A PACKAGE DIMENSIONS SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HC574A PACKAGE DIMENSIONS TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE C 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V IIII IIII IIII K K1 S J J1 11 B -U- L PIN 1 IDENT SECTION N-N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N A -V- F DETAIL E -W- C G D H DETAIL E 0.100 (0.004) -T- SEATING PLANE DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 --0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 --0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC574A PACKAGE DIMENSIONS SOEIAJ-20 F SUFFIX CASE 967 ISSUE A 20 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c A1 b 0.13 (0.005) M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74HC574A/D