© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 15 1Publication Order Number:
MC74HC574A/D
MC74HC574A
Octal 3-State Noninverting
D Flip-Flop
High−Performance Silicon−Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
•Chip Complexity: 266 FETs or 66.5 Equivalent Gates
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
Figure 1. Logic Diagram
DATA
INPUTS
D0 219
Q0
D1
D2
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
3
4
5
6
7
8
9
11
1
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
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20
11
20
MARKING DIAGRAMS
SOIC−20
HC574A
AWLYYWWG
HC
574A
ALYWG
G
TSSOP−20 SOEIAJ−20
74HC574A
AWLYWWG
20
1
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
F SUFFIX
CASE 967
FUNCTION TABLE
Inputs Output
OE Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = Don’t Care
Z = High Impedance
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
614
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
VCC
CLOCK
Q7
Q6
Q5
Q4
PIN ASSIGNMENT
MC74HC574A
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2
Design Criteria Value Units
Internal Gate Count* 66.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0 mW
Speed Power Product 0.0075 pJ
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage −0.5 to VCC + 0.5 V
VODC Output Voltage (Note 1) −0.5 to VCC + 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±35 mA
IODC Output Sink Current ±35 mA
ICC DC Supply Current per Supply Pin ±75 mA
IGND DC Ground Current per Ground Pin ±75 mA
TSTG Storage Temperature Range −65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature under Bias +150 _C
qJA Thermal Resistance SOIC
TSSOP 96
128
_C/W
PDPower Dissipation in Still Air at 85_C SOIC
TSSOP 500
450 mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 4000
> 300
> 1000
V
ILatchup Latchup Performance Above VCC and Below GND at 85_C (Note 5) ±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VI, VODC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types −55 +125 _C
tr, tfInput Rise and Fall Time (Figure 2) VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
MC74HC574A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
VGuaranteed Limit
Symbol Parameter Test Conditions −55 to 25_C≤ 85_C≤ 125_CUnit
VIH Minimum High−Level Input
Voltage Vout = VCC – 0.1 V
|Iout| ≤ 20 mA2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage Vout = 0.1 V
|Iout| ≤ 20 mA2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage Vin = VIH
|Iout| ≤ 20 mA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VOH Minimum High−Level Output
Voltage Vin = VIH |Iout| ≤ 2.4 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
VOL Maximum Low−Level Output
Voltage Vin = VIL
|Iout| ≤ 20 mA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIL |Iout| ≤ 2.4 mA
|Iout| ≤ 6.0 mA
|Iout| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin Maximum Input Leakage
Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State
Leakage Current Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ±0.5 ±5.0 ±10 mA
ICC Maximum Quiescent Supply
Current (per Package) Vin = VCC or GND
Iout = 0 mA6.0 4.0 40 160 mA
MC74HC574A
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4
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
VCC
VGuaranteed Limit
Symbol Parameter −55 to 25_C≤ 85_C≤ 125_CUnit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 5) 2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL Maximum Propagation Delay, Clock to Q
(Figures 2 and 5) 2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6) 2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6) 2.0
3.0
4.5
6 0
140
90
28
24
175
120
35
30
210
140
42
36
ns
tTLH,
tTHL Maximum Output Transition Time, any Output
(Figures 2 and 5) 2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
Cin Maximum Input Capacitance 10 10 10 pF
Cout Maximum Three−State Output Capacitance, Output in High−Impedance
State 15 15 15 pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Enabled Output)* 24 pF
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC –55 to 25_C≤ 85_C≤ 125_C
Symbol Parameter Figure Volts Min Max Min Max Min Max Unit
tsu Minimum Setup Time, Data to Clock 4 2.0
3.0
4.6
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
thMinimum Hold Time, Clock to Data 4 2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
twMinimum Pulse Width, Clock 2 2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
tr, tfMaximum Input Rise and Fall Times 2 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC574A
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5
Figure 2. Figure 3.
CLOCK
Q
trtfVCC
GND
90%
50%
10%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
1/fmax Q
Q
VM
VM
90%
10%
tPZL tPLZ
tPZH tPHZ
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
OUTPUT
ENABLE
SWITCHING WAVEFORMS
Figure 4. Figure 5.
Figure 6. Test Circuit
Figure 7. Expanded Logic Diagram
50%CLOCK
VCC
VALID
GND
VCC
GND
tsu th
50%DATA
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
C
DQ
2
D0 19 Q0
C
DQ
3
D1 18 Q1
C
DQ
4
D2 17 Q2
C
DQ
5
D3 16 Q3
C
DQ
6
D4 15 Q4
C
DQ
7
D5 14 Q5
C
DQ
8
D6 13 Q6
C
DQ
9
D7 12 Q7
11
CLOCK
1
OUTPUT ENABLE
MC74HC574A: VM = VOH x 0.5
MC74HCT574A: VM = 1.3 V @ VCC = 3 V
MC74HC574A
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6
ORDERING INFORMATION
Device Package Shipping†
MC74HC574ADWG SOIC−20 WIDE
(Pb−Free) 38 Units / Rail
MC74HC574ADWR2G SOIC−20 WIDE
(Pb−Free) 1000 Tape & Reel
MC74HC574ADTR2G TSSOP−20
(Pb−Free) 2500 Tape & Reel
NLV74HC574ADTR2G* TSSOP−20
(Pb−Free) 2500 Tape & Reel
MC74HC574AFELG SOEIAJ−20
(Pb−Free) 2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC74HC574A
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7
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X A1
A
SEATING
PLANE
q
hX 45_
E
D
M
0.25 M
B
M
0.25 S
AS
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D12.65 12.95
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
MC74HC574A
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8
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E 6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC574A
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9
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967
ISSUE A
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.15 0.25 0.006 0.010
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.81 --- 0.032
A1
HE
Q1
LE
_10 _0
_10 _
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
HE
A1
LEQ1
_
c
A
ZD
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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UBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
MC74HC574A/D
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