NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Based on DDR2-533/667/800 64Mx16 (1GB)/128Mx8 (2GB) SDRAM C-Die Features * Performance: PC2-4200 PC2-5300 PC2-6400 PC2-6400 -37B -3C -AD -AC 4 5 6 5 fck - Clock Freqency 266 333 400 400 MHz tck - Clock Cycle 3.75 3 2.5 2.5 ns Data Transfer Speed 533 667 800 800 Speed Sort DIMM CAS Latency * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 1GB: 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx16 DDR2 SDRAM C Die devices. * 2GB: 256Mx64 Unbuffered DDR2 SO-DIMM based on 128Mx8 DDR2 SDRAM C Die devices. * Intended for 266MHz, 333MHz, and 400MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 8 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Serial Presence Detect Unit Mbps * Programmable Operation: - DIMM Latency: 3, 4, 5 (-37B/-3C/-AC) - DIMM Latency: 4, 5, 6 (-AD) - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/2 Addressing (1GB) * 14/10/2 Addressing (2GB) * 7.8 s Max. Average Periodic Refresh Interval * Gold contacts * 1GB module's SDRAMs are 84-ball BGA Package * 2GB module's SDRAMs are 60-ball BGA Package * RoHS compliance Description NT1GT64UH8C0FN and NT2GT64U8HC0BN are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 (1GB)/256Mx64 (2GB) high-speed memory array. NT1GT64UH8C0FN uses eight 64Mx16 84-ball BGA packaged devices and NT2GT64U8HC0BN use sixteen 128Mx8 60-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint. The DIMM is intended for use in applications operating of 266MHz/333MHz/400MHz clock speeds and achieves high-speed data transfer speed of 533Mbps/667Mbps/800Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A12 (1GB) / A0-A13 (2GB) and I/O inputs BA0, BA1 and BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.1 02/2008 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Ordering Information Part Number Speed Organization NT2GT64U8HC0BN -AC DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5) NT2GT64U8HC0BN -AD DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6) NT2GT64U8HC0BN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) NT2GT64U8HC0BN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) NT1GT64UH8C0FN -AC DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 5) NT1GT64UH8C0FN -AD DDR2-800 PC2-6400 400MHz (2.5ns @ CL = 6) NT1GT64UH8C0FN -3C DDR2-667 PC2-5300 333MHz (3ns @ CL = 5) NT1GT64UH8C0FN -37B DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) REV 1.1 02/2008 Power Leads 1.8V Gold Note 256Mx64 128Mx64 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Pin Description CK0, CK1, , CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable DQS0-DQS7 Row Address Strobe - Column Address Strobe , A0-A9 A11-A13 A0-A9 A10/AP Data input/output Bidirectional data strobes Differential data strobes DM0-DM7 Input Data Masks Write Enable VDD Power (1.8V) Chip Selects VREF Ref. Voltage for SSTL_18 inputs Row Address Inputs VDDSPD Column Address Inputs Serial EEPROM positive power supply VSS Ground Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1, BA2 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 NC Serial Presence Detect Address Inputs No Connect Note: A13 is for 2GB modules only. REV 1.1 02/2008 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM 1GB/2GB DDR2 SDRAM SODIMM Pinout Pin Front Pin 1 VREF 3 VSS 5 DQ0 7 DQ1 9 VSS 11 Back Pin Front Pin Back Pin Front Pin 2 VSS 51 DQS2 52 DM2 4 DQ4 53 VSS 54 VSS 6 DQ5 55 DQ18 56 8 VSS 57 DQ19 10 DM0 59 VSS 101 A1 103 VDD DQ22 105 58 DQ23 107 60 VSS 109 12 VSS 61 DQ24 62 DQ28 111 DQS0 14 DQ6 63 DQ25 64 DQ29 113 15 VSS 16 DQ7 65 VSS 66 VSS 115 17 DQ2 18 VSS 67 DM3 68 19 DQ3 20 DQ12 69 NC 70 21 VSS 22 DQ13 71 VSS 23 DQ8 24 VSS 73 DQ26 25 DQ9 26 DM1 75 DQ27 27 VSS 28 VSS 77 VSS 30 CK0 79 13 29 Back Pin Front Pin Back 102 A0 151 DQ42 152 DQ46 104 VDD 153 DQ43 154 DQ47 A10/AP 106 BA1 155 VSS 156 VSS BA0 108 157 DQ48 158 DQ52 110 159 DQ49 160 DQ53 VDD 112 VDD 161 VSS 162 VSS 114 ODT0 163 NC 164 CK1 A13/NC 165 VSS 166 116 117 VDD 118 VDD 167 DQS3 119 ODT1 120 NC 169 168 VSS DQS6 170 DM6 72 VSS 121 VSS 122 VSS 74 DQ30 123 DQ32 124 DQ36 171 VSS 172 VSS 173 DQ50 174 DQ54 76 DQ31 125 DQ33 126 78 VSS 127 VSS 128 DQ37 175 DQ51 176 DQ55 VSS 177 VSS 178 CKE0 80 CKE1 129 130 VSS DM4 179 DQ56 180 DQ60 31 DQS1 32 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 BA2 86 NC 135 DQ34 136 DQ39 185 DM7 186 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 49 Note: All pin assignments are consistent for all 8-byte unbuffered versions. A13 is for 2GB modules only. REV 1.1 02/2008 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 (SSTL) Positive Edge The positive line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising edge of their associated clocks. , (SSTL) Negative Edge The negative line of the differential pair of system clock inputs which drives the input to the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, executed by the SDRAM. , , VREF Supply , , define the operation to be Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1, BA2 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12/A13 define the row address (RA0-RA12/RA13) when sampled at the rising clock edge. A13 applies on 2GB SODIMM only. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1/BA2 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1/BA2 to control which bank(s) to precharge. If AP is high all 8 banks will be precharged regardless of the state of BA0/BA1/BA2. If AP is low, then BA0/BA1/BA2 are used to define which bank to pre-charge. A0 - A9 A10/AP A11, A12/A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - (SSTL) Negative and Positive Edge Input Active High DM0 - DM7 On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR2 SDRAM input buffers and core logic Data strobe for input and output data The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA1 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.1 02/2008 Supply Serial EEPROM positive power supply. 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Functional Block Diagram [1GB - 2 Ranks, 64Mx16 DDR2 SDRAMs] REV 1.1 02/2008 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Functional Block Diagram [2GB - 2 Ranks, 128Mx8 DDR2 SDRAMs] REV 1.1 02/2008 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (1GB - 2 Ranks, 64Mx16 DDR2 SDRAMs) (Part 1 of 2) SPD Entry Value Serial PD Data Entry (Hex.) Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Ranks, Package, and Height 6 Data Width of Assembly 7 Reserved 8 Voltage Interface Level of this Assembly SSTL_1.8V 9 DDR2 SDRAM Device Cycle Time at CL=X 3.75ns 3.0ns 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=X 0.5ns 0.45ns 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width X16 10 10 10 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 00 00 00 15 Reserved Undefined 00 00 00 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 0C 0C 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 8 08 08 08 08 18 DDR2 SDRAM Device Attributes: Supported 38 38 70 38 19 DIMM Mechanical Characteristics <3.80mm 01 01 01 01 20 DDR2 SDRAM DIMM Type Information -37B Latencies -3C -AD -AC -37B -3C -AD -AC 128 80 80 80 80 256 08 08 08 08 DDR2-SDRAM 08 08 08 08 13 0D 0D 0D 0D 10 0A 0A 0A 0A 2 ranks, Height=30mm 61 61 61 61 X64 40 40 40 40 Undefined 00 00 00 00 05 05 05 05 2.5ns 3D 30 25 25 0.40ns 50 45 40 40 Non Address/Command Parity, Non Data ECC, Non Data Parity, 00 00 00 00 7.8 s/self 82 82 82 82 3,4,5 4,5,6 3,4,5 SODIMM (67.6mm) 04 04 04 04 Analysis probe installed : No, FET Switch External Enable : No, Number of PLLs : 0, Number of Active Registers : 1, 00 00 00 00 Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 07 07 07 07 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=X-1 3.75ns 3.0ns 3.75ns 3D 3D 30 3D 24 Maximum Data Access Time from Clock at CL=X-1 0.5ns 0.45ns 0.5ns 50 50 45 50 25 Minimum Clock Cycle Time at CL=X-2 5ns 3.75ns 5ns 50 50 3D 50 26 Maximum Data Access Time from Clock at CL=X-2 0.6ns 0.5ns 0.6ns 60 60 50 60 27 Minimum Row Precharge Time (tRP) 12.5ns 3C 3C 3C 32 28 Minimum Row Active to Row Active delay (tRRD) 28 28 28 28 29 Minimum 3C 3C 3C 32 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 2D 2D 2D 31 Module Rank Density 512MB 80 80 80 80 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.2ns 0.17ns 25 20 17 17 33 Address and Command Hold Time After Clock (tIH) 0.37ns 0.27ns 0.25ns 37 27 25 25 34 Data Input Setup Time Before Clock (tDS) 0.5ns 10 10 05 05 35 Data Input Hold Time After Clock (tDH) 0.12ns 22 17 12 12 36 Write Recovery Time (tWR) 3C 3C 3C 3C REV 1.1 02/2008 to 15ns 10ns delay (tRCD) 15ns 12.5ns 0.1ns 0.22ns 0.17ns 15ns Note 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (1GB - 2 Ranks, 64Mx16 DDR2 SDRAMs) (Part 2 of 2) Byte Description SPD Entry Value -37B -3C -AD Serial PD Data Entry (Hex.) -37B -3C -AD -AC 37 Internal Write to Read Command delay (tWTR) 7.5ns -AC 1E 1E 1E 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 1E 1E 1E 39 Reserved Undefined 00 00 00 00 The number below a decimal point of tRC=0 and tRFC=5, tRFC is less than 256ns 06 06 06 36 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 60ns 3C 3C 3C 39 42 Min. Auto Refresh Command Cycle Time (tRFC) 127ns 7F 7F 7F 7F 43 Maximum Clock Cycle Time (tCK) 8.0ns 80 80 80 80 44 Max. DQS-DQ Skew Factor (tQHS) 0.3ns 0.24ns 0.2ns 1E 18 14 14 45 Read Data Hold Skew Factor (tQHS) 0.4ns 0.34ns 0.3ns 28 22 1E 1E 00 00 00 00 46-61 Reserved 62 SPD Reversion 63 Checksum for Byte 0-62 Undefined 1.3 13 13 13 13 Checksum Data EE AA 74 90 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 Module Manufacturing Location Manufacturing code - 73-91 Module Part number Module Part Number in ASCII - undefined - 92-255 Reserved Note Note 1: Module part number: NT1GT64UH8C0FN-37B 4E5431475436345548384330464E2D33374220 NT1GT64UH8C0FN-3C 4E5431475436345548384330464E2D33432020 NT1GT64UH8C0FN-AD 4E5431475436345548384330464E2D41442020 NT1GT64UH8C0FN-AC 4E5431475436345548384330464E2D32354320 REV 1.1 02/2008 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 1 NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (2GB - 2 Ranks, 128Mx8 DDR2 SDRAMs) (Part 1 of 2) SPD Entry Value Serial PD Data Entry (Hex.) Byte Description -37B -3C -AD -AC 0 Number of Serial PD Bytes Written during Production 128 80 80 80 80 1 Total Number of Bytes in Serial PD device 256 08 08 08 08 2 Fundamental Memory Type DDR2 SDRAM 08 08 08 08 3 Number of Row Addresses on Assembly 14 0E 0E 0E 0E 4 Number of Column Addresses on Assembly 10 0A 0A 0A 0A 5 Number of DIMM Ranks, Package, and Height Module Height = 30.0mm, 2 ranks 61 61 61 61 6 Data Width of Assembly X64 40 40 40 40 7 Reserved Undefined 00 00 00 00 8 Voltage Interface Level of this Assembly 05 05 05 05 9 DDR2 SDRAM Device Cycle Time at CL=X 3.75ns 3ns 2.5ns 3D 30 25 25 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=X 0.5ns 0.45ns 0.4ns 50 45 40 40 11 DIMM Configuration Type Non Address/Command Parity, Non Data ECC, Non Data Parity, 00 00 00 00 12 Refresh Rate/Type 7.8 s 82 82 82 82 13 Primary DDR2 SDRAM Width X8 08 08 08 08 14 Error Checking DDR2 SDRAM Device Width Undefined 00 00 00 00 15 Reserved Undefined 00 00 00 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 0C 0C 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 8 08 08 08 08 18 DDR2 SDRAM Device Attributes: Supported 38 38 70 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information -37B Latencies -3C -AD -AC SSTL 1.8V 3,4,5 4,5,6 x 3,4,5 01 01 01 01 SO-DIMM (67.6mm) 3.80 (mm) 04 04 04 04 Analysis probe installed : No, FET Switch External Enable : No, Number of PLLs : 0, Number of Active Registers : 1, 00 00 00 00 Supports Weak Driver, Supports 50 ohm ODT, Supports PASR, 07 07 07 07 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=X-1 3.75ns 3ns 3.75ns 3D 3D 30 3D 24 Maximum Data Access Time from Clock at CL=X-1 0.5ns 0.45ns 0.5ns 50 50 45 50 25 Minimum Clock Cycle Time at CL=X-2 5ns 3.75ns 5ns 50 50 3D 50 26 Maximum Data Access Time from Clock at CL=X-2 0.6ns 0.5ns 0.6ns 60 60 50 60 27 Minimum Row Precharge Time (tRP) 12.5ns 3C 3C 3C 32 28 Minimum Row Active to Row Active delay (tRRD) 1E 1E 1E 1E 29 Minimum 3C 3C 3C 32 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 2D 2D 2D 31 Module Rank Density 1GB 01 01 01 01 32 Address and Command Setup Time Before Clock (tIS) 0.25ns 0.2ns 0.17ns 25 20 17 17 33 Address and Command Hold Time After Clock (tIH) 0.37ns 0.27ns 0.25ns 37 27 25 25 34 Data Input Setup Time Before Clock (tDS) 0.05ns 10 10 05 05 35 Data Input Hold Time After Clock (tDH) 0.12ns 22 17 12 12 36 Write Recovery Time (tWR) 3C 3C 3C 3C REV 1.1 02/2008 to 15ns 7.5ns delay (tRCD) 15ns 12.5ns 0.1ns 0.22ns 0.17ns 15ns Note 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Serial Presence Detect (2GB - 2 Ranks, 128 M x 8 DDR2 SDRAMs) (Part 2 of 2) Byte Description SPD Entry Value -37B -3C -AD Serial PD Data Entry (Hex.) -37B -3C -AD -AC 37 Internal Write to Read Command delay (tWTR) 7.5ns -AC 1E 1E 1E 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 1E 1E 1E 39 Reserved Undefined 00 00 00 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 06 06 06 36 60ns 3C 3C 3C 39 127.5ns 7F 7F 7F 7F 8ns 80 80 80 80 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tQHS) 0.3ns 0.24ns 0.2ns 1E 18 14 14 45 Read Data Hold Skew Factor (tQHS) 0.4ns 0.34ns 0.3ns 28 22 1E 1E 00 00 00 00 46-61 Reserved 62 SPD Reversion 63 Checksum for Byte 0-62 Undefined 1.3 13 13 13 13 Checksum Data 5E 1A E4 00 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 Module Manufacturing Location Manufacturing code - 73-91 Module Part number Module Part Number in ASCII - undefined - 92-255 Reserved Note Note 1: Module part number: NT2GT64U8HC0BN-37B 4E5432475436345538484330424E2D33374220 NT2GT64U8HC0BN-3C 4E5432475436345538484330424E2D33432020 NT2GT64U8HC0BN-AD 4E5432475436345538484330424E2D41442020 NT2GT64U8HC0BN-AC 4E5432475436345538484330424E2D41432020 REV 1.1 02/2008 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 1 NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Environmental Requirements Symbol Rating Units Operating Temperature (ambient) 0 to 65 C HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature -50 to 100 C HSTG Storage Humidity (without condensation) 5 to 95 % 105 to 69 kPa TOPR Parameter Barometric pressure (operating & storage) up to 9850ft. Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Absolute Maximum DC Ratings Symbol Rating Units Voltage on VDD pins relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V VDD VIN, VOUT TSTG Parameter Voltage on I/O pins relative to Vss -0.5 to +2.3 V Storage Temperature (Plastic) -55 to +100 C Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage temperature is the case surface temperature on the center/top side of the DRAM. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 s DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V Input Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 Termination Voltage VREF - 0.04 VREF + 0.04 V 3 VSS, VSSQ VREF VTT Supply Voltage, I/O Supply Voltage Note: 1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However, VDDQ must be less than or equal to VDD under all conditions. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. REV 1.1 02/2008 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM ODT DC Electrical Characteristics Parameter/Condition Symbol Min. Nom. Max. Units Note Rtt effective impedance value for EMRS(A6,A2)=0,1; 75ohm Rtt1(eff) 60 75 90 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,0; 150ohm Rtt2(eff) 120 150 180 ohm 1 Rtt effective impedance value for EMRS(A6,A2)=1,1; 50ohm Rtt3(eff) 40 50 60 ohm 1 Deviation of VM with respect to VDDQ/2 Delta VM -6 +6 % 1 Note1: Test condition for Rtt measurements. Input AC/DC logic level Symbol Parameter VIH (AC) Input High (Logic1) Voltage VIL (AC) Input Low (Logic0) Voltage VIH (DC) Input High (Logic1) Voltage VIL (DC) Input Low (Logic0) Voltage REV 1.1 02/2008 PC2-4200 PC2-5300 PC2-6400 Units Min. Max. Min. Max. Min. Max. VREF + 0.250 - VREF + 0.200 - VREF + 0.200 - V - VREF 0.250 - VREF 0.200 - VREF 0.200 V VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 V -0.3 VREF 0.125 -0.3 VREF 0.125 -0.3 VREF 0.125 V 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V [1GB, 2 Ranks, 64Mx16 DDR2 SDRAMs] Symbol Parameter/Condition IDD0 IDD1 PC2-4200 PC2-5300 PC2-6400 PC2-6400 Unit (-37B) (-3C) (-AD) (-AC) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 634 720 806 806 mA Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 731 790 885 885 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 70 70 70 70 mA IDD2Q Precharge quiet standby current 422 466 519 519 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 519 590 660 660 mA IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 212 227 243 243 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 100 100 100 100 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 529 586 644 644 mA IDD4R Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 879 987 1097 1097 mA IDD4W Operating Current: one bank; Burst = 4; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 775 863 953 953 mA Burst Refresh Current: tRC = tRFC (MIN) 1144 1261 1312 1312 mA 79 79 79 79 mA 1350 1613 1863 1863 mA IDD5B IDD6 Self-Refresh Current: CKE 0.2V IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.1 02/2008 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V [2GB, 2 Ranks, 128M x 8 DDR2 SDRAMs] Symbol Parameter/Condition IDD0 IDD1 PC2-4200 PC2-5300 PC2-6400 PC2-6400 Unit (-37B) (-3C) (-AD) (-AC) Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1196 1363 1538 1538 mA Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1135 1279 1436 1436 mA IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 141 141 141 141 mA IDD2Q Precharge quiet standby current 796 883 981 981 mA IDD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 998 1128 1265 1265 mA IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 415 440 476 476 mA IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 185 187 189 189 mA IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 964 1073 1192 1192 mA IDD4R Operating Current: one bank; Burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 1296 1457 1627 1627 mA IDD4W Operating Current: one bank; Burst = 4; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 1201 1335 1479 1479 mA Burst Refresh Current: tRC = tRFC (MIN) 2242 2473 2576 2576 mA IDD6 Self-Refresh Current: CKE 0.2V 158 158 158 158 mA IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1830 2138 3636 3636 mA IDD5B Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.1 02/2008 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -37B Parameter -3C -AD/-AC Unit Min. Max. Min. Max. Min. Max. DQ output access time from CK/ -0.5 +0.5 -0.45 +0.45 -0.40 +0.40 ns DQS output access time from CK/ -0.45 +0.45 -0.4 +0.4 -0.35 +0.35 ns tCH CK high-level width 0.45 0.55 0.48 0.52 0.48 0.52 tCK tCL CK low-level width 0.45 tAC tDQSCK 0.55 0.48 0.52 0.48 0.52 tCK tCH or tCL - tCH or tCL - tCH or tCL - tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCK Clock Cycle Time 3.75 8 3 8 2.5 8 ns tDH DQ and DM input hold time 225 - 175 - 125 - ps tDS DQ and DM input setup time 100 - 100 - 50 - ps tIPW Input pulse width 0.6 - 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - 0.35 - tCK - tAC (max) - tAC (max) - tAC (max) ns tAC (max) ns tAC (max) ns tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ 2tAC tAC (max) (min) 2tAC tAC (max) (min) 2tAC (min) tAC (min) tAC (max) tAC (min) tAC (max) tAC (min) DQS-DQ skew (DQS & associated DQ signals) - 0.30 - 0.24 - 0.20 ns tQHS Data hold Skew Factor - 0.4 - 0.34 - 0.30 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - tHP tQHS - ns tDQSQ tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK tDQSH DQS input high pulse width 0.35 - 0.35 - 0.35 - tCK tDQSL DQS input low pulse width 0.35 - 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - 2 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - 0.35 - tCK tIH Address and control input hold time 0.375 - 0.275 - 0.250 - ns tIS Address and control input setup time 0.25 - 0.2 - 0.175 - ns tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 0.4 0.6 tCK tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tIS + tCK + tIH - tIS + tCK + tIH - tIS + tCK + tIH - ns tRFC Refresh to active/Refresh command time tREFI REV 1.1 02/2008 127.5 127.5 127.5 ns Average Periodic Refresh Interval (85C < TCASE 95C) 3.9 3.9 3.9 s Average Periodic Refresh Interval (0C TCASE 85C) 7.8 7.8 7.8 s Notes 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tRRD tCCD -37B Parameter Active bank A to Active bank B command -3C -AD/-AC Unit Min. Max. Min. Max. Min. Max. 7.5 - 7.5 - 7.5 - ns 2 - 2 - 2 - tCK - 15 - 15 - ns to tWR Write recovery time WR Write recovery time with Auto-Precharge tDAL Auto precharge write recovery + precharge time WR +tRP - WR +tRP - WR +tRP - tCK tWTR Internal write to read command delay 7.5 - 7.5 - 7.5 - ns tRTP Internal read to precharge command delay 7.5 - 7.5 - 7.5 - ns tXSNR Exit self refresh to a Non-read command tRFC +10 - tRFC +10 - tRFC +10 - ns tXSRD Exit self refresh to a Read command 200 - 200 - 200 - tCK Exit precharge power down to any Non- read command 2 - 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - 2 - tCK tXARDS Exit active power down to read command 6-AL - 7-AL - 8-AL - tCK 3 - 3 - 3 - tCK 0 12 0 12 0 12 ns 2 2 2 2 2 2 tCK ODT turn-on tAC(min) tAC(max) tAC(min) tAC(max) tAC(min) tAC(max) ns ODT turn-on (Power down mode) tAC(min) +2 2tCK + tAC(max) +1 tAC(min) +2 2tCK + tAC(max) +1 tAC(min) +2 2tCK + tAC(max) +1 ns 2.5 2.5 2.5 2.5 2.5 2.5 tCK tAC(min) tAC(max) +0.6 tAC(min) tXP tCKE CKE minimum pulse width tOIT OCD drive mode output delay 15 tWR/tCK tWR/tCK tWR/tCK Notes ns ODT tAOND tAON tAONPD ODT turn-on delay +0.7 +0.7 +0.7 tAOFD ODT turn-off delay tAOF ODT turn-off tAC(min) tAC(max) +0.6 tAC(max) +0.6 ns tAOFPD ODT turn-off (Power down mode) tAC(min) +2 2.5tCK + 2.5tCK + 2.5tCK + t t tAC(max) AC(min) tAC(max) AC(min) tAC(max) +2 +2 +1 +1 +1 ns tANPD ODT to power down entry latency 3 - 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - 8 - tCK Speed Grade Definition Symbol Parameter -37B -3C -AD -AC Min. Max. Min. Max. Min. Max. Min. Max. Unit tRAS Row Active Time 45 70000 45 70000 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 15 - 15 - 12.5 - ns tRC Row Cycle Time 60 - 60 - 60 - 57.5 - ns tRP Row Precharge Time 15 - 15 - 15 - 12.5 - ns REV 1.1 02/2008 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Package Dimensions [1GB - 2 Ranks, 64Mx16 DDR2 SDRAMs] 6 " " ! 012 6 5 " 012 012 # $ %& '(#'( ) *+, - . # ) ', (#/012 4' ($5 & )( ',. ( " 3' ((#. )- ( ( % Note: Device position and scale are only for reference. REV 1.1 02/2008 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Package Dimensions [2GB - 2 Ranks, 128Mx8 DDR2 SDRAMs] 6 " " ! 6 5 012 " "" "5 012 012 # $ %& '(#'( ) *+, - . # ) ', (#/012 4' ($5 & )( ',. ( " 3' ((#. )- ( ( % Note: Device position and scale are only for reference. REV 1.1 02/2008 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GT64UH8C0FN / NT2GT64U8HC0BN 1GB: 128M x 64 / 2GB: 256M x 64 PC2-4200 / PC2-5300 / PC2-6400 Unbuffered DDR2 SO-DIMM Revision Log Rev Date Modification 0.1 08/2007 Preliminary Release 1.0 01/2008 Official Release 1.1 02/2008 Update New IDD Currents Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2006 REV 1.1 02/2008 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.