DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs 256MB 512MB 1GB 2GB - W1D32M72R8 W1D64M72R8 W1D128M72R8 W1D256M72R8 (Preliminary*) Features: * * * * * * * * * * * * Figure 1: Available layouts 240-pin Registered ECC DDR2 SDRAM Dual-InLine Memory Module for DDR2-400 and DDR2-533 JEDEC standard VDD=1.8V (+/- 0.1V) power supply One rank 256MB, 512MB, 1GB, and 2GB Modules are built with 18 x8 DDR2 SDRAM devices in a 60-ball FBGA package ECC error detection and correction Programmable CAS Latency of 3 and 4; Burst Length of 4 and 8 Auto Refresh and Self Refresh Mode OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) SPD (Serial Presence Detect) with EEPROM All input/output are SSTL_18 compatible All contacts are gold plated One clock delay for register Layout A: 1.181" Layout B: 1.0" Front view of double-sided DIMM (see detail physical dimensions at the back) Speed Grades: Speed Grade -5 -3.75 Units Module Speed Grade PC2-3200 PC2-4200 Speed @ CL3 Speed @ CL4 Speed @ CL5 400 400 - 533 533 MHz MHz MHz Note: See Product ordering for full naming guide Description: The following specification covers the W1D32M72R8, W1D64M72R8, W1D128M72R8, and W1D256M72R8 family of Single-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for available layout configurations and the product ordering guide on the final page of this specification for available options including speed grade and silicon manufacturer. Address Summary Table: Module Configuration Refresh Device Configuration Row Addressing Column Addressing Module Rank 256MB 32M x 72 8k 32M x 8 (9 components) A0-A13 A0-A9 1 512MB 64M x 72 8K 64M x 8 (9 components) A0-A13 A0-A9 1 1GB 128M x 72 8K 128M x 8 (9 components) A0-A14 A0-A9 1 2GB 256M x 72 8K 256M x 8 (9 components) A0-A14 A0-A9 1 *Specifications are for reference purposes only and are subject to change by Wintec without notice. DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 1 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Pin Configuration: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ19 61 A4 91 VSS 121 VSS 151 VSS VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 DQ25 64 VDD 94 VSS 124 VSS 154 VSS VSS KEY 95 DQ42 125 DM0/DQS9 155 DM3/DQS12 DQS3# 65 VSS 96 DQ43 126 NC/DQS9# 156 NC/DQS12# DQS3 66 VSS 97 VSS 127 VSS 157 VSS VSS 67 VDD 98 DQ48 128 DQ6 158 DQ30 DQ26 68 NC 99 DQ49 129 DQ7 159 DQ31 DQ27 69 VDD 100 VSS 130 VSS 160 VSS VSS 70 A10/AP 101 SA2 131 DQ12 161 CB4 CB0 71 BA0 102 NC,TEST1 132 DQ13 162 CB5 CB1 72 VDDQ 103 VSS 133 VSS 163 VSS VSS 73 WE# 104 DQS6# 134 DM1/DQS10 164 DM8/DQS17 DQS8# 74 CAS# 105 DQS6 135 NC/DQS10# 165 NC/DQS17# DQS8 75 VDDQ 106 VSS 136 VSS 166 VSS VSS 76 S1# 107 DQ50 137 RFU 167 CB6 CB2 77 ODT1 108 DQ51 138 RFU 168 CB7 CB3 78 VDDQ 109 VSS 139 VSS 169 VSS VSS 79 VSS 110 DQ56 140 DQ14 170 VDDQ VDDQ 80 DQ32 111 DQ57 141 DQ15 171 CKE1 CKE0 81 DQ33 112 VSS 142 VSS 172 VDD VDD 82 VSS 113 DQS7# 143 DQ20 173 A15 A16,BA2 83 DQS4# 114 DQS7 144 DQ21 174 A14 NC 84 DQS4 115 VSS 145 VSS 175 VDDQ VDDQ 85 VSS 116 DQ58 146 DM2/DQS11 176 A12 A11 86 DQ34 117 DQ59 147 NC/DQS11# 177 A9 A7 87 DQ35 118 VSS 148 VSS 178 VDD VDD 88 VSS 119 SDA 149 DQ22 179 A8 A5 89 DQ40 120 SCL 150 DQ23 180 A6 90 DQ41 NC - No Connect, RFU - Reserved for Future Use 1. The Test pin (Pin 102) is reserved for bus analysis and is not connected on normal memory modules 2. CKE1 and S1# pin are used for dual-rank Registered DIMM 3. A13 (Pin 196) is for 512MB and above DIMM. Pin 181 182 183 184 Symbol VDDQ A3 A1 VDD KEY CK0 CK0# VDD A0 VDD BA1 VDDQ RAS# S0# VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS Pin 211 212 213 214 215 185 216 186 217 187 218 188 219 189 220 190 221 191 222 192 223 193 224 194 225 195 226 196 227 197 228 198 229 199 230 200 231 201 232 202 DM4/DQS13 233 203 NC/DQS13# 234 204 VSS 235 205 DQ38 236 206 DQ39 237 207 VSS 238 208 DQ44 239 209 DQ45 240 210 VSS Symbol DM5/DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 Pin Locations: Front View 64 Pin 1 Pin 240 65 184 185 120 121 Back View 240-pin DIMM DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 2 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Functional Block Diagram: Single Rank 32M x 72 (256MB), 64M x 72 (512MB), 128M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered SDRAM DIMM (x8 organization) RCS0# DQS4 DQS4# DM4/DQS13 DQS0 DQS0# DM0/DQS9 DQS9# NU/ DM/ CS# DQS# DQS RDQS# RDQS U0 DQ[0:7] 8 DQS5 DQS5# DM5/DQS14 NU/ DM/ CS# DQS# DQS RDQS# RDQS 8 DQS6 DQS6# DM6/DQS15 NU/ DM/ CS# DQS# DQS RDQS# RDQS 8 DQS7 DQS7# DM7/DQS16 NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS16# U3 DQ[24:31] 8 VDDSPD NU/ DM/ CS# DQS# DQS RDQS# RDQS To SPD To U0 - U8 To U0 - U8 To U0 - U8 VDD/VDDQ VREF Vss U8 CB[0:7] NU/ DM/ CS# DQS# DQS RDQS# RDQS U7 DQ[56:63] 8 DQS8 DQS8# DM8/DQS17 DQS17# U6 DQ[48:55] 8 DQS3 DQS3# DM3/DQS12 DQS12# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS15# U2 DQ[16:23] U5 DQ[40:47] 8 DQS2 DQS2# DM2/DQS11 DQS11# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS14# U1 DQ[8:15] U4 DQ[32:39] 8 DQS1 DQS1# DM1/DQS10 DQS10# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS13# 8 SERIAL PD SCL BA0-BA1 A0-A13 RAS# CAS# WE# CKE0 ODT0 CS0#* RESET# R E G I S T E R RST# RBA0-RBA1 -> BA0-BA1 to U0 - U8 RA0-RA13 -> A0-A13 to U0 - U8 RRAS# -> RAS# to U0 - U8 RCAS# -> CAS# to U0 - U8 RWE# -> WE# to U0 - U8 RCKE0 -> CKE0 to U0 - U8 RODT0 -> ODT0 to U0 - U8 RS0# -> CS0# to U0 - U8 CK0 CK0# RESET# A0 A1 A2 SA0 SA1 SA2 P L L SDA CK to U0 - U8 CK# to U0 - U8 CK to all registers CK# to all registers Note: 1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2; CSR# of Register 1 and DCS# of Register 2 connects to VDD 2. DQ/DM/DQS, address and control resistor values are 22 Ohms. DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 3 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Absolute Maximum Ratings: Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect reliability of the module. Symbol VDD VDDQ VDDL VIN, VOUT TSTG TOPR IIL IOL Parameter VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to VSS Voltage on any pin relative to VSS Storage temperature (Tcase) Operating Temperature (Ambient) Input Leakage Current; Any input 0V VIN 0.95V Output Leakage Current; 0V VOUT VDDQ; DQS and ODT are disabled Min Max Units -1.0 -0.5 -0.5 -0.5 -55 0 -5 -5 2.3 2.3 2.3 2.3 +100 +55 5 5 V V V V C C A A DC Operating Conditions: Parameter Supply Voltage VDDL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Symbol Min Nom Max VDD VDDL VDDQ VREF VTT 1.7 1.7 1.7 0.49 x VDDQ VREF - 40 1.8 1.8 1.8 0.50 x VDDQ VREF 1.9 1.9 1.9 0.51 x VDDQ VREF + 40 Units Notes V V V V mV 1 4 4 2 3 NOTE: 1. VDD and VDDQ must keep track of each other. VDDQ cannot exceed the value of VDD 2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF 4. VDDQ must tracks VDD; and VDDL tracks VDD Input/Output Capacitance: VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VREF = VSS, f =100MHz, 0C<TOPR <+55C, VOUT(DC) = VDDQ/2 Parameter Input Capacitance: CK, CK Delta Input Capacitance: CK, CK Input Capacitance: BA0, BA1, A0-A12, CS , RAS , CAS , WE , CKE, ODT Delta Input Capacitance: BA0, BA1, A0-A12, CS , RAS , CAS , WE , CKE, ODT Input/Output Capacitance: DQs, DQS, DM, NF Delta Input/Output Capacitance: DQs, DQS, DM, NF DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Symbol Min Max Units CCK CDCK CI 1.0 1.0 2.0 0.25 2.0 pF pF pF CDI - 0.25 pF CIO CDIO 3.0 - 4.0 0.5 pF pF Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 4 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs IDD Specifications and Conditions (256MB - 32Mx8, 9 components): Symbol Parameter DRAM IC Manufacturer* -5 DDR2-400 -3.75 DDR2-533 IDD0 Operating Current IDD1 Operating Current IDD2P Precharge Power-Down Current IDD2Q Precharge Quiet Standby Current IDD2N Precharge Standby Current IDD3P Active Power-Down Standby Current MRS(12) = 0 MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM 675 N/A 1265 765 N/A 1330 32 N/A 495 189 N/A 665 225 N/A 670 135 N/A 720 63 N/A 365 288 N/A 1065 1125 N/A 1635 990 N/A 1520 1485 N/A 1900 27 N/A 485 2070 N/A 2885 720 N/A 1420 810 N/A 1540 45 N/A 535 225 N/A 715 270 N/A 730 171 N/A 750 81 N/A 375 351 N/A 1180 1440 N/A 2115 1260 N/A 1840 1530 N/A 2005 27 N/A 555 2160 N/A 2975 Active Power-Down Standby Current MRS(12) = 1 IDD3N Active Standby Current IDD4W Operating Current Burst Write IDD4R Operating Current Burst Read IDD5B Burst Auto-Refresh Current IDD6 Self Refresh Current IDD7 Operating Current Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note: DRAM IC Manufacturer* - MT = Micron, INF = Infineon, SAM=Samsung DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 5 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs IDD Specifications and Conditions (512MB - 64Mx8, 9 components): Symbol Parameter DRAM IC Manufacturer* -5 DDR2-400 -3.75 DDR2-533 IDD0 Operating Current IDD1 Operating Current IDD2P Precharge Power-Down Current IDD2Q Precharge Quiet Standby Current IDD2N Precharge Standby Current IDD3P Active Power-Down Standby Current MRS(12) = 0 MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM MT INF SAM TBD 745 1265 TBD 790 1330 TBD 286 495 TBD 475 665 TBD 538 670 TBD 367 720 TBD 295 365 TBD 565 1065 TBD 925 1725 TBD 880 1655 TBD 1330 2125 TBD 36 490 TBD 1420 3020 TBD 918 1420 TBD 1008 1540 TBD 369 535 TBD 603 715 TBD 639 730 TBD 477 750 TBD 378 375 TBD 693 1180 TBD 1188 2340 TBD 1143 2020 TBD 1503 2275 TBD 36 560 TBD 1593 3155 Active Power-Down Standby Current MRS(12) = 1 IDD3N Active Standby Current IDD4W Operating Current Burst Write IDD4R Operating Current Burst Read IDD5B Burst Auto-Refresh Current IDD6 Self Refresh Current IDD7 Operating Current Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note: DRAM IC Manufacturer* - MT = Micron, INF = Infineon, SAM=Samsung DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 6 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Electrical Characteristics and AC Timings: VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VREF = VSS, f =100MHz, 0C<TOPR <+55C, VOUT(DC) = VDDQ/2 Symbol -5 -3.75 Units Parameter DDR2-400 DDR2-533 MIN MAX MIN MAX tAC -600 +600 -500 +500 ps DQ output access time from CK/ CK tDQSCK -500 +500 -450 +450 ps CK high-level width CK low-level width CK half period tCH tCL tHP 0.55 0.55 - tCK tCK ps tCK 8,000 8,000 0.45 0.45 MIN (tCH, tCL) 5,000 3,750 0.55 0.55 - Clock cycle time 0.45 0.45 MIN (tCH, tCL) 5,000 5,000 8,000 8,000 ps ps DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/ CK Data-out low-impedance time from CK/ CK DQS-DQ skew for DQS and associated DQ signals Data hold skew factor Data output hold time from DQS tDH tDS tIPW 400 400 0.6 - 350 350 0.6 - ps ps tCK tDIPW 0.35 - 0.35 - tCK tHZ - tACmax - tACmax ps tLZ tACmin tACmax tACmin tACmax ps - 350 - 300 ps tHPtQHS WL-0.25 450 - tHPtQHS WL-0.25 400 - ps ps DQS output access time from CK/ CK CL=3 CL=4 & 5 tDQSQ tQHS tQH Write command to 1st DQS latching transition DQS input low/high pulse width tDQSS tDQSL/H 0.35 WL+ 0.25 - DQS falling edge to CK setup time tDSS 0.2 DQS falling edge hold time from CK tDSH Mode register set command cycle time tMRD Write preamble setup time Write preamble Write postamble Read preamble Read postamble Active to Precharge command Active to Active command period Refresh to Refresh command interval Active to Read/Write delay Precharge command period tWPRES tWPRE tWPST tRPRE tRPST tRAS tRC tRFC tRCD tRP DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 0.35 WL+ 0.25 - tCK tCK - 0.2 - tCK 0.2 - 0.2 - tCK 2 - 2 - tCK 0 0.25 0.40 0.9 0.4 45 60 105 15 15 0.60 1.1 0.6 70,000 - 0 0.25 0.40 0.9 0.4 45 60 105 15 15 0.60 1.1 0.6 70,000 - ps tCK tCK tCK tCK ns ns ns ns ns Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 7 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VREF = VSS, f =100MHz, 0C<TOPR <+55C, VOUT(DC) = VDDQ/2 Symbol -5 -3.75 Units Parameter DDR2-400 DDR2-533 MIN MAX MIN MAX Active bank A to Active bank B command tRRD 7.5 7.5 ns tCCD 2 2 tCK CAS A to CAS B command period Write recovery time tWR 15 15 ns WR+tRP WR+tRP Auto Precharge write recovery + Precharge tDAL tCK time Internal Write to Read command delay tWTR 10 7.5 ns Internal Read to Precharge command delay tRTP 7.5 7.5 ns Exit precharge power down to any non-Read tXP 2 2 tCK command Exit Self-Refresh to Read command tXSRD 200 200 tCK tRFC+10 tRFC+10 Exit Self-Refresh to non-Read command tXSNR ns CKE minimum high and low pulse width tCKE 3 3 tCK Average periodic refresh interval tREFI 7.8 7.8 s OCD drive mode output delay tOIT 0 12 0 12 ns tIS+tCK tIS+tCK ns tDELAY CKE low to CK, CK uncertainty +tIH +tIH Note: These parameters are applicable for all 3 chip manufacturers, Micron, Infineon, and Samsung. DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 8 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Physical Dimensions - Layout A: Layout A: DDR2 Registered DIMM Raw Card A One physical rank, 9 components x8 organised 240 185 184 Pin 121 BACK 0.106/(2.7) Max 5.250/(133.350.15) 5.171/(131.35) Register 0.1575/(4.0) 1.181/(30.0) PLL 0.10/(2.54) Pin 1 0.118/(3.0) 0.25/(6.35) 2.55/(64.77) 64 0.039/ (1.0) 65 0.05/ (1.27) 1.95/(49.5) 5.014/(127.35) FRONT 120 0.0500.004/ (1.270.1) SIDE Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237) DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 9 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Physical Dimensions - Layout B: Layout B: 1" height DDR2 Registered DIMM Raw Card A One physical rank, 9 components x8 organised 240 185 184 Pin 121 BACK 5.250/(133.350.15) 0.106/(2.7) Max 5.171/(131.35) Register 0.1575/(4.0) 1.0/(25.4) PLL 0.10/(2.54) Pin 1 0.118/(3.0) 0.25/(6.35) 2.55/(64.77) 64 0.039/ (1.0) 65 0.05/ (1.27) 120 0.0500.004/ (1.270.1) 1.95/(49.5) 5.014/(127.35) SIDE FRONT Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237) DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 10 DDR2-400, 533 Single Rank, x8 Registered SDRAM DIMMs Product Ordering Guide: 256MB 512MB 1GB 2GB - W1D32M72R8 W1D64M72R8 W1D128M72R8 W1D256M72R8 (Preliminary*) DDR II Product Ordering Guide W 1 D 32 M 72 R 8 A - 5A E - P A 1 PCB Rev. Control Blank Initial release 1 1st Revision 2 2nd Revision Die Rev. Control A A Die B B Die DRAM IC Vendor P Samsung Q Infineon H Micron F Promos/Vitelic J Nanya Options Contact Us: Wintec Industries OEM & Industrial Solutions 4280 Technology Drive Fremont, CA 94538 Ph: 510-360-6246 Fx: 510-770-9338 Industrial T emp L Custom Labeling P Low Power R Reduced SPD Program Module Speed C o m po ne nt S pe e d Grade oemsales@wintecind.com http://www.wintecind.com/oem DDR2_RDIMM_1 rank_x8_spec Rev. 1.0 - December, 04 E Da ta R a te M o dule B a ndwidth 5A 400-333 PC2-3200 3.75A 533-444 PC2-4200 PCB Layout See Front page/Module Dimension for details Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice. 2004 Wintec Industries, Inc. 11