PHK12NQ03LT,518 - NEXPERIA

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PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Rev. 02 — 02 March 2004 Product data

M3D315

1. Product proﬁle

1.1 Description

N-channel enhancement mode ﬁeld-effect transistor in a plastic package using

TrenchMOS™ technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

2. Pinning information

3. Ordering information

■Low on-state resistance ■Fast switching.

■DC-to-DC converters ■Portable equipment applications.

■VDS ≤30 V ■ID≤11.8 A

■Ptot ≤2.5 W ■RDSon ≤14 mΩ

Table 1: Pinning - SOT96-1 (SO8), simpliﬁed outline and symbol

Pin Description Simpliﬁed outline Symbol

1,2,3 source (s)

SOT96-1 (SO8)

4 gate (g)

5,6,7,8 drain (d)

Top view MBK187

MBB076

Table 2: Ordering information

Type number Package

Name Description Version

PHK12NQ03LT SO8 Plastic small outline package; 8 leads SOT96

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 2 of 12

4. Limiting values

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage (DC) 25 °C≤Tj≤150 °C - 30 V

VGS gate-source voltage - ±20 V

IDdrain current Tamb =25°C; pulsed; tp≤10 s; Figure 2 and 3- 11.8 A

IDM peak drain current Tamb =25°C; pulsed; tp≤10 µs; Figure 3 - 35.3 A

Ptot total power dissipation Tamb =25°C; pulsed; tp≤10 s; Figure 1 - 2.5 W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −55 +150 °C

Source-drain diode

ISsource (diode forward) current Tamb =25°C; pulsed; tp≤10 s - 11.8 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

avalanche energy unclamped inductive load; ID= 7.7 A;

tp= 2.35 ms; VDD ≤30 V; VGS =10V;

starting Tj=25°C

- 440 mJ

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 3 of 12

VGS ≥5V

Fig 1. Normalized total power dissipation as a

function of ambient temperature. Fig 2. Normalized continuous drain current as a

function of ambient temperature.

Tamb =25°C; IDM is single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa11

120

0 50 100 150 200

Tamb (°C)

Pder

(%)

03aa19

120

0 50 100 150 200

Tamb (°C)

Ider

(%)

Pder Ptot

Ptot 25 C

()

----------------------- 100%×=Ider ID

ID25C

()

------------------- 100%×=

003aaa160

10-2

10-1

102

10-1 1 10 102

VDS (V)

(A)

10 s

10 ms

Limit RDSon = VDS / ID

1 ms

tp = 10 µs

100 µs

1 s

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 4 of 12

5. Thermal characteristics

5.1 Transient thermal impedance

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from junction to ambient mounted on a printed-circuit board;

minimum footprint; tp≤10 s; Figure 4 --50K/W

Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration.

003aaa161

10-1

102

10-4 10-3 10-2 10-1 1 10 102

tp (s)

Zth(j-amb)

(K/W)

single pulse

δ = 0.5

0.2

0.1

0.05

0.02

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 5 of 12

6. Characteristics

Table 5: Characteristics

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown voltage ID= 250 µA; VGS =0V 30--V

VGS(th) gate-source threshold voltage ID= 250 µA; VDS =V

GS; Tj=25°C; Figure 9 1- 2V

IDSS drain-source leakage current VDS =24V; V

GS =0V

Tj=25°C --1µA

Tj= 100 °C --5µA

IGSS gate-source leakage current VGS =±20 V; VDS = 0 V - 100 nA

RDSon drain-source on-state resistance VGS = 4.5 V; ID=10A;Figure 8 - 1114mΩ

VGS = 10 V; ID=12A;Figure 8 - 8.9 10.5 mΩ

Dynamic characteristics

gfs forward transconductance VDS =15V; I

D=10A; - 34 - S

Qg(tot) total gate charge ID= 15 A; VDD =16V; V

GS =5V;Figure 13 - 17.6 - nC

Qgs gate-source charge - 4 - nC

Qgd gate-drain (Miller) charge - 4.4 - nC

Ciss input capacitance VGS =0V; V

DS = 16 V; f = 1 MHz; Figure 11 -1335-pF

Coss output capacitance - 391 - pF

Crss reverse transfer capacitance - 190 - pF

td(on) turn-on delay time VDD =16V; R

D=10Ω; VGS = 10 V - 10.6 - ns

trrise time - 11.7 - ns

td(off) turn-off delay time - 37 - ns

tffall time -19-ns

Source-drain (reverse) diode

VSD source-drain (diode forward) voltage IS= 1 A; VGS =0V;Figure 12 - 0.7 1.0 V

trr reverse recovery time IS= 2.3 A; dIS/dt = −100 A/µs; VGS =0V - 70 - ns

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 6 of 12

Tj=25°CT

j=25°C and 150 °C; VDS >ID×RDSon

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

Tj=25°C

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values. Fig 8. Normalized drain source on-state resistance

factor as a function of junction temperature.

003aaa162

0 0.2 0.4 0.6 0.8 1

VDS (V)

(A)

VGS = 2. 2 V

5 V

2.5 V

4 V

2.8 V

003aaa163

01234

VGS (V)

(A)

VDS > ID x RDSon

Tj = 25 °C

150 °C

003aaa164

0.02

0.04

0.06

0.08

0.1

0481216

ID (A)

RDSon

(Ω)

4 V

VGS = 2. 5 V 2.8 V

5 V

03aa27

0.5

1.5

-60 0 60 120 180

Tj (°C)

aRDSon

RDSon 25°C()

------------------------------

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 7 of 12

ID= 250 µA; VDS =V

GS Tj=25°C; VDS =5V

Fig 9. Gate-source threshold voltage as a function of

junction temperature. Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

VGS = 0 V; f = 1 MHz Tj=25°C and 150 °C; VGS =0V

Fig 11. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values.

Fig 12. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical

values.

03aa33

0.5

1.5

2.5

-60 0 60 120 180

Tj (°C)

VGS(th)

(V) max

typ

min

03ai52

10-6

10-5

10-4

10-3

10-2

10-1

0123

VGS (V)

(A)

typ maxmin

003aaa165

102

103

104

10-1 1 10 102

VDS (V)

(pF)

Ciss

Coss

Crss

003aaa166

0.4 0.6 0.8 1

VSD (V)

(A)

Tj = 25 °C

150 °C

VGS = 0 V

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 8 of 12

ID= 15 A; VDD =16V

Fig 13. Gate-source voltage as a function of gate charge; typical values.

003aaa167

0 10203040

QG (nC)

VGS

(V)

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 9 of 12

7. Package outline

Fig 14. SOT96-1 (SO8).

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 10 of 12

8. Revision history

Table 6: Revision history

Rev Date CPCN Description

02 20040302 - Product data (9397 750 12955)

Modiﬁcations

•Data sheet updated to latest presentation standards.

•Section 1.4 “Quick reference data” correction to ID value.

•Section 4 “Limiting values” ID, IDM, Ptot and IS conditions and values corrected.

•Section 4 “Limiting values” Figure 1,2 and 3 corrected.

•Section 4 “Limiting values” EDS(AL)S added.

•Section 5 “Thermal characteristics” typ and max values corrected.

•Section 5 “Thermal characteristics” Figure 4 corrected.

•Section 6 “Characteristics” Figure 13 corrected.

01 20020322 - Product data (9397 750 09405)

9397 750 12955

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 11 of 12

9397 750 12955

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

Product data Rev. 02 — 02 March 2004 11 of 12

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

9. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

12. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 02 March 2004 Document order number: 9397 750 12955

Contents

Philips Semiconductors PHK12NQ03LT

N-channel TrenchMOS™ logic level FET

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

5.1 Transient thermal impedance . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

9 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 11

10 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11