WS128K32-XXX 128Kx32 SRAM MODULE FEATURES Access Times of 70, 85, 100, 120nS MIL-STD-883 Compliant Devices Available Commercial, Industrial and Military Temperature Ranges 5 Volt Power Supply Low Power CMOS Packaging * 66-pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400*), SMD Number 5962-93187 * 66-pin, PGA Type, 1.185 inch square, Hermetic Ceramic HIP (Package 401*), SMD Number 5962-93187 * 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140") (Package 502), SMD Number 5962-95595 * 68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square (Package 500). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3), SMD Number 5962-95595 TTL Compatible Inputs and Outputs Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight WS128K32-XG2X - 8 grams typical WS128K32-XHX - 13 grams typical WS128K32-XG4X - 20 grams typical All devices are upgradeable to 512Kx32 PIN CONFIGURATION FOR WS128K32N-XHX, SMD Number 5962-93187 AND WS128K32N-XH1X PIN DESCRIPTION TOP VIEW 1 12 23 WE2 I/O8 34 I/O15 45 VCC I/O24 56 I/O31 I/O9 CS2 I/O14 I/O25 CS4 I/O30 I/O10 GND I/O13 I/O26 WE4 I/O29 A13 I/O11 I/O12 A6 I/O27 A10 A14 OE A3 A7 I/O0-31 Data Inputs/Outputs A0-16 Address Inputs WE1-4 Write Enables CS1-4 Chip Selects OE Output Enable I/O28 VCC Power Supply A0 GND Ground NC Not Connected A15 A11 NC NC A4 A1 A16 A12 WE1 A8 A5 A2 BLOCK DIAGRAM WE1 CS 1 NC VCC I/O7 A9 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O4 I/O18 WE2 CS2 WE3 CS 3 WE 4CS4 OE A0-16 128K x 8 I/O3 I/O2 11 22 33 I/O19 44 I/O20 55 8 8 128K x 8 8 128K x 8 8 66 I/O0-7 August 1996 128K x 8 1 I/O8-15 I/O16-23 I/O24-31 White Microelectronics * Phoenix, AZ * (602) 437-1520 SRAM MODULES FIG. 1 4 * Call factory for PGA type (HIP) package options. Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8 WS128K32-XXX FIG. 2 PIN CONFIGURATION FOR WS128K32-XG4TX, SMD Number 5962-95595 TOP VIEW NC A0 A1 A2 A3 A4 A5 CS1 GND CS3 WE A6 A7 A8 A9 A10 VCC PIN DESCRIPTION 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 Data Inputs/Outputs A0-16 Address Inputs WE Write Enable CS 1-4 Chip Selects OE Output Enable VCC Power Supply GND Ground NC Not Connected BLOCK DIAGRAM CS3 CS 2 CS 1 CS4 WE OE A0-16 128K x 8 128K x 8 128K x 8 128K x 8 8 VCC A11 A12 A13 A14 A15 A16 CS2 OE CS4 NC NC NC NC NC NC NC 8 FIG. 3 I/O8-15 I/O0-7 8 I/O16-23 I/O24-31 PIN DESCRIPTION NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC TOP VIEW I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 8 PIN CONFIGURATION FOR WS128K32-XG2X, SMD Number 5962-95595 I/O 0-31 Data Inputs/Outputs 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 A0-16 Address Inputs WE1-4 Write Enables 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 0.940" WE1 CS 1 A16 CS1 OE CS2 NC WE2 WE3 WE4 NC NC NC A15 A14 A13 A12 Chip Selects OE Output Enable VCC Power Supply GND Ground WE2 CS2 WE3 CS 3 WE 4CS4 OE A0-16 128K x 8 8 I/O0-7 White Microelectronics * Phoenix, AZ * (602) 437-1520 CS1-4 NC Not Connected The White 68 lead G2 CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2 has the TCE and lead inspection advantage of the BLOCK DIAGRAM CQFP form. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A11 SRAM MODULES 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC 4 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O0-31 2 128K x 8 8 I/O8-15 128K x 8 8 I/O16-23 128K x 8 8 I/O24-31 WS128K32-XXX TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit TA -55 +125 C C Operating Temperature Storage Temperature TSTG -65 +150 Signal Voltage Relative to GND VG -0.5 Vcc+0.5 V Junction Temperature TJ 150 C 7.0 V Supply Voltage VCC -0.5 CS H L L L OE X L H X WE X H H L Data I/O High Z Data Out High Z Data In Power Standby Active Active Active CAPACITANCE (T A = +25C) RECOMMENDED OPERATING CONDITIONS Parameter Mode Standby Read Out Disable Write Symbol Min Max Unit Supply Voltage VCC 4.5 5.5 V OE capacitance COE VIN = 0 V, f = 1.0 MHz Input High Voltage VIH 2.2 V CC + 0.3 V CWE VIN = 0 V, f = 1.0 MHz Input Low Voltage VIL -0.5 +0.8 V WE1-4 capacitance HIP (PGA) CQFP G4 CQFP G2 Parameter Symbol Conditions Max 50 Unit pF pF 20 50 20 CS1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF DC CHARACTERISTICS (V CC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Sym Conditions -70 Min -85 Max 10 Min Max 10 Min -100 Max 10 Min -120 Max 10 Units A Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC Output Leakage Current ILO CS = V IH, OE = VIH, VOUT = GND to VCC 10 10 10 10 A Operating Supply Current ICC CS = V IL, OE = VIH , f = 5MHz, Vcc = 5.5 120 120 120 120 mA Standby Current ISB CS = V IH, OE = VIH, f = 5MHz, Vcc = 5.5 Output Low Voltage VOL IOL = 2.1mA, Vcc = 4.5 Output High Voltage VOH IOH = -1.0mA, Vcc = 4.5 5 5 2.4 2.4 mA 0.4 0.4 0.4 0.4 V 2.4 2.4 2.4 2.4 V NOTE: DC test conditions: VIH = V CC -0.3V, VIL = 0.3V DATA RETENTION CHARACTERISTICS (TA = -55C to +125C) Parameter Symbol Conditions Min Data Retention Supply Voltage V DR CS V CC -0.2V Data Retention Current I CCDR1 V CC = 3V -70 Typ 2.0 80 Max Min 5.5 2.0 1600 -85 Typ 80 3 Max Min 5.5 2.0 1600 -100 Typ 80 Max Min 5.5 2.0 1100 -120 Typ 80 Units Max 5.5 V 1100 A White Microelectronics * Phoenix, AZ * (602) 437-1520 SRAM MODULES This parameter is guaranteed by design but not tested. 4 WS128K32-XXX AC CHARACTERISTICS (V CC = 5.0V, T A = -55C To +125C) Parameter Symbol Read Cycle -70 Min Read Cycle Time t RC Address Access Time tAA Output Hold from Address Change t OH Chip Select Access Time tACS -85 Max Min 70 -100 Max Min 85 100 70 Units Max nS 100 5 5 70 Min 120 85 5 -120 Max 120 nS 120 nS 5 85 nS 100 Output Enable to Output Valid tOE Chip Select to Output in Low Z t CLZ1 5 Output Enable to Output in Low Z t OLZ 1 5 Chip Disable to Output in High Z tCHZ 1 25 25 35 35 nS Output Disable to Output in High Z t OHZ 1 25 25 35 35 nS 35 45 50 5 5 5 60 nS 5 5 nS 5 nS 1. This parameter is guaranteed by design but not tested. 4 AC CHARACTERISTICS (V CC = 5.0V, T A = -55C To +125C) SRAM MODULES Parameter Symbol Write Cycle -70 Min -85 Max Min -100 Max Min -120 Max Min Units Max Write Cycle Time t WC 70 85 100 120 nS Chip Select to End of Write t CW 60 75 80 100 nS Address Valid to End of Write t AW 60 75 80 100 nS Data Valid to End of Write tDW 30 35 40 50 nS Write Pulse Width t WP 50 55 70 80 nS Address Setup Time t AS 5 5 5 5 nS Address Hold Time t AH 5 5 5 5 nS Output Active from End of Write t OW1 5 5 5 5 Write Enable to Output in High Z t WHZ1 Data Hold Time tDH 25 25 0 nS 35 0 0 35 nS 0 nS 1. This parameter is guaranteed by design but not tested. FIG. 4 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Microelectronics * Phoenix, AZ * (602) 437-1520 4 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 nS Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . V Z is typically the midpoint of V OH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WS128K32-XXX FIG. 5 TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tRC tCHZ tACS ADDRESS tCLZ tAA OE tOE tOLZ tOH DATA I/O PREVIOUS DATA VALID DATA I/O DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1 (CS = OE = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) 4 SRAM MODULES FIG. 6 WRITE CYCLE - WE CONTROLLED tWC ADDRESS tAW tAH tCW CS tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED FIG. 7 WRITE CYCLE - CS CONTROLLED tWC WS32K32-XHX ADDRESS tAS tAW tAH tCW CS tWP WE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, CS CONTROLLED 5 White Microelectronics * Phoenix, AZ * (602) 437-1520 WS128K32-XXX PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1) 27.3 (1.075) 0.25 (0.010) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 4 4.34 (0.171) MAX SRAM MODULES 3.81 (0.150) 0.13 (0.005) 1.42 (0.056) 0.13 (0.005) 0.76 (0.030) 0.13 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H) 30.1 (1.185) 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 6.22 (0.245) MAX 3.81 (0.150) 0.1 (0.005) 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Microelectronics * Phoenix, AZ * (602) 437-1520 6 WS128K32-XXX PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2) 25.1 (0.990) 0.25 (0.010) SQ 5.1 (0.200) MAX 22.4 (0.880) 0.25 (0.010) SQ 0.25 (0.010) 0.1 (0.005) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.0 (0.946) 0.25 (0.010) 0.25 (0.010) 0.127 (0.005) 3 / -3 1.0 (0.040) 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP 4 SEE DETAIL "A" 20.3 (0.800) REF The White 68 lead G2 CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2 has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 7 White Microelectronics * Phoenix, AZ * (602) 437-1520 SRAM MODULES 0.38 (0.015) 0.05 (0.002) WS128K32-XXX PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T) 39.6 (1.56) 0.38 (0.015) SQ PIN 1 IDENTIFIER 3.56 (0.140) MAX Pin 1 12.7 (0.500) 0.5 (0.020) 4 PLACES 4 SRAM MODULES 5.1 (0.200) 0.25 (0.010) 4 PLACES 0.38 (0.015) 0.08 (0.003) 68 PLACES 1.27 (0.050) TYP 0.25 (0.010) 0.05 (0.002) 38 (1.50) TYP 4 PLACES ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Microelectronics * Phoenix, AZ * (602) 437-1520 8 WS128K32-XXX ORDERING INFORMATION W S 128K 32 X - XXX X X DEVICE GRADE: Q = MIL-STD-883 Compliant M= Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C PACKAGE TYPE: H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400*) H = 1.185" sq. Ceramic Hex-In-line Package, HIP (Package 401*) G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500) G4T = 40 mm Low Profile CQFP (Package 502) ACCESS TIME in nS IMPROVEMENT MARK: N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrades User configurable as 256Kx16 or 512Kx8 SRAM WHITE MICROELECTRONICS * Call factory for PGA type (HIP) package options. DEVICE TYPE SPEED PACKAGE SMD NO. 128K x 32 SRAM Module 120nS 66 pin HIP (H1) 128K x 32 SRAM Module 100nS 66 pin HIP (H1) 5962-93187 02H5X 128K x 32 SRAM Module 85nS 66 pin HIP (H1) 5962-93187 03H5X 128K x 32 SRAM Module 70nS 66 pin HIP (H1) 5962-93187 04H5X 128K x 32 SRAM Module 120nS 68 lead CQFP Low Profile (G4T) 5962-95595 01HYX 128K x 32 SRAM Module 100nS 68 lead CQFP Low Profile (G4T) 5962-95595 02HYX 128K x 32 SRAM Module 85nS 68 lead CQFP Low Profile (G4T) 5962-95595 03HYX 128K x 32 SRAM Module 70nS 68 lead CQFP Low Profile (G4T) 5962-95595 04HYX 128K x 32 SRAM Module 120nS 68 lead CQFP/J (G2) 5962-95595 01HMX 128K x 32 SRAM Module 100nS 68 lead CQFP/J (G2) 5962-95595 02HMX 128K x 32 SRAM Module 85nS 68 lead CQFP/J (G2) 5962-95595 03HMX 128K x 32 SRAM Module 70nS 68 lead CQFP/J (G2) 5962-95595 04HMX 9 5962-93187 01H5X White Microelectronics * Phoenix, AZ * (602) 437-1520 4 SRAM MODULES ORGANIZATION, 128Kx32