White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
1
128Kx32 SRAM MODULE
Commercial, Industrial and Military Temperature Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins for
Low Noise Operation
Weight
WS128K32-XG2X - 8 grams typical
WS128K32-XHX - 13 grams typical
WS128K32-XG4X - 20 grams typical
All devices are upgradeable to 512Kx32
* Call factory for PGA type (HIP) package options.
WS128K32-XXX
FEATURES
Access Times of 70, 85, 100, 120nS
MIL-STD-883 Compliant Devices Available
Packaging
66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400*), SMD Number 5962-93187
66-pin, PGA Type, 1.185 inch square, Hermetic
Ceramic HIP (Package 401*), SMD Number 5962-93187
68 lead, 40mm Low Profile CQFP, 3.5mm (0.140")
(Package 502), SMD Number 5962-95595
68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500). Designed to fit JEDEC 68 lead 0.990” CQFJ
footprint (Fig. 3), SMD Number 5962-95595
Organized as 128Kx32; User Configurable as 256Kx16 or
512Kx8
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-16 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
128K x 8
8
I/O
0-7
CS
1
128K x 8
8
I/O
8-15
2
128K x 8
8
I/O
16-23
3
128K x 8
8
I/O
24-31
4
A
0-16
OE
WE
CS
WE
CS
WE
CS
WE
1234
BLOCK DIAGRAM
TOP VIEW
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
11 22 33 44 55 66
1 12 23 34 45 56
FIG. 1 PIN CONFIGURATION FOR WS128K32N-XHX, SMD N umber 5962-93187
AND WS128K32N-XH1X
August 1996
2
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
WS128K32-XXX
FIG. 2 PIN CONFIGURATION FOR WS128K32-XG4TX, SMD Number 5962-95595
FIG. 3 PIN CONFIGURATION FOR WS128K32-XG2X, SMD Number 5962-95595
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
OE
CS
2
NC
WE
2
WE
3
WE
4
NC
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
TOP VIEW
I/O0-31 Data Inputs/Outputs
A0-16 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
PIN DESCRIPTION
The White 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
128K x 8
8
I/O
0-7
CS
1
128K x 8
8
I/O
8-15
2
128K x 8
8
I/O
16-23
3
128K x 8
8
I/O
24-31
4
A
0-16
OE
WE
CS
WE
CS
WE
CS
WE
1234
BLOCK DIAGRAM
TOP VIEW PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-16 Address Inputs
WE Write Enable
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
BLOCK DIAGRAM
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
NC
NC
NC
NC
NC
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
0.940"
128K x 8
8
I/O
0-7
CS
1
128K x 8
8
I/O
8-15
CS
2
128K x 8
8
I/O
16-23
CS
3
128K x 8
8
I/O
24-31
CS
4
A
0
-
16
OE
WE
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
3
WS128K32-XXX
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
V
IN
= 0 V, f = 1.0 MHz
50 pF
WE1-4 capacitance CWE
V
IN
= 0 V, f = 1.0 MHz
pF
HIP (PGA) 20
CQFP G4 50
CQFP G2 20
CS1-4 capacitance CCS
V
IN
= 0 V, f = 1.0 MHz
20 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
20 pF
Address input capacitance CAD
V
IN
= 0 V, f = 1.0 MHz
50 pF
This parameter is guaranteed by design but not tested.
Parameter Sym Conditions -70 -85 -100 -120 Units
Min Max Min Max Min Max Min Max
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 10 10 10 µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 10 10 10 µA
Operating Supply Current ICC CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 120 120 120 120 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 5 5 2.4 2.4 mA
Output Low Voltage VOL IOL = 2.1mA, Vcc = 4.5 0.4 0.4 0.4 0.4 V
Output High Voltage VOH IOH = -1.0mA, Vcc = 4.5 2.4 2.4 2.4 2.4 V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
ABSOLUTE MAXIMUM RATINGS TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Operating Temperature TA-55 +125 °C
Storage Temperature TSTG -65 +150 °C
Signal Voltage Relative to GND VG-0.5 Vcc+0.5 V
Junction Temperature TJ150 °C
Supply Voltage VCC -0.5 7.0 V
Parameter Symbol Min Max Unit
Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
DATA RETENTION CHARACTERISTICS
(TA = -55°C to +125°C)
CS OE WE Mode Data I/O Power
H X X Standby High Z Standby
L L H Read Data Out Active
L H H Out Disable High Z Active
L X L Write Data In Active
Parameter Symbol Conditions -70 -85 -100 -120 Units
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Data Retention
Supply Voltage VDR CS VCC -0.2V 2.0 5.5 2.0 5.5 2.0 5.5 2.0 5.5 V
Data Retention
Current ICCDR1 VCC = 3V 80 1600 80 1600 80 1100 80 1100 µA
4
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
WS128K32-XXX
FIG. 4
AC TEST CIRCUIT
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
1.5V
(Bipolar Supply)
Z
Current Source
OH
AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 nS
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Parameter Symbol -70 -85 -100 -120 Units
Read Cycle Min Max Min Max Min Max Min Max
Read Cycle Time tRC 70 85 100 120 nS
Address Access Time tAA 70 85 100 120 nS
Output Hold from Address Change tOH 5555nS
Chip Select Access Time tACS 70 85 100 120 nS
Output Enable to Output Valid tOE 35 45 50 60 nS
Chip Select to Output in Low Z tCLZ15555nS
Output Enable to Output in Low Z tOLZ15555nS
Chip Disable to Output in High Z tCHZ125 25 35 35 nS
Output Disable to Output in High Z tOHZ125 25 35 35 nS
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, TA = -55°C To +125°C)
AC CHARACTERISTICS
(VCC = 5.0V, TA = -55°C To +125°C)
Parameter Symbol -70 -85 -100 -120 Units
Write Cycle Min Max Min Max Min Max Min Max
Write Cycle Time tWC 70 85 100 120 nS
Chip Select to End of Write tCW 60 75 80 100 nS
Address Valid to End of Write tAW 60 75 80 100 nS
Data Valid to End of Write tDW 30 35 40 50 nS
Write Pulse Width tWP 50 55 70 80 nS
Address Setup Time tAS 5555nS
Address Hold Time tAH 5555nS
Output Active from End of Write tOW15555nS
Write Enable to Output in High Z tWHZ125 25 35 35 nS
Data Hold Time tDH 0000nS
1. This parameter is guaranteed by design but not tested.
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
5
WS128K32-XXX
WS32K32-XHX
FIG. 5
TIMING WAVEFORM - READ CYCLE
FIG. 7
WRITE CYCLE - CS CONTROLLED
FIG. 6
WRITE CYCLE - WE CONTROLLED
ADDRESS
DATA I/O
WRITE CYCLE 1, WE CONTROLLED
t
AW
t
CW
t
AH
t
WP
t
DW
t
WHZ
t
AS
t
OW
t
DH
t
WC
DATA VALID
CS
WE
ADDRESS
DATA I/O
WRITE CYCLE 2, CS CONTROLLED
t
AW
t
AS
t
CW
t
AH
t
WP
t
DH
t
DW
t
WC
CS
WE
DATA VALID
ADDRESS
DATA I/O
READ CYCLE 2 (WE = VIH)
tAA
tACS
tOE
tCLZ
tOLZ tOHZ
tRC
DATA VALID
HIGH IMPEDANCE
CS
OE
tCHZ
ADDRESS
DATA I/O
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
t
AA
t
OH
t
RC
DATA VALIDPREVIOUS DATA VALID
6
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
WS128K32-XXX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
15.24 (0.600) TYP
0.76 (0.030) ± 0.13 (0.005)
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
2.54 (0.100)
TYP
25.4 (1.0) TYP
1.42 (0.056) ± 0.13 (0.005)
1.27 (0.050) TYP DIA
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) ± 0.38 (0.015) SQ
25.4 (1.0) TYP
15.24 (0.600) TYP
0.76 (0.030) ± 0.1 (0.005)
6.22 (0.245)
MAX
3.81 (0.150)
± 0.1 (0.005)
2.54 (0.100)
TYP
25.4 (1.0) TYP
1.27 (0.050) ± 0.1 (0.005)
1.27 (0.050) TYP DIA
0.46 (0.018) ± 0.05 (0.002) DIA
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
7
WS128K32-XXX
PACKAGE 500: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2)
0.38 (0.015) ± 0.05 (0.002)
0.25 (0.010) ± 0.1 (0.005)
25.1 (0.990) ± 0.25 (0.010) SQ
1.27 (0.050) TYP
24.0 (0.946)
± 0.25 (0.010)
22.4 (0.880) ± 0.25 (0.010) SQ
20.3 (0.800) REF
5.1 (0.200) MAX
0.25 (0.010)
± 0.127 (0.005)
23.87
(0.940) REF
1.0 (0.040)
± 0.127 (0.005)
0.25 (0.010) REF
3° / -3°
R 0.25
(0.010)
DETAIL A
SEE DETAIL "A"
Pin 1
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
0.940"
TYP
The White 68 lead G2 CQFP fills
the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC.
But the G2 has the TCE and lead
inspection advantage of the
CQFP form.
8
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
WS128K32-XXX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G4T)
38 (1.50) TYP
4 PLACES
0.38 (0.015) 
± 0.08 (0.003)
68 PLACES
1.27 (0.050)
TYP
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
0.25 (0.010)
± 0.05 (0.002)
PIN 1 IDENTIFIER Pin 1
39.6 (1.56) ± 0.38 (0.015) SQ 3.56 (0.140) MAX
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
SRAM MODULES
9
DEVICE TYPE SPEED PACKAGE SMD NO.
128K x 32 SRAM Module 120nS 66 pin HIP (H1) 5962-93187 01H5X
128K x 32 SRAM Module 100nS 66 pin HIP (H1) 5962-93187 02H5X
128K x 32 SRAM Module 85nS 66 pin HIP (H1) 5962-93187 03H5X
128K x 32 SRAM Module 70nS 66 pin HIP (H1) 5962-93187 04H5X
128K x 32 SRAM Module 120nS 68 lead CQFP Low Profile (G4T) 5962-95595 01HYX
128K x 32 SRAM Module 100nS 68 lead CQFP Low Profile (G4T) 5962-95595 02HYX
128K x 32 SRAM Module 85nS 68 lead CQFP Low Profile (G4T) 5962-95595 03HYX
128K x 32 SRAM Module 70nS 68 lead CQFP Low Profile (G4T) 5962-95595 04HYX
128K x 32 SRAM Module 120nS 68 lead CQFP/J (G2) 5962-95595 01HMX
128K x 32 SRAM Module 100nS 68 lead CQFP/J (G2) 5962-95595 02HMX
128K x 32 SRAM Module 85nS 68 lead CQFP/J (G2) 5962-95595 03HMX
128K x 32 SRAM Module 70nS 68 lead CQFP/J (G2) 5962-95595 04HMX
WS128K32-XXX
ORDERING INFORMATION
W S 128K 32 X - XXX X X
DEVICE GRADE:
Q= MIL-STD-883 Compliant
M= Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C= Commercial 0°C to +70°C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex-In-line Package, HIP (Package 400*)
H = 1.185" sq. Ceramic Hex-In-line Package, HIP (Package 401*)
G2 = 22 mm Ceramic Quad Flat Pack, CQFP (Package 500)
G4T = 40 mm Low Profile CQFP (Package 502)
ACCESS TIME in nS
IMPROVEMENT MARK:
N = No Connect at pin 8, 21, 28 and 39 in HIP for Upgrades
ORGANIZATION, 128Kx32
User configurable as 256Kx16 or 512Kx8
SRAM
WHITE MICROELECTRONICS
* Call factory for PGA type (HIP) package options.