©
1995
DATA SHEET
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD16435 and 16435A are controllers/drivers for a 119 × 73-dot LCD, and perform LCD full-dot and character
composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type
DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive.
The
µ
PD16435 uses an external reference clock. The
µ
PD16435A has the on-chip oscillation circuit (external
crystal resonator).
FEATURES
• Can interface to 4 or 8-bit CPU.
• Incorporates 119 segment outputs and 73 common outputs.
(Display duty selectable from 1/35, 1/37, 1/71, 1/73)
•5 × 7 character font 208 character data configuration character generation ROM and 16 character data configuration
character generation RAM, allowing composite full-dot and character display
• Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc.
• Operating voltage: 2.7 V to 5.5 V
• On-chip DC/DC converter: Selectable between ×4 set-up circuit and ×2 step-up circuit
• On-chip temperature correction circuit
• Master/slave operation capability
• On-chip power-on reset circuit
• On-chip oscillation circuit (
µ
PD16435A)
• 232-pin TCP (Tape Carried Package)
ORDERING INFORMATION
Part Number Package
µ
PD16435N-001-××× TCP (TAB), Standard ROM code
µ
PD16435N-001-001 Standard quad TCP (Conforms to EIAJ), Standard ROM code
µ
PD16435N-001-002 Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code
µ
PD16435AN-001-××× TCP (TAB), Standard ROM code
µ
PD16435AN-001-001 Standard quad TCP (Conforms to EIAJ), Standard ROM code
µ
PD16435AN-001-052 Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code
Explanation of Part Number
µ
PD16435 (A) N-xxx-xxx TCP code
ROM code
The TCP model is a custom model. For details, consult NEC sales representative.
Document No. S10298EJ3V0DS00 (3rd edition)
Date Published April 1997 N
Printed in Japan
DOT MATRIX LCD CONTROLLER/DRIVER
µ
PD16435, 16435A
µ
PD16435, 16435A
2
BLOCK DIAGRAM
COM73
73
119
119
7
8
8
8
8
TEST1
TEST2
WS
CS
RS
RD
WR
BUSY
RESET
SYNC
SCR
GND1
GND2
V
CC
V
DD
3/5
C
1
+
C
1
–
C
2
+
C
2
–
C
3
+
C
3
–
D
0~7
V
5
V
4
V
3
V
2
V
1
V
IN
V
IN
8
8
5
5
OSC1
OSC3
COM1
SEG1
OSC
SEG119
OSC2
Common Driver 
Segment Driver
Scaler 
Timing Generator 
73-Bit Shift Register 119-Bit Latch
Selector
Cursor Blinking 
Control Register
Display RAM
119 × 73 Bits
Scroll RAM
13 × 73 Bits
CGROM
5 × 7 × 208 Bits
CGRAM
5 × 7 × 16 Bits
Address 
Counter
Instruction Register Data Register Busy Flag
OP-Amp
Parallel I/F  ×2/×4 Step-Up Circuit
–
+
Instruction Decoder
µ
PD16435, 16435A
3
PIN CONFIGURATION (CHIP)
Dummy22
Dummy21
COM1
COM2
215
214
Dummy26
VDD
GND1
CS
RS
RD
WR
WS
D0
D1
D2
D3
D4
D5
D6
D7
RESET
SCR
BUSY
SYNC
TEST1
TEST2
3/5
OSC1
OSC2
OSC3
VCC
Dummy25
C1–
C1+
C2–
C2+
C3–
C3+
VIN(
–
)
VIN(+)
GND2
V1
V2
V3
V4
V5
Dummy24
Dummy23
SEG85
Dummy16
Dummy17
SEG119
COM37
Dummy20
Dummy1
Dummy2
COM38
COM39
258
1
Dummy13
SEG30
Dummy5
Dummy14
SEG31
SEG32
SEG83
SEG84
Dummy15
COM73
Dummy3
Dummy4
SEG1
13580
79 136
µ
PD16435, 16435A
4
PIN DESCRIPTIONS
Description
Chip select signal
Register selection signal (specifies address register when “0”,
control register when “1”).
Read enable signal. Reads write address when scrolling.
Active edge is falling edge.
Write enable signal.
Active edge is falling edge.
Word length selection signal (4-bit input when “1”, 8-bit input
when “0”).
Transmit/receive data (3-state bidirectional)
Upper → D4 to D7
Lower → D0 to D3 (These pins should be set as unused in case
of 4-bit data).
In test mode, these pins are output pins.
In a 4-bit transfer, storage is performed in the upper (MSB) in
order from the data transferred first.
“0” indicates busy state.
“0” → Initialization of all internal registers and commands is
performed. Output is fixed at V1.
Signal is output to CPU on completion of one-character scroll.
Synchronization signal input/output pins for master/slave
operation.
µ
PD16435: Input the 4.19 MHz reference clock to the OSC1 pin
externally. Leave the OSC2 pin open. (Always outputs high
level.)
µ
PD16435A: This is the pin to which the 4.19 MHz crystal
resonator is connected. Input the external clock to OSC1 first.
2 Hz external clock input pin. Scaled by 2 internally to generate 1
Hz, used as blink synchronization signal.
Common output signals
Segment output signals
“1” → Test mode
“0” or open → Normal operating mode
Output Type
–––
–––
–––
–––
–––
CMOS 3-state
Nch open-drain
–––
CMOS
Nch open-drain
–––
–––
Analog switch
Analog switch
–––
Input/Output
Input
Input
Input (Schmitt)
Input (Schmitt)
Input
Input/output
Output
Input
Output
Input/output
–––
Input (Schmitt)
Output
Output
Output
Pin Name Pin No.
CS 255
RS 254
RD 253
WR 252
WS 251
250
D0 to D7to
243
BUSY 240
RESET 242
SCR 241
SYNC 239
OSC1235
OSC2234
OSC3233
COM1 to
212 to 176
COM73 3 to 38
SEG1 to 41 to 70
SEG119
81 to 134
137 to 171
TEST1 238
TEST2 237
µ
PD16435, 16435A
5
Pin Name Pin No.
V1 221
220
V2 to V5 to
217
VIN(–) 224
VIN(+) 223
VCC, GND1 232, 256
VDD, GND2 257, 222
3/5 236
C1±, C2±, 230 to
C3±225
Description
LCD drive power supply pin
Internal OP-amp output
LCD drive power supply pins
Can be adjusted by addition of external resistor.
Liquid crystal drive power supply OP-amp input pins
Logic power supply, GND
Liquid crystal drive (step-up) power supply, GND
Drive voltage selection pin
“1” → VDD = 3 V (×4 step-up circuit selected)
“0” → VDD = 5 V (×2 step-up circuit selected)
A 1
µ
F tantalum or ceramic capacitor should be connected
externally.
Input/Output
Output
Input
Input
–––
–––
Input
–––
Output Type
–––
–––
–––
–––
–––
–––
–––
REFERENCE CLOCK
Product Name Reference Clock
µ
PD16435 External input
µ
PD16435A On-chip oscillation circuit (External crystal resonator)
OSC CIRCUIT (
µ
PD16435A)
OSC
2
OSC
1
4.19 MHz
µ
PD16435, 16435A
6
Register address list
Address Register Name
b3 b2 b1 b0
0 0 0 0 Full-dot X address register
0 0 0 1 Full-dot Y address register
0 0 1 0 Full-dot data register
0 0 1 1 Character X address register
0 1 0 0 Character Y address register
0 1 0 1 Character data register
0 1 1 0 CGRAM address register
0 1 1 1 CGRAM data register
1 0 0 0 Extension register
1 0 0 1 Extension register X address register
1 0 1 0 Extension register Y address register
1 0 1 1 Scroll register
1 1 0 0 Control register
REGISTER FUNCTIONS
(1) Address Register
Sets the address of each register, and also sets display control, standby mode, and scaler resetting.
MSB LSB
After powering on
× : Don’t Care
b7 b6 b4 b3 b2 b1 b0b5
Register address (0H to CH)
See table below
Display control
00: Display control off (SEG
n
, COM
n
= V
1
)
01: Display control off (SEG
n
, COM
n
= unselected waveform)
10: Normal operation
11: Normal operation
Standby mode setting
0: Normal operation
1: Standby mode
Blink internal scaler reset and 1/2 scaler reset
0: Normal operation
1: Reset (Blinking starts when it lights.)
(Used to synchronize time variations and time mark blinking.)
Note Standby mode = DC/DC converter stopped 
OSC
1
input invalid ( PD16435)
OSC stopped ( PD16435A)
SEG
n
, COM
n
= V
1
Data write/read prohibited
0 0 0 0 0 0 00
Note
µ µ
µ
PD16435, 16435A
7
(2) Full-Dot X Address Register (Register Address = 0000B)
Performs full-dot display, display screen X (segment) direction address setting. As scrolling is not possible with a full-
dot display, addresses are not allocated to the scroll RAM area.
After powering on: Undefined
(3) Full-Dot Y Address Register (Register Address = 0001B)
Performs full-dot display, display screen Y (common) direction address setting.
After powering on: Undefined
(4) Full-Dot Data Register (Register Address = 0010B)
Inputs full-dot display data. Display data is stored in the display memory with the MSB on the left, and display data “1”
corresponds to illumination.
After powering on: Undefined
MSB LSB
× : Don’t Care
b3 b2 b1 b0
Full-dot X address (00H to 0EH)
MSB LSB
× : Don’t Care
b6 b4 b3 b2 b1 b0b5
Full-dot Y address (00H to 48H)
MSB LSB
b7 b6 b4 b3 b2 b1 b0b5
× : Don’t Care
MSB LSB
b7 b6 b4 b3 b2 b1b5
Full-dot X address = 00H to 0DH
Full-dot X address = 0EH
Full-dot display data
Full-dot display data
µ
PD16435, 16435A
8
Full-Dot X Address and Y Address Allocation
(5) Character X Address Register (Register Address = 0011B)
Performs character display display, screen X (segment) direction address setting. X addresses include the scroll RAM
area.
After powering on: Undefined
(6) Character Y Address Register (Register Address = 0100B)
Performs character display display, screen Y (common) direction address setting.
After powering on: Undefined
00H(1)
00H(1)
01H(2) 0EH(15)
48H(73)
01H(2)
X Address
Y Address
b7 b6 b5 b4 b3 b2 b1b7 b6 b5 b4 b3 b2 b1 b0
8 Bits 7 Bits
MSB LSB
× : Don’t Care
b4 b3 b2 b1 b0
Character X address (00H to 15H)
MSB LSB
× : Don’t Care
b2 b1 b0
Character Y address (00H to 07H)
µ
PD16435, 16435A
9
(7) Character Data Register (Register Address = 0101B)
The character indicated in the character code table is displayed at the position indicated by the character X and Y address
registers.
After powering on: Undefined
Character X Address and Y Address Allocation
MSB LSB
b7 b6 b4 b3 b2 b1 b0b5
Character code
× : Don’t Care
X Address
Y Address
00H(1)
00H(1)
13H(20)01H(2) 14H
(21) 15H
(22)
07H(8)
01H(2)
8 Bits
1 Bit
5 Bits
1 Bit
Scroll 
RAM Area
Display RAM Area
µ
PD16435, 16435A
10
(8) CGRAM Address Register (Register Address = 0110B)
Performs address setting when display data is written to CGRAM. Bits b6 to b3 of the CGRAM address indicate the
character code, and bits b2 to b0 indicate the character line.
Note If auto increment is set with the control register, 06H is followed by 07H. Dummy data should be sent when the address
is 07H.
Example: (CGRAM address with auto increment)
--- → 15H → 16H → 17H → 18H → ---
After powering on: Underfined
(9) CGRAM Data Register (Register Address = 0111B)
CGRAM display data. The lower 5 bits of the write data are valid.
After powering on: Undefined
MSB LSB
× : Don’t Care
b6 b4 b3 b2 b1 b0b5
Line address (00H to 06H)
Character code (00H to 0FH)
Note
MSB LSB
× : Don’t Care
b4 b3 b2 b1 b0
CGRAM data
µ
PD16435, 16435A
11
(10) Extension Register (Register Address = 1000B)
Performs magnification, reverse, cursor, and time mark setting.
MSB LSB
× : Don’t Care
b3 b2 b1 b0
In case of magnification setting
00: Standard
01: ×2 horizontal
10: ×2 vertical
11: ×4 magnification (×2 horizontal & vertical)
Magnification display is performed at any line position; characters of different
sizes cannot be displayed on the same line.
Line specification magnification display is possible by setting an extension Y
address after this command, and multiple-line magnification display is possible
by setting consecutive extension Y address.
After powering on
0 0 00
Extension function setting
00: Magnification setting
01: Reverse setting
10: Cursor setting
11: Character blink setting
In case of reverse setting
00: Reverse cancellation (line specification)
01: Reverse (line specification)
10: Reverse cancellation (full screen)
11: Reverse (full screen)
Line specification reverse display is possible by setting an extension Y address 
after this command, and multiple-line reverse display is possible by setting 
consecutive extension Y addresses.
Regarding the reverse display Y address direction, a total of 9 dots (7 character
part dots + 1 cursor part dot + 1 top space dot) are reversed.
In the case of ×2 vertical magnification or ×4 magnification, a total of 18 dots
(14 character part dots + 2 cursor part dots + 2 top space dots) are reversed.
In case of cursor setting
00: Cursor non-display
01: Cursor display (blinking stopped)
10: Cursor display (blink operation)
11: Don’t Care
Blinking display can be performed at any address by specifying an extension X
and Y address after this command. The specification is for one address only. 
The address specification should be performed in the order: X address → Y address.
In case of character blink setting
X0: Blinking stopped
X1: Blink operation
Blinking can be performed at any address by specifying an extension X and Y 
address after this command. The specification is for one address only.
The address specification should be performed in the order: X address → Y address.
µ
PD16435, 16435A
12
Display and RAM Allocation in Case of Magnification Setting
(1) Example of ×2 horizontal magnification (line 07H specified)
Note Lines 0AH to 15H for which ×2 horizontal magnification is specified can be used as scroll RAM.
00H(1)
00H(1)
13H(20)
01H(2)
07H(8)
01H(2)
(X=00H) (X=09H) 8 Bits
1 Bit
10 Bits
2 Bits 1 Bit
Display
RAM
00H(1)
00H(1)
13H(20) 14H(21) 15H(22)
01H(2)
07H(8)
00H 01H 09H 0AH 15H
01H(2)
Display Area  Non-Display Area
µ
PD16435, 16435A
13
(2) Example of ×2 vertical magnification (line 00H specified)
Note If ×2 vertical magnification is specified for line 07H, the lower half will be outside the display area.
Also, if ×2 vertical magnification is specified for line 06H, the bottom dot will be a space.
00H(1)
00H(1)
13H(20)
01H(2)
06H(7)
01H(2)
16 Bits
2 Bits
1 Bit
5 Bits
Display
RAM
00H(1)
00H(1)
13H(20) 14H(21) 15H(22)
01H(2)
07H(8)
06H(7)
01H(2)
Display Area  Non-Display Area
µ
PD16435, 16435A
14
(3) Example of ×4 magnification (line 00H specified)
Note Lines 0AH to 15H for which ×4 magnification is specified can be used as scroll RAM.
If ×4 magnification is specified for line 07H, the lower half will be outside the display area, and if ×4 magnification
is specified for line 06H, the bottom dot will be a space.
00H(1)
00H(1)
09H(10)
00H 01H 13H
06H(7)
01H(2)
16 Bits
2 Bits
1 Bit
1 Bit
2 Bits
10 Bits
Display
RAM 00H(1)
00H(1)
09H(10)
0AH(11) 14H(21) 15H(22)
01H(2)
07H(8)
00H 01H 13H 14H 15H
06H(7)
01H(2)
Display Area  Non-Display Area
µ
PD16435, 16435A
15
(11) Extension X Address Register (Register Address = 1001B)
Performs extension display, display screen X (segment) direction address setting. X addresses include the scroll RAM
area. This register must be executed before the extension Y address register.
After powering on: Undefined
(12) Extension Y Address Register (Register Address = 1010B)
Performs extension display, display screen Y (common) direction address setting. This register must be executed after
the X address.
After powering on: Undefined
(13) Scroll Register (Register Address = 1011B)
Performs scroll setting.
MSB LSB
× : Don’t Care
b4 b3 b2 b1 b0
Character X address (00H to 15H)
MSB LSB
× : Don’t Care
b2 b1 b0
Character Y address (00H to 07H)
MSB LSB
After powering on
× : Don’t Care
b7 b6 b4 b3 b2 b1 b0b5
Scroll direction setting
00: Scroll reset
01: Right scroll
10: Left scroll
11: Scrolling stopped
Scrolling by specification of any line is possible by setting 
a character Y address after this command. Scrolling can only 
be performed for one character-unit line.
Scroll speed setting (00H to 3FH)
This value specifies the number of frames for a one-bit move. 
If 00H is set, scrolling is stopped.
0 0 0 0 0 0 00
Note 1
Note 2
Notes 1. When scroll reset is executed, the screen leftmost character X address returns to 00H, and scrolling is stopped.
2. After scrolling has been stopped, character Y address setting is necessary when scrolling is restarted. It is not
possible to set a different address from the character Y address before scrolling was stopped.
µ
PD16435, 16435A
16
(14) Control Register (Register Address = 1100B)
Performs address increment direction, common output, frame frequency, blinking, and master/slave setting.
Note CGRAM is incremented in the Y direction even if 00H is set.
MSB LSB
After powering on
× : Don’t Care
b7 b6 b4 b3 b2 b1 b0b5
Address increment direction setting
00: Auto increment in X direction (up-count)
01: Auto increment in Y direction (up-count)
1×: Address retention
When auto increment is used, the address is automatically 
up-counted after a full-dot, character, or CGRAM data write. 
The character X address is reset to 13H.
When address retention is specified, the address is retained 
after a data write.
Frame frequency setting
00: 100 Hz
01: 75 Hz
10: 50 Hz
11: Don’t Care
LCD drive is performed by frame inversion.
Blink source setting
0: External clock (OSC3)
1: Internal scaled block
Master/slave setting
0: Master
1: Slave
Common output setting
00: 35 outputs (1/35 duty, COM
2
to COM
36
selected)
01: 37 outputs (1/37 duty, COM
1
to COM
37
selected)
10: 71 outputs (1/71 duty, COM
2
to COM
72
selected)
11: 73 outputs (1/73 duty, COM
1
to COM
73
selected)
0 0 0 0 0 0 00
Note
17
µ
PD16435, 16435A
Standard ROM Code (001)
0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
CC
RAM
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
xxxx0000
xxxx0001
xxxx0010
xxxx0011
xxxx0100
xxxx0101
xxxx0110
xxxx0111
xxxx1000
xxxx1001
xxxx1010
xxxx1011
xxxx1100
xxxx1101
xxxx1110
xxxx1111
Higher Bit
4 Bits
Lower
Bit 4 Bits
18
µ
PD16435, 16435A
ABSOLUTE MAXIMUM RATINGS (TA = 25 ˚C, GND1 = GND2 = 0 V)
Parameter Symbol Rating Unit
Supply voltage 1 (3/5 = L) VCC1 –0.3 to +7.0 V
Supply voltage 2 (3/5 = H) VCC2 –0.3 to +4.0 V
Logic input voltage VIN –0.3 to VCC+0.3 V
Logic output voltage VOUT1 –0.3 to VCC+0.3 V
LCD drive power supply voltage VDD VCC–0.3 to +16.0 V
LCD drive power supply input voltage V2 to V5–0.3 to VDD+0.3 V
LCD drive power supply output voltage V1–0.3 to VDD+0.3 V
Amplifier input voltage VIN (+), VIN (–) –0.3 to VDD+0.3 V
Driver output voltage (Segment, common) VOUT2 –0.3 to VDD+0.3 V
Storage temperature range Tstg. –55 to +150 ˚C
Parameter Symbol MIN. TYP. MAX. Unit
Supply voltage 1 (3/5 = L) VCC1 4.5 5.0 5.5 V
Supply voltage 2 (3/5 = H) VCC2 2.7 3.0 3.6 V
LCD drive supply voltage VDD VCC 8.0 14.5 V
Logic input voltage VIN 0VCC V
LCD drive power supply input voltage V2 to V50VDD V
LCD drive power supply output voltage V10VDD V
External capacitance C0 to C31 4.7
µ
F
Operating temperature range TA–40 +85 ˚C
RECOMMENDED OPERATING RANGES
19
µ
PD16435, 16435A
Symbol
VIH1
VIL1
VIH2
VIL2
VH
IIH1
IIH1
IIH2
IIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
ILOH
ILOL
RCOM
RSEG
VDD1
VDD2
MIN. TYP. MAX. Unit
0.7VCC V
0.3VCC V
0.8VCC V
0.2VCC V
0.05VCC 0.2VCC V
1
µ
A
–1
µ
A
6mA
–100
µ
A
0.9VCC V
0.1VCC V
0.9VCC V
0.1VCC V
0.9VCC V
0.1VDD V
10
µ
A
–10
µ
A
5kΩ
10 kΩ
1.9VCC 2.0VCC V
3.6VCC 4.0VCC V
ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, Vcc =
5 V ±10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H)
Test Conditions
Except Schmitt inputs
Except Schmitt inputs
Schmitt inputs
Schmitt inputs
Schmitt inputs
CS, RS, RD, WR, WS, RESET, 3/5,
OSC3, VIN(+), VIN(–), VIN = VCC
CS, RS, RD, WR, WS, RESET, 3/5,
OSC3, VIN(+), VIN(–), VIN = 0 V
TEST1, TEST2, VIN = VCC
TEST1, TEST2, VIN = 0 V
Dn, SCR, 3/5 = L
IOH = –1 mA
Dn, BUSY, SCR, SYNC, 3/5 = L
IOL = 4 mA
Dn, SCK, 3/5 = H
IOH = –0.6 mA
Dn, BUSY, SCR, SYNC, 3/5 = H
IOL = 2.4 mA
V1 pin
IOH = –1 mA
VIN(+) = VDD, VIN(–) = 0 V
V1 pin
IOL = –10
µ
A
VIN(+) = 0 V, VIN(–) = VDD
Dn, SYNC, BUSY
VIN/OUT = VCC
Dn, SYNC, BUSY
VIN/OUT = 0 V
COM1 to COM73
|IO| = 100
µ
A
SEG1 to SEG119
|IO| = 100
µ
A
RB = 10 kΩ
3/5 = L
RB = 10 kΩ
3/5 = H
Parameter
Input voltage high
Input voltage low
Input voltage high
Input voltage low
Hysteresis voltage
Input current high
Input current low
Input current high
Input current low
Output voltage high
Output voltage low
Output voltage high
Output voltage low
Output voltage high
Output voltage low
Leak current high
Leak current low
Common output
on-resistance
Segment output
on-resistance
Driver unit supply voltage
(step-up voltage)
Driver unit supply voltage
(step-up voltage)
20
µ
PD16435, 16435A
ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, Vcc =
5 V ±10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H)
Symbol MIN. TYP. MAX. UnitTest Conditions
Logic consumption current
(
µ
PD16435)
Logic consumption current
(
µ
PD16435A)
ICC1
ICC2
ICC3
ICC4
ICC1
ICC2
ICC3
ICC4
0.35 1 mA
0.35 1 mA
1.3 2.5 mA
0.75 1.5 mA
0.6 1.5 mA
0.65 1.5 mA
1.5 3 mA
1.05 2 mA
Parameter
VCC = 3.0 V, no load, 3/5=H
fOSC = 4.19 MHz
VCC = 5.0 V, no load, 3/5=L
fOSC = 4.19 MHz
VCC = 3.0 V, 3/5=H
RB = 10 kΩNote
fOSC = 4.19 MHz
VCC = 5.0 V, 3/5=L
RB = 10 kΩNote
fOSC = 4.19 MHz
VCC = 3.0 V, no load, 3/5=H
fOSC = 4.19 MHz
VCC = 5.0 V, no load, 3/5=L
fOSC = 4.19 MHz
VCC = 3.0 V, 3/5=H
RB = 10 kΩNote
fOSC = 4.19 MHz
VCC = 5.0 V, 3/5=L
RB = 10 kΩNote
fOSC = 4.19 MHz
Note TYP. values are reference values for TA = 25 ˚C.
21
µ
PD16435, 16435A
NOTE MEASUREMENT CIRCUIT
MIN. TYP. MAX. Unit
150 ns
10 ns
3 9 CLKNote
48 54 CLKNote
100 550
µ
s
SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, Vcc =
5 V ±10%, RL = 5 kΩ, CL = 150 pF)
Test Conditions
RD↓ → Dn
RD↑ → Dn
When full-dot data is written
When charactor data is written
Symbol
tRDD
tRDH
tBL
tBL
tSCR
Note CLK = 4/fOSC
Parameter
RD data delay time
RD data hold time
BUSY low-level time
BUSY low-level time
SCR high-level time
R
B
V
1
V
CC
V
2
V
3
V
4
V
5
R
B
R
B
R
B
R
B
+
–
V
IN
-
V
IN
+
22
µ
PD16435, 16435A
Symbol
fOSC
tWHC
tWLC
tRDH
tRDL
tWRH
tWRL
tWRRD
tRDWR
tCRS
tCRH
tDS
tDH
MIN. TYP. MAX. Unit
3.77 4.19 4.61 MHz
100 ns
100 ns
200 ns
200 ns
200 ns
200 ns
200 ns
200 ns
0ns
300 ns
0ns
200 ns
Test Conditions
µ
PD16435 only
µ
PD16435 only
µ
PD16435 only
WR↑ → RD↓
RD↑ → WR↓
CS↓, RS → WR↓, RD↓
WR↑, RD↑ → CS↑, RS
Dn → WR↑
WR↑ → Dn
REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, VCC =
5 V ±10%, RL = 5 kΩ, CL = 150 pF)
Parameter
Clock frequency
High-level clock pulse width
Low-level clock pulse width
RD high-level width
RD low-level width
WR high-level width
WR low-level width
WR – RD time
RD – WR time
CS, RS setup time
CS, RS hold time
Input data setup time
Input data hold time
SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, Vcc = 2.7
to 3.6 V, RL = 5 kΩ, CL = 150 pF)
MIN. TYP. MAX. Unit
500 ns
15 ns
3 9 CLKNote
48 54 CLKNote
100 550
µ
s
Test Conditions
RD↓ → Dn
RD↑ → Dn
When full-dot data is written
When charactor data is written
Symbol
tRDD
tRDH
tBL
tBL
tSCR
Parameter
RD data delay time
RD data hold time
BUSY low-level time
BUSY low-level time
SCR high-level time
Note CLK = 4/fOSC
23
µ
PD16435, 16435A
REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = –40 to +85 ˚C, C0 to C3 = 1
µ
F, VCC = 2.7
to 3.6 V, RL = 5 kΩ, CL = 150 pF)
Parameter
Clock frequency
High-level clock pulse width
Low-level clock pulse width
RD high-level width
RD low-level width
WR high-level width
WR low-level width
WR – RD time
RD – WR time
CS, RS setup time
CS, RS hold time
Input data setup time
Input data hold time
Symbol
fOSC
tWHC
tWLC
tRDH
tRDL
tWRH
tWRL
tWRRD
tRDWR
tCRS
tCRH
tDS
tDH
MIN. TYP. MAX. Unit
3.77 4.19 4.61 MHz
100 ns
100 ns
400 ns
400 ns
400 ns
400 ns
400 ns
400 ns
0ns
600 ns
0ns
400 ns
Test Conditions
µ
PD16435 only
µ
PD16435 only
µ
PD16435 only
WR↑ → RD↓
RD↑ → WR↓
CS↓, RS → WR↓, RD↓
WR↑, RD↑ → CS↑, RS
Dn → WR↑
WR↑ → Dn
24
µ
PD16435, 16435A
AC TIMING TEST VOLTAGE
AC CHARACTERISTICS WAVEFORM
OSC
READ TIMING
WRITE TIMING
V
IH
V
IL
V
OH
V
OL
Input
Output
t
WHC
t
WLC
I/f
OSC
OSC1
t
CRS
t
RDL
t
RDH
t
RDWR
t
CRH
t
RDH
t
RDD
CS, RS
RD
WR
D
n
t
CRS
t
WRL
t
WRH
t
WRRD
t
CRH
t
DH
t
DS
CS, RS
WR
RD
D
n
25
µ
PD16435, 16435A
BUSY
SCR
t
BL
BUSY
t
SCR
SCR
26
µ
PD16435, 16435A
EXAMPLE TEMPERATURE CORRECTION CIRCUIT CONNECTION
V
2
V
3
V
4
V
5
V
1
V
IN
-
V
IN
+
V
CC
R
1
R
t
R
p
+
-
R
B
R
B
R
B
R
B
R
B
R
t
: Thermistor
27
µ
PD16435, 16435A
STANDARD TCP PACKAGE DRAWINGS (
µ
PD16435N-001-001,
µ
PD16435AN-001-001)
8.33
137
171
134
7.50
81
70
41
3
257232217
212
0.15
(0.30)
P0.28 ± 0.01X57 = 15.96 ± 0.025 W0.12 ± 0.02
P0.40 ± 0.01X60 = 24.00 ± 0.04
11.50
12.70 12.70
13.475
16.30 13.475
11.50
4.75 ± 0.03
0.3 ± 0.3
W0.12 ± 0.02
11.5011.50
12.70
13.475
0.142 ± 0.03
12.70
13.475
31.82+0.04
-
0.07
P0.28 ± 0.01X57 = 15.96 ± 0.025
P0.40 ± 0.01X60 = 24.00 ± 0.04
1.00
2.252.251.42 ± 0.03
2.25 2.2518.00
6.00
4.00 9.50 11.00
13.475 13.475
30°
1.00
Cu
φ1.00
18.00 13.47513.475
14.50
3.50
11.50
P0.40
12.70
13.475
90°
12.70
13.475
P0.40
11.50
0.50
0.65
0.40±0.015
0.60±0.015
Detail of Test Pad and Alignment Mark
From Pattern Center
From Pattern Center
12.1+0
-
4.6
COATING AREA
12.93+0
-
4.6
COATING AREA
MAX. 0.9
28
µ
PD16435, 16435A
DUMMY
SEG31
D
U
M
M
Y
SEG30
SEG29 SEG28
DUMMY
SEG27
COM50
COM51
COM48
COM49
DUMMY
COM47
D
U
M
M
Y
S
E
G
3
3
S
E
G
3
2
S
E
G
3
4
S
E
G
8
6
S
E
G
8
4
S
E
G
8
8
D
U
M
M
Y
S
E
G
8
5
C
O
M
4
6
C
O
M
3
8
G
N
D
0
1
D
U
M
M
Y
V
D
D
C
S
D
U
M
M
Y
V
0
3
V
0
5
D
U
M
M
Y
V
0
4
C
O
M
0
1
C
O
M
0
9
S
E
G
8
7
S
E
G
8
9
S
E
G
3
6
S
E
G
3
5
DUMMY
SEG91
SEG93
DUMMY
COM13
COM11
DUMMY COM10
COM12
COM14
SEG94
SEG92
SEG90
29
µ
PD16435, 16435A
STANDARD TCP PACKAGE DRAWINGS (
µ
PD16435N-001-002)
8.33
137
171
134
7.50
81
70
41
3
257232217
212
MATERIAL
Detail of Alignment Mark
Base Hole
3.50 17.50
14.7 ± 0.3
10.00
P0.10
P0.1044
10.00
14.7 ± 0.3
(30.00)
12.1+0
-
4.6
COATING AREA
P0.70 ± 0.01X41 = 28.70 ± 0.045 W0.35 ± 0.02
31.00
19.00
BASE FILM
ADHESIVE
COPPER FOIL
PLATING
SOLDER RESIST
: UPILEX-S
: EPOXY
: ELECTROLYSIS Cu
: Sn
: EPOXY
t=75 m
t=12 m
t=18 m
t=MIN 0.25 m
t=25 m
This Figure is shown by Copper side over Polyimide
All tolerances unless otherwise specified 0.05 mm.
Coner radius is 0.3 mm Max.
II Sprocket holes (52.25 mm) for 1 Pattern
2-φ1.30
2-R1.15 ± 0.3
SR
2-φ1.10
Cu
2-φ1.90
Cu
WINDING WAY OUTPUT LEADS
UNWINDING
DIRECTION
FACE(COPPER)
3.00
(1.50)
0.95
2.00
6.00 4.65
31.82+0.04
-
0.07
9.00 5.05 ± 0.3 (4.20)
(12.50) (9.25)
13.00 11.10 ■1.42 ± 0.03
10.90
(0.70)
P0.1003
1.175 ± 0.01
24.8 ± 0.324.8 ± 0.3
1.175 ± 0.01
MAX 0.9
25.5525.55 (50.25)
P0.25 ± 0.01X195 = 48.75 ± 0.075 W0.125 ± 0.015
4.60 P0.10X654.60P0.10X71
P0.0964P0.1013
■4.75 ± 0.03
P0.1
P0.10
10.004.00
8.465 +0
-
2.3 4.465 +0
-
2.3
COATING AREA
4.75 10.90
7.00
0.3 ± 0.3
0.70
(3.80)
6.00 2.50 (0.70)
f1.00
1.00
P0.1005
Cu
m
m
m
m
m
P0.1060
30
µ
PD16435, 16435A
from P.C. 25.55
P0.25
0.40
0.30
1.175 ± 0.01
0.60 ± 0.015
0.40 ± 0.015
0.125
1.50
0.50
0.200.10
0.50
0.10
(1.20)
0.10
(1.40) 1.40
10.90 from P.C.
11.10 from P.C.
Detail of Test Pad
and Alignment Mark
DUMMY
V
DD
GND1
CS
RS
RD
WR
WS
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
RESET
SCR
BUSY
SYNC
TEST1
TEST2
3/5
OSC
1
OSC
2
OSC
3
V
CC
C1
-
C1+
C2
-
C2+
C3
-
C3+
V
IN
(
-
)
V
IN
(+)
GND2
V1
V2
V3
V4
V5
DUMMY
NC
NC
COM38
COM39
COM40
COM41
COM42
•
•
•
•
COM73
SEG1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG119
COM37
•
•
•
•
COM5
COM4
COM3
COM2
COM1
NC
NC
31
µ
PD16435, 16435A
8.33
137
171
134
7.50
81
70
41
3
257232217
212
MATERIAL
Detail of Alignment Mark
Base Hole
3.50 17.50
14.7 ± 0.3
10.00
P0.10
P0.1044
10.00
14.7 ± 0.3
(30.00)
12.1+0
-
4.6
COATING AREA
P0.70 ± 0.01X41 = 28.70 ± 0.045 W0.35 ± 0.02
31.00
19.00
BASE FILM
ADHESIVE
COPPER FOIL
PLATING
SOLDER RESIST
: UPILEX-S
: EPOXY
: ELECTROLYSIS Cu
: Sn
: EPOXY
t=75 m
t=12 m
t=18 m
t=MIN 0.25 m
t=25 m
This Figure is shown by Copper side over Polyimide
All tolerances unless otherwise specified 0.05 mm.
Coner radius is 0.3 mm Max.
II Sprocket holes (52.25 mm) for 1 Pattern
2-φ1.30
2-R1.15 ± 0.3
SR
2-φ1.10
Cu
2-φ1.90
Cu
WINDING WAY OUTPUT LEADS
UNWINDING
DIRECTION
FACE(COPPER)
3.00
(1.50)
0.95
2.00
6.00 4.65
31.82+0.04
-
0.07
9.00 5.05 ± 0.3 (4.20)
(12.50) (9.25)
13.00 11.10 ■1.42 ± 0.03
10.90
(0.70)
P0.1003
1.175 ± 0.01
24.8 ± 0.324.8 ± 0.3
1.175 ± 0.01
MAX 0.9
25.5525.55 (50.25)
P0.25 ± 0.01X195 = 48.75 ± 0.075 W0.125 ± 0.015
4.60 P0.10X654.60P0.10X71
P0.0964P0.1013
■4.75 ± 0.03
P0.1
P0.10
10.004.00
8.465 +0
-
2.3 4.465 +0
-
2.3
COATING AREA
4.75 10.90
7.00
0.3 ± 0.3
0.70
(3.80)
6.00 2.50 (0.70)
f1.00
1.00
P0.1005
Cu
m
m
m
m
m
P0.1060
STANDARD TCP PACKAGE DRAWINGS (
µ
PD16435AN-001-052)
32
µ
PD16435, 16435A
from P.C. 25.55
P0.25
0.40
0.30
1.175 ± 0.01
0.60 ± 0.015
0.40 ± 0.015
0.125
1.50
0.50
0.200.10
0.50
0.10
(1.20)
0.10
(1.40) 1.40
10.90 from P.C.
11.10 from P.C.
Detail of Test Pad
and Alignment Mark
DUMMY
V
DD
GND1
CS
RS
RD
WR
WS
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
RESET
SCR
BUSY
SYNC
TEST1
TEST2
3/5
OSC
1
OSC
2
OSC
3
V
CC
C1
-
C1+
C2
-
C2+
C3
-
C3+
V
IN
(
-
)
V
IN
(+)
GND2
V1
V2
V3
V4
V5
DUMMY
NC
NC
COM38
COM39
COM40
COM41
COM42
•
•
•
•
COM73
SEG1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SEG119
COM37
•
•
•
•
COM5
COM4
COM3
COM2
COM1
NC
NC
33
µ
PD16435, 16435A
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (IEI-1212)
Semiconductor Device Mounting Technology Manual (C10535E)
34
µ
PD16435, 16435A
[MEMO]
35
µ
PD16435, 16435A
[MEMO]
32
µ
PD16435, 16435A
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5