General Description
The MAX1165/MAX1166 16-bit, low-power, successive-
approximation analog-to-digital converters (ADCs) fea-
ture automatic power-down, factory-trimmed internal
clock, and a 16-bit wide (MAX1165) or byte wide
(MAX1166) parallel interface. The devices operate from
a single +4.75V to +5.25V analog supply and a +2.7V
to +5.25V digital supply.
The MAX1165/MAX1166 use an internal 4.096V refer-
ence or an external reference. The MAX1165/MAX1166
consume only 1.8mA at a sampling rate of 165ksps with
external reference and 2.7mA with internal reference.
AutoShutdown™ reduces supply current to 0.1mA at
10ksps.
The MAX1165/MAX1166 are ideal for high-perfor-
mance, battery-powered, data-acquisition applications.
Excellent dynamic performance and low power con-
sumption in a small package make the MAX1165/
MAX1166 ideal for circuits with demanding power con-
sumption and space requirements.
The 16-bit wide MAX1165 is available in a 28-pin
TSSOP package and the byte wide MAX1166 is avail-
able in a 20-pin TSSOP package. Both devices are
available in either the 0°C to +70°C commercial, or the
-40°C to +85°C extended temperature range.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Applications
Temperature Sensor/Monitor
Industrial Process Control
I/O Boards
Data-Acquisition Systems
Cable/Harness Tester
Accelerometer Measurements
Digital Signal Processing
Features
♦16-Bit Wide (MAX1165) and Byte Wide (MAX1166)
Parallel Interface
♦High Speed: 165ksps Sample Rate
♦Accurate: ±2LSB INL, 16 Bit No Missing Codes
♦4.096V, 35ppm/°C Internal Reference
♦External Reference Range: +3.8V to +5.25V
♦Single +4.75V to +5.25V Analog Supply Voltage
♦+2.7V to +5.25V Digital Supply Voltage
♦Low Supply Current
1.8mA (External Reference)
2.7mA (Internal Reference)
0.1µA (10ksps, External Reference)
♦Small Footprint
28-Pin TSSOP Package (16-Bit Wide)
20-Pin TSSOP Package (Byte Wide)
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converters
with Parallel Interface
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX1165
0.1µF0.1µF
+5V ANALOG +5V DIGITAL
ANALOG INPUT AIN
R/C
CS
EOC
REF
D0–D15
REFADJ
RESET AGND DGND 0.1µF4.7µF
µP DATA
BUS
AVDD DVDD
Typical Operating Circuit
19-2551; Rev 0; 6/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
Functional Diagram appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE INL
MAX1165ACUI* 0°C to +70°C 28 TSSOP ±2
MAX1165BCUI 0°C to +70°C 28 TSSOP ±2
MAX1165CCUI 0°C to +70°C 28 TSSOP ±4
MAX1165AEUI* -40°C to +85°C 28 TSSOP ±2
MAX1165BEUI* -40°C to +85°C 28 TSSOP ±2
MAX1165CEUI* -40°C to +85°C 28 TSSOP ±4
*Future product—contact factory for availability.
Ordering Information continued at end of data sheet.
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND ........................................-0.3V to (AVDD + 0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V)
CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V
Digital Output (D15–D0, EOC)
to DGND ..............................................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current Into Any Pin ........................50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 10.9mW/°C above+70°C) ........879mW
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
Operating Temperature Ranges
MAX116_ _CU_...................................................0°C to +70°C
MAX116_ _EU_ ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution N 16 Bits
MAX116_A ±2
MAX116_B ±2
Relative Accuracy
(Note 1) INL
MAX116_C ±4
LSB
MAX116_A ±1
No missing codes
over temperature MAX116_B -1 ±1.5
Differential Nonlinearity DNL
MAX116_C ±2
LSB
RMS noise, external reference, includes
quantization noise 0.65 LSBRMS
Transition Noise
Internal reference 0.7 LSBRMS
Offset Error 0.05 1 mV
Gain Error (Note 2) ±0.002 ±0.02 %FSR
Offset Drift 0.6 ppm/°C
Gain Drift 0.2 ppm/°C
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 1kHz, VIN = 4.096VP-P, 165ksps)
Signal-to-Noise Plus Distortion SINAD 86 90 dB
Signal-to-Noise Ratio SNR 87 90 dB
Total Harmonic Distortion THD -102 -90 dB
Spurious-Free Dynamic Range SFDR 92 105 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 81dB 33 kHz
CONVERSION RATE
Sample Rate fSAMPLE 165 ksps
Aperture Delay 27 ns
Aperture Jitter <100 ps
ANALOG INPUT
Input Range VAIN 0V
REF V
Input Capacitance CAIN 40 pF
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL REFERENCE
REF Output Voltage VREF 4.056 4.096 4.136 V
REF Output Tempco TCREF ±25 ppm/°C
REF Short-Circuit Current IREFSC ±10 mA
Capacitive Bypass at REFADJ CREFADJ 0.1 µF
Capacitive Bypass at REF CREF 1µF
REFADJ Input Leakage Current IREFADJ 20 µA
EXTERNAL REFERENCE
REFADJ Buffer Disable Threshold To power down the internal reference AVDD -
0.4
AVDD -
0.1 V
REF Input Voltage Range Internal reference disabled 3.8 AVDD V
VREF = +4.096V, fSAMPLE = 165ksps 50 120
REF Input Current IREF Shutdown mode ±0.1 µA
DIGITAL INPUTS/OUTPUTS
Input High Voltage VIH 0.7 ×
DVDD V
Input Low Voltage VIL 0.3 ×
DVDD V
Input Leakage Current IIN VIH = 0 or DVDD ±0.1 ±1 µA
Input Hysteresis VHYST 0.1 V
Input Capacitance CIN 15 pF
Output High Voltage VOH ISOURCE = 0.5mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V
DVDD -
0.4 V
Output Low Voltage VOL ISINK = 1.6mA, DVDD = +2.7V to +5.25V,
AVDD = +5.25V 0.4 V
Three-State Leakage Current IOZ D0–D15 ±0.1 ±10 µA
Three-State Output Capacitance COZ 15 pF
POWER REQUIREMENTS
Analog Supply Voltage AVDD 4.75 5.25 V
Digital Supply DVDD 2.7 AVDD V
165ksps 2.7 3.2
100ksps 2.0
10ksps 1.0
Internal reference
1ksps 1.0
165ksps 1.8 2.3
100ksps 1.1
10ksps 0.1
Analog Supply Current IAVDD
External reference
1ksps 0.01
mA
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
4 _______________________________________________________________________________________
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 2: Offset nulled.
Note 3: Shutdown supply currents are typically 0.5µA, maximum specification is limited by automated test equipment.
Note 4: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply.
Note 5: To ensure best performance, finish reading the data and wait tBR before starting a new acquisition.
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
165ksps 0.5 0.7
100ksps 0.3
10ksps 0.03
Digital Supply Current IDVDD D0–D15 = all zeros
1ksps 0.003
mA
IAVDD 0.5 5
Full power-down IDVDD 0.5 5 µA
IAVDD 1.0 1.2 mAShutdown Supply Current ISHDN REF and REF buffer enabled
(standby mode) IDVDD
(Note 3) 0.5 5 µA
Power-Supply Rejection Ratio PSRR AVDD = +5V ±5%, full-scale input (Note 4) 68 dB
TIMING CHARACTERISTICS (Figures 1 and 2)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to AVDD, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, CLOAD = 20pF,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Acquisition Time tACQ 1.1
Conversion Time tCONV 4.7 µs
CS Pulse Width High tCSH (Note 5) 40 ns
VDVDD = 4.75V to 5.25V 40
CS Pulse Width Low (Note 5) tCSL VDVDD = 2.7V to 5.25V 60 ns
R/C to CS Fall Setup Time tDS 0ns
VDVDD = 4.75V to 5.25V 40
R/C to CS Fall Hold Time tDH VDVDD = 2.7V to 5.25V 60 ns
VDVDD = 4.75V to 5.25V 40
CS to Output Data Valid tDO VDVDD = 2.7V to 5.25V 80 ns
VDVDD = 4.75V to 5.25V 40
HBEN Transition to Output Data
Valid (MAX1166 Only) tDO1 VDVDD = 2.7V to 5.25V 80 ns
EOC Fall to CS Fall tDV 0ns
VDVDD = 4.75V to 5.25V 40
CS Rise to EOC Rise tEOC VDVDD = 2.7V to 5.25V 80 ns
VDVDD = 4.75V to 5.25V 40
Bus Relinquish Time (Note 5) tBR VDVDD = 2.7V to 5.25V 80 ns
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
_______________________________________________________________________________________ 5
INL vs. OUTPUT CODE
MAX1165/66 toc01
OUTPUT CODE
INL (LSB)
4915216384 32768
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
0 65536
DNL vs. OUTPUT CODE
MAX1165/66 toc02
OUTPUT CODE
DNL (LSB)
4915216384 327680 66536
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
IAVDD + IDVDD SUPPLY CURRENT
vs. SAMPLE RATE
MAX1165/66 toc03
SAMPLE RATE (ksps)
SUPPLY CURRENT (mA)
1001010.1
0.001
0.01
0.1
1
10
0.0001
0.01 1000
IAVDD + IDVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1165/66 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6040200-20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
-40 80
SAMPLE RATE = 165ksps
IAVDD + IDVDD SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1165/66 toc05
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
6040200-20
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 80
INTERNAL REFERENCE
vs. TEMPERATURE
MAX1165/66 toc06
TEMPERATURE (°C)
INTERNAL REFERENCE (V)
6040-20 0 20
4.066
4.076
4.086
4.096
4.106
4.116
4.126
4.136
4.056
-40 80
Typical Operating Characteristics
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA= +25°C, unless otherwise noted.)
OFFSET ERROR
vs. TEMPERATURE
MAX1165/66 toc07
TEMPERATURE (°C)
OFFSET ERROR (µV)
6040200-20
-800
-600
-400
-200
0
200
400
600
800
1000
-1000
-40 80
GAIN ERROR
vs. TEMPERATURE
MAX1165/66 toc08
TEMPERATURE (°C)
GAIN ERROR (%FSR)
6040-20 0 20
-0.015
-0.010
-0.005
0
0.005
0.010
0.015
0.020
-0.020
-40 80
SINAD vs. FREQUENCY
MAX1165/66 toc09
FREQUENCY (kHz)
SINAD (dB)
101
10
20
30
40
50
60
70
80
90
100
0
0.1 100
SAMPLE RATE = 165ksps
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, external reference = +4.096V, CREF = 4.7µF, CREFADJ = 0.1µF, TA= +25°C, unless otherwise noted.)
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
6 _______________________________________________________________________________________
THD vs. FREQUENCY
MAX1165/66 toc10
FREQUENCY (kHz)
THD (dB)
101
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
0.1 100
SAMPLE RATE = 165ksps
SFDR vs. FREQUENCY
MAX1165/66 toc11
FREQUENCY (kHz)
SFDR (dB)
101
10
20
30
40
50
60
70
80
90
100
110
120
0
0.1 100
SAMPLE RATE = 165ksps
FFT AT 1kHz
MAX1165/66 toc12
FREQUENCY (kHz)
MAGNITUDE (dB)
604020
-120
-100
-80
-60
-40
-20
0
-140
080
SAMPLE RATE = 165ksps
SNR vs. FREQUENCY
MAX1165/66 toc13
FREQUENCY (kHz)
SNR (dB)
101
10
20
30
40
50
60
70
80
90
100
110
120
0
0.1 100
SAMPLE RATE = 165ksps
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
_______________________________________________________________________________________ 7
Pin Description
PIN NAME
MAX1165 MAX1166 MAX1165 MAX1166 FUNCTION
1 1 D8 D4/D12 Three-State Digital Data Output
2 2 D9 D5/D13 Three-State Digital Data Output
3 3 D10 D6/D14 Three-State Digital Data Output
4 4 D11 D7/D15 Three-State Digital Data Output. D15 is the MSB.
5—D12 —Three-State Digital Data Output
6—D13 —Three-State Digital Data Output
7—D14 —Three-State Digital Data Output
8—D15 —Three-State Digital Data Output (MSB)
95 R/C
Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode
by holding R/C low during the first falling edge of CS. During the second falling
edge of CS, the level on R/C determines whether the reference and reference
buffer power down or remain on after conversion. Set R/C high during the second
falling edge of CS to power down the reference and buffer, or set R/C low to leave
the reference and buffer powered up. Set R/C high during the third falling edge of
CS to put valid data on the bus.
10 6 EOC End of Conversion. EOC drives low when conversion is complete.
11 7 AVDD Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
12 8 AGND Analog Ground. Primary analog ground (star ground).
13 9 AIN Analog Input
14 10 AGND Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8
(MAX1166).
15 11 REFADJ Refer ence Buffer Outp ut. Byp ass RE FAD J w i th a 0.1µF cap aci tor to AG N D for i nter nal
r efer ence m od e. C onnect RE FAD J to AV
D D
to sel ect exter nal r efer ence m od e.
16 12 REF Reference Input/Output. Bypass REF with a 4.7µF capacitor to AGND for internal
reference mode. External reference input when in external reference mode.
17 —RESET Reset Input. Logic high resets the device.
—13 HBEN
High-Byte Enable Input. Used to multiplex the 14-bit conversion result:
1: Most significant byte available on the data bus.
0: Least significant byte available on the data bus.
18 14 CS
Convert Start. The first falling edge of CS powers up the device and enables
acquire mode when R/C is low. The second falling edge of CS starts conversion.
The third falling edge of CS loads the result onto the bus when R/C is high.
19 15 DGND Digital Ground
20 16 DVDD Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
21 17 D0 D0/D8 Three-State Digital Data Output
22 18 D1 D1/D9 Three-State Digital Data Output
23 19 D2 D2/D10 Three-State Digital Data Output
24 20 D3 D3/D11 Three-State Digital Data Output
25 —D4 —Three-State Digital Data Output
26 —D5 —Three-State Digital Data Output
27 —D6 —Three-State Digital Data Output
28 —D7 —Three-State Digital Data Output
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
8 _______________________________________________________________________________________
Detailed Description
Converter Operation
The MAX1165/MAX1166 use a successive-approxima-
tion (SAR) conversion technique with an inherent track-
and-hold (T/H) stage to convert an analog input into a
16-bit digital output. Parallel outputs provide a high-
speed interface to most microprocessors (µPs). The
Functional Diagram shows a simplified internal archi-
tecture of the MAX1165/MAX1166. Figure 3 shows a
typical application circuit for the MAX1166.
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent T/H function. The single-ended
input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD and/or AGND, allow the input to swing
from AGND - 0.3V to AVDD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
D0–D15 D0–D15
1mA
DGND DGND
DVDD
CLOAD = 20pF
CLOAD = 20pF
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
1mA
Figure 1. Load Circuits
CS
R/C REF POWER-
DOWN BIT
EOC
D0–D15
HBEN*
DATA VALID
D8/D15–
D0/D7*
HIGH-/LOW-
BYTE VALID
HIGH-/LOW-
BYTE VALID
tACQ
tCONV
tCSH
tCSL
tDH
tDO
tDO1 tBR
*HBEN AND BYTE-WIDE DATA BUS
AVAILABLE ON MAX1166 ONLY.
tDS tDV tEOC
HIGH-Z HIGH-Z
tBR
Figure 2. MAX1165/MAX1166 Timing Diagram
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
_______________________________________________________________________________________ 9
Track and Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition ends on the second
falling edge of CS. At this instant, the T/H switches
open. The retained charge on CDAC represents a sam-
ple of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion time to restore node ZERO
to zero within the limits of 16-bit resolution. Force CS low
to put valid data on the bus at the end of the conversion.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the device takes to acquire
the signal. Use the following formula to calculate acqui-
sition time:
tACQ = 11 (RS+ RIN) ✕35pF
where RIN = 800Ω, RS= the input signal’s source
impedance, and tACQ is never less than 1.1µs. A
source impedance less than 1kΩdoes not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
quickly.
Power-Down Modes
Select standby mode or shutdown mode with the R/C
bit during the second falling edge of CS (see the
Selecting Standby or Shutdown Mode section). The
MAX1165/MAX1166 automatically enter either standby
mode (reference and buffer on) or shutdown (reference
and buffer off) after each conversion depending on the
status of R/Cduring the second falling edge of CS.
Internal Clock
The MAX1165/MAX1166 generate an internal conver-
sion clock. This frees the microprocessor from the bur-
den of running the SAR conversion clock. Total
conversion time after entering hold mode (second
falling edge of CS) to end of conversion (EOC) falling is
4.7µs (max).
Applications Information
Starting a Conversion
CS and R/Ccontrol acquisition and conversion in the
MAX1165/MAX1166 (Figure 2). The first falling edge of
CS powers up the device and puts it in acquire mode if
R/Cis low. The convert start is ignored if R/Cis high.
The MAX1165/MAX1166 need at least 10ms
(CREFADJ = 0.1µF, CREF = 4.7µF) for the internal refer-
ence to wake up and settle before starting the conver-
sion if powering up from shutdown. The ADC can wake
up, from shutdown, to an unknown state. Put the ADC
in a known state by completing one “dummy” conver-
sion. The MAX1165/MAX1166 are in a known state,
ready for actual data acquisition, after the completion
of the dummy conversion. A dummy conversion con-
sists of one full conversion cycle.
The MAX1165 provides an alternative reset function to
reset the device (see the RESET section).
MAX1166
0.1µF
+5V ANALOG +5V DIGITAL
0.1µF
ANALOG INPUT AIN
AVDD DVDD
R/C
CS
EOC
REF
D0–D7
OR
D8–D15
REFADJ
HBEN AGND DGND
0.1µF 4.7µF
µP DATA
BUS
HIGH
BYTE
LOW
BYTE
Figure 3. Typical Application Circuit for the MAX1166
AIN
REF
AGND
ZERO
AUTOZERO
RAIL
TRACK
TRACK
HOLD
HOLD
CSWITCH
3pF
CAPACITIVE DAC
CDAC = 32pF RIN
800Ω
Figure 4. Equivalent Input Circuit
MAX1165/MAX1166
Selecting Standby or Shutdown Mode
The MAX1165/MAX1166 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a con-
version. The reference and reference buffer require a
minimum of 10ms (CREFADJ = 0.1µF, CREF = 4.7µF) to
power up and settle from shutdown.
The state of R/Cat the second falling edge of CS
selects which power-down mode the MAX1165/
MAX1166 enter upon conversion completion. Holding
R/Clow causes the MAX1165/MAX1166 to enter stand-
by mode. The reference and buffer are left on after the
conversion completes. R/Chigh causes the MAX1165/
MAX1166 to enter shutdown mode and shut down the
reference and buffer after conversion (Figures 5 and 6).
When using an external reference, set the REF power-
down bit high for lowest current operation.
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/Clow causes the MAX1165/MAX1166 to exit standby
mode and begin acquisition. The reference and refer-
ence buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/Clow
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 16-bit accuracy, allow
10ms (CREFADJ = 0.1µF, CREF = 4.7µF) for the internal
reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1165/MAX1166 is
internally buffered to provide +4.096V output at REF.
Bypass REF to AGND and REFADJ to AGND with 4.7µF
and 0.1µF, respectively.
Fine adjustments can be made to the internal reference
voltage by sinking or sourcing current at REFADJ. The
input impedance of REFADJ is nominally 5kΩ. The
internal reference voltage is adjustable to ±1.5% with
the circuit of Figure 7.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1165/
MAX1166s’ internal buffer amplifier. When connecting an
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
10 ______________________________________________________________________________________
CS
REF
AND
BUFFER
REF POWER-
DOWN BIT
ACQUISITION CONVERSION
DATA
OUT
R/C
EOC
Figure 5. Selecting Standby Mode
REF POWER-
DOWN BIT
ACQUISITION CONVERSION
DATA
OUT
CS
REF
AND
BUFFER
R/C
EOC
Figure 6. Selecting Shutdown Mode
MAX1165
MAX1166
REFADJ
+5V
100kΩ
150kΩ
68kΩ
0.1µF
Figure 7. MAX1165/MAX1166 Reference Adjust Circuit
external reference to REFADJ, the input impedance is
typically 5kΩ. Using the buffered REFADJ input makes
buffering the external reference unnecessary; however,
the internal buffer output must be bypassed at REF with
a 1µF capacitor.
Connect REFADJ to AVDD to disable the internal buffer.
Directly drive REF using an external reference. During
conversion the external reference must be able to drive
100µA of DC load current and have an output imped-
ance of 10Ωor less. REFADJ’s impedance is typically
5kΩ. The DC input impedance of REF is a minimum
40kΩ.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1165/MAX1166s’ equivalent input
noise (38µVRMS) when choosing a reference.
Reading a Conversion Result
EOC is provided to flag the microprocessor when a con-
version is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D15 are the parallel outputs of the MAX1165/
MAX1166. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conver-
sion. Data is loaded onto the bus with the third falling
edge of CS with R/Chigh after tDO. Bringing CS high
forces the output bus back to high impedance. The
MAX1165/MAX1166 then wait for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1165 loads the conversion result onto a 16-bit
wide data bus while the MAX1166 has a byte-wide out-
put format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
RESET
Toggle RESET with CS high. The next falling edge of CS
begins acquisition. This reset is an alternative to the
dummy conversion explained in the Starting a Conversion
section.
Transfer Function
Figure 8 shows the MAX1165/MAX1166 output transfer
function. The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, the input channel should be switched immedi-
ately after acquisition, rather than near the end of or
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output volt-
age change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sam-
pling capacitor array connects to AIN (the amplifier out-
put), causing some output disturbance. Ensure that the
sampled voltage has settled to within the required limits
before the end of the acquisition time. If the frequency
of interest is low, AIN can be bypassed with a large
enough capacitor to charge the internal sampling
capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capaci-
tive load (in parallel with any AIN bypass capacitor
used) and also settle quickly. An example of this circuit
using the MAX4434 is given in Figure 9.
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
______________________________________________________________________________________ 11
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
12 3
0FS
INPUT VOLTAGE (LSB) FS - 3/2LSB
11...110
11...101
00...011
00...010
00...001
00...000
FS = VREF
1LSB = VREF
65536
Figure 8. MAX1165/MAX1166 Transfer Function
MAX1165
MAX1166
MAX4434
ANALOG
INPUT
10Ω
AIN 40pF
Figure 9. MAX1165/MAX1166 Fast Settling Input Buffer
MAX1165/MAX1166
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and ana-
log supply by connecting them with a low-value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AVDD supply. Bypass AVDD to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1165/MAX1166
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02 ✕N + 1.76)dB
where N = 16 bits.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude and V2through
V5are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
THD
VVVV
V
=×
+++
20
22324252
1
log
ENOB SINAD
=−176
602
.
.
SINAD dB Signal
Noise Distortion
RMS
RMS
( ) log ()
=× +
20
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
12 ______________________________________________________________________________________
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
______________________________________________________________________________________ 13
Chip Information
TRANSISTOR COUNT: 15,140
PROCESS: BiCMOS
REFERENCE
CLOCK
OUTPUT
REGISTERS
CAPACITIVE
DAC
SUCCESSIVE-
APPROXIMATION
REGISTER AND
CONTROL LOGIC
16 OR 8* 16 OR 8* D0–D15
OR
D0/D7–D8/D15*
REFADJ
REF
EOC
HBEN*
AIN
AGND
AVDD AGND DVDD DGND
RESET**
CS
R/C
* BYTE WIDE (MAX1166 ONLY)
**16-BIT WIDE (MAX1165 ONLY)
5kΩ
MAX1165
MAX1166
Functional Diagram
Ordering Information (continued)
PART TEMP RANGE PIN-PACKAGE INL
MAX1166ACUP* 0°C to +70°C 20 TSSOP ±2
MAX1166BCUP 0°C to +70°C 20 TSSOP ±2
MAX1166CCUP 0°C to +70°C 20 TSSOP ±4
MAX1166AEUP* -40°C to +85°C 20 TSSOP ±2
MAX1166BEUP* -40°C to +85°C 20 TSSOP ±2
MAX1166CEUP* -40°C to +85°C 20 TSSOP ±4
*Future product—contact factory for availability.
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
14 ______________________________________________________________________________________
Pin Configurations
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D7
D6
D5
D4
D3
D2
REFADJ
D1
D0
DVDD
DGND
RESET
REF
AGND
AIN
AGND
R/C
D15
D14
D13
D12
D11
D10
D9
D8
TSSOP
TOP VIEW
MAX1165
EOC
AVDD CS
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
D3/D11
D2/D10
D1/D9
D0/D8D7/D15
D6/D14
D5/D13
D4/D12
DVDD
DGND
CS
HBENAGND
AVDD
12
11
9
10
REF
REFADJAGND
AIN
MAX1166
TSSOP
R/C
EOC
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP.EPS
