IRFP140N Data Sheet January 2002 33A, 100V, 0.040 Ohm, N-Channel Power MOSFET Packaging Features JEDEC TO-247 SOURCE DRAIN GATE * Ultra Low On-Resistance - rDS(ON) = 0.040, VGS = 10V * Simulation Models - Temperature Compensated PSPICETM and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.fairchildsemi.com * Peak Current vs Pulse Width Curve DRAIN (TAB) * UIS Rating Curve Ordering Information Symbol PART NUMBER D IRFP140N PACKAGE TO-247 BRAND IRFP140N G S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRFP140N UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 100 V Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS 20 V Drain Current Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 33 23 Figure 4 A A Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 0.80 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC NOTES: 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. (c)2002 Fairchild Semiconductor Corporation IRFP140N Rev. B IRFP140N Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 100 - - V - - 1 A OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250A, VGS = 0V (Figure 11) VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC - - 250 A VGS = 20V - - 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 33A, VGS = 10V (Figure 9) - 0.033 0.040 TO-247 - - 1.25 oC/W - - 30 oC/W - - 100 ns - 9.5 - ns - 57 - ns td(OFF) - 40 - ns tf - 55 - ns tOFF - - 145 ns - 66 79 nC - 35 42 nC THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time tON td(ON) tr Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 33A VGS = 10V, RGS = 9.1 (Figures 18, 19) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V VDD = 50V, ID = 33A, Ig(REF) = 1.0mA - 2.4 2.9 nC Gate to Source Gate Charge Qgs - 5.4 - nC Gate to Drain "Miller" Charge Qgd - 13 - nC (Figures 13, 16, 17) CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 1220 - pF - 295 - pF - 100 - pF MIN TYP MAX UNITS Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge (c)2002 Fairchild Semiconductor Corporation SYMBOL VSD TEST CONDITIONS ISD = 33A - - 1.25 V ISD = 17A - - 1.00 V trr ISD = 33A, dISD/dt = 100A/s - - 112 ns QRR ISD = 33A, dISD/dt = 100A/s - - 400 nC IRFP140N Rev. B IRFP140N Typical Performance Curves 40 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 VGS = 10V 30 20 10 0.2 0 0 25 50 75 100 150 125 0 175 25 TC , CASE TEMPERATURE (oC) 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 600 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 100 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 20 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY (c)2002 Fairchild Semiconductor Corporation IRFP140N Rev. B IRFP140N Typical Performance Curves (Continued) 200 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 300 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 100s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 10ms 100 10 STARTING TJ = 150oC 0.01 300 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.1 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 60 60 VGS = 20V VGS = 10V ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 40 TJ = 175oC 20 TJ = -55oC VGS = 7V VGS = 6V 40 VGS =5V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC TJ = 25oC 0 0 2 0 6 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 FIGURE 8. SATURATION CHARACTERISTICS 1.2 VGS = 10V, ID = 33A VGS = VDS, ID = 250A 2.5 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA ID, DRAIN CURRENT (A) STARTING TJ = 25oC 10 0.001 1 1 100 2.0 1.5 1.0 0.8 1.0 0.6 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation 200 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE IRFP140N Rev. B IRFP140N Typical Performance Curves (Continued) 4000 VGS = 0V, f = 1MHz ID = 250A C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 1.1 1.0 1000 CISS = CGS + CGD COSS CDS + CGD 100 CRSS = CGD 0.9 -80 -40 0 40 80 120 160 20 0.1 200 TJ , JUNCTION TEMPERATURE (oC) 1.0 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 50V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 33A ID = 17A 2 0 10 0 20 30 Qg, GATE CHARGE (nC) 40 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS tP + RG VDS IAS VDD VDD - VGS DUT 0V tP IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation FIGURE 15. UNCLAMPED ENERGY WAVEFORMS IRFP140N Rev. B IRFP140N Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM IRFP140N Rev. B IRFP140N PSPICE Electrical Model .SUBCKT IRFP140N 2 1 3 ; rev 15 Jan 2000 CA 12 8 1.95e-9 CB 15 14 1.90e-9 CIN 6 8 1.12e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD LDRAIN DPLCAP DRAIN 2 5 10 5 51 ESLC 11 - RDRAIN 6 8 EVTHRES + 19 8 + LGATE GATE 1 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD + 17 EBREAK 18 50 - IT 8 17 1 EVTEMP RGATE + 18 22 9 20 21 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.00e-2 RGATE 9 20 1.77 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 ESG LDRAIN 2 5 1.0e-9 LGATE 1 9 6.19e-9 LSOURCE 3 7 2.18e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 112.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RLSOURCE S1A 12 S2A 13 8 S1B CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 VBAT 5 8 EDS - - IT 14 + + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RBREAK 15 14 13 - + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*71),3.5))} .MODEL DBODYMOD D (IS = 1.20e-12 RS = 4.2e-3 XTI = 5 TRS1 = 1.3e-3 TRS2 = 8.0e-6 CJO = 1.50e-9 TT = 7.47e-8 M = 0.63) .MODEL DBREAKMOD D (RS = 4.2e-1 TRS1 = 8e-4 TRS2 = 3e-6) .MODEL DPLCAPMOD D (CJO = 1.45e-9 IS = 1e-30 M = 0.82) .MODEL MMEDMOD NMOS (VTO = 3.11 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.77) .MODEL MSTROMOD NMOS (VTO = 3.57 KP = 33.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 17.7 ) .MODEL RBREAKMOD RES (TC1 =1.05e-3 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -8.6e-6) .MODEL RVTEMPMOD RES (TC1 = -3.0e-3 TC2 =1.5e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.2 VOFF= -3.1) VON = -3.1 VOFF= -6.2) VON = -1.0 VOFF= 0.5) VON = 0.5 VOFF= -1.0) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation IRFP140N Rev. B IRFP140N SABER Electrical Model REV 15 Jan 2000 template IRFP140N n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.20e-12, cjo = 1.50e-9, tt = 7.47e-8, xti = 5, m = 0.63) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.45e-9, is = 1e-30, m = 0.82) m..model mmedmod = (type=_n, vto = 3.11, kp = 5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.57, kp = 33.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.68, kp = 0.09, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -3.1) DPLCAP sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.1, voff = -6.2) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0) c.ca n12 n8 = 1.95e-9 c.cb n15 n14 = 1.90e-9 c.cin n6 n8 = 1.12e-9 DRAIN 2 RSLC1 51 RLDRAIN RDBREAK RSLC2 72 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + i.it n8 n17 = 1 LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 MWEAK MSTRO CIN DBODY EBREAK + 17 18 MMED m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 71 11 16 6 RLGATE res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7 res.rdbody n71 n5 = 4.2e-3, tc1 = 1.30e-3, tc2 = 8.0e-6 res.rdbreak n72 n5 = 4.2e-1, tc1 = 8.0e-4, tc2 = 3.0e-6 res.rdrain n50 n16 = 2.00e-2, tc1 = 9.40e-3, tc2 = 2.93e-5 res.rgate n9 n20 = 1.77 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.5e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -3.0e-3, tc2 = 1.5e-7 res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -8.6e-6 21 RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 6.19e-9 l.lsource n3 n7 = 2.18e-9 LDRAIN 5 - 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 112.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/71))** 3.5)) } } (c)2002 Fairchild Semiconductor Corporation IRFP140N Rev. B IRFP140N SPICE Thermal Model th REV 15 Jan 2000 JUNCTION IRFP140NT CTHERM1 th 6 2.60e-3 CTHERM2 6 5 8.85e-3 CTHERM3 5 4 7.60e-3 CTHERM4 4 3 7.65e-3 CTHERM5 3 2 1.22e-2 CTHERM6 2 tl 8.70e-2 RTHERM1 th 6 9.00e-3 RTHERM2 6 5 1.80e-2 RTHERM3 5 4 9.15e-2 RTHERM4 4 3 2.43e-1 RTHERM5 3 2 3.10e-1 RTHERM6 2 tl 3.21e-1 SABER Thermal Model RTHERM1 CTHERM1 6 CTHERM2 RTHERM2 5 CTHERM3 RTHERM3 SABER thermal model IRFP140NT template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.60e-3 ctherm.ctherm2 6 5 = 8.85e-3 ctherm.ctherm3 5 4 = 7.60e-3 ctherm.ctherm4 4 3 = 7.65e-3 ctherm.ctherm5 3 2 = 1.22e-2 ctherm.ctherm6 2 tl = 8.70e-2 rtherm.rtherm1 th 6 = 9.00e-3 rtherm.rtherm2 6 5 = 1.80e-2 rtherm.rtherm3 5 4 = 9.15e-2 rtherm.rtherm4 4 3 = 2.43e-1 rtherm.rtherm5 3 2 = 3.10e-1 rtherm.rtherm6 2 tl = 3.21e-1 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2002 Fairchild Semiconductor Corporation CASE IRFP140N Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4