5
6
7
8
9
10
11
25
24
23
22
21
20
19
432128
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
DIR
SAB
CLKAB
B8
B7
A8
GND
NC
NC
CLKBA
SBA
V
A7
B6
17 18
27 26
NC – No internal connection
CC
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SN54ALS646, SN54ALS648, SN54AS646 . . . JT PACKAGE
SN74ALS646A, SN74ALS648A, SN74AS646,
SN74AS648 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54ALS646, SN54ALS648, SN54AS646 . . . FK PACKAGE
(TOP VIEW)
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Independent Registers for A and B Buses
•Multiplexed Real-Time and Stored Data
•Choice of True or Inverting Data Paths
•Choice of 3-State or Open-Collector
Outputs
•Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICE OUTPUT LOGIC
SN54ALS646, SN74ALS646A, ′AS646 3 state T rue
SN54ALS648, SN74ALS648A, SN74AS648 3 state Inverting
description
These devices consist of bus-transceiver circuits
with 3-state or open-collector outputs, D-type
flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Data on the A or B bus is clocked into the registers
on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the octal bus
transceivers and registers.
Output-enable (OE) and direction-control (DIR)
inputs control the transceiver functions. In the
transceiver mode, data present at the high-
impedance port may be stored in either or both
registers.
The select-control (SAB and SBA) inputs can
multiplex stored and real-time (transparent mode)
data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In
the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other
register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended
maximum IOL in the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646,
SN54ALS648, or SN74ALS648A.
The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are
characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
21
X
3
DIR
X
1
CLKAB 23
CLKBA
X
2
SAB
X
22
SBA
X
STORAGE FROM
A, B, OR A AND B
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
HX
XXX
X
X
XL H H or L X H X
↑↑
↑↑
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE OE
OEOE
Figure 1. Bus-Management Functions
Pin numbers shown are for the DW, JT, and NT packages.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN54ALS646, SN54AS646, SN74ALS646A, SN74AS646
INPUTS DATA I/O
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION
OR
FUNCTION
X X ↑X X X Input Unspecified†Store A, B unspecified†
XXX ↑X X Unspecified†Input Store B, A unspecified†
H X ↑ ↑ X X Input Input Store A and B data
HX H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54ALS648, SN74ALS648A, SN74AS648
INPUTS DATA I/O
OPERATION OR FUNCTION
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
OPERATION
OR
FUNCTION
X X ↑X X X Input Unspecified†Store A, B unspecified†
XXX ↑X X Unspecified†Input Store B, A unspecified†
H X ↑ ↑ X X Input Input Store A and B data
HX H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
LL X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols†
A1 4B1
20
4D
5
7
7
5
1
1
6D ≥1
≥1
1
2
A2 5B2
19
A3 6B3
18
A4 7B4
17
A5 8B5
16
A6 9B6
15
A7 10 B7
14
A8 11 B8
13
SN54ALS646, SN54AS646,
SN74ALS646A, SN74AS646
OE G3
21
3 EN2 [AB]
G5
22
SBA
3 EN1 [BA]
3
DIR
23
CLKBA
1
CLKAB
G7
2
SAB
C6
C4
A1 4B1
20
4D
5
7
7
5
1
1
6D ≥1
≥1
1
2
A2 5B2
19
A3 6B3
18
A4 7B4
17
A5 8B5
16
A6 9B6
15
A7 10 B7
14
A8 11 B8
13
SN54ALS648,
SN74ALS648A, SN74AS648
OE G3
21
3 EN2 [AB]
G5
22
SBA
3 EN1 [BA]
3
DIR
23
CLKBA
1
CLKAB
G7
2
SAB
C6
C4
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
A1 B1
1D
C1
1D
C1
One of Eight Channels
20
4
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
SN54ALS646, SN54AS646,
SN74ALS646A, SN74AS646
A1 B1
1D
C1
1D
C1
One of Eight Channels
20
4
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
SN54ALS648,
SN74ALS648A, SN74AS648
Pin numbers shown are for the DW, JT, and NT packages.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: Control inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS646 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS646A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN54ALS646 SN74ALS646A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –12 –15 mA
I
Low level output current
12 24
mA
I
OL
L
ow-
l
eve
l
ou
t
pu
t
curren
t
48‡m
A
fclock Clock frequency 0 35 0 40 MHz
twPulse duration, CLKBA or CLKAB high or low 14.5 12.5 ns
tsu Setup time, A before CLKAB↑ or B before CLKBA↑15 10 ns
thHold time, A after CLKAB↑ or B after CLKBA↑0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
‡Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS646 SN74ALS646A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2
VOH
IOH = –3 mA 2.4 3.2 2.4 3.2
V
V
OH VCC = 4.5 V IOH = –12 mA 2
V
IOH = –15 mA 2
IOL = 12 mA 0.25 0.4 0.25 0.4
VOL VCC = 4.5 V IOL = 24 mA 0.35 0.5 V
IOL = 48 mA‡0.35 0.5
II
Control inputs
VCC =55V
VI = 7 V 0.1 0.1
mA
I
IA or B ports
V
CC =
5
.
5
V
VI = 5.5 V 0.1 0.1
mA
I
Control inputs
V55V
20 20
A
I
IH A or B ports§
V
CC =
5
.
5
V
,
I =
.
20 20 µ
A
I
Control inputs
V55V
–0.2 –0.2
mA
I
IL A or B ports§
V
CC =
5
.
5
V
,
I =
.
–0.2 –0.2 m
A
IOVCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
Outputs high 47 76 47 76
ICC VCC = 5.5 V Outputs low 55 88 55 88 mA
Outputs disabled 55 88 55 88
†All typical values are at VCC = 5 V, TA = 25°C.
‡Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25
§For I/O ports, the parameters IIH and IIL include the off-state output current.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN54ALS646 SN74ALS646A
MIN MAX MIN MAX
fmax 35 40 MHz
tPLH
CLKBA or CLKAB
AorB
10 35 7 30
ns
tPHL
CLKBA
or
CLKAB
A
or
B
5 20 5 17
ns
tPLH
AorB
BorA
522 3 20
ns
tPHL
A
or
B
B
or
A
3 15 3 12
ns
tPLH SBA or SAB
‡
AorB
10 40 7 35
ns
tPHL (stored data low)
A
or
B
5 23 5 20
ns
tPLH SBA or SAB
‡
AorB
8 30 6 25
ns
tPHL (stored data high)
A
or
B
5 24 5 20
ns
tPZH
OE
AorB
320 2 17
ns
tPZL
OE
A
or
B
522 4 20
ns
tPHZ
OE
AorB
1 12 1 10
ns
tPLZ
OE
A
or
B
120 2 16
ns
tPZH
DIR
AorB
538 3 30
ns
tPZL
DIR
A
or
B
530 4 25
ns
tPHZ
DIR
AorB
1 12 1 10
ns
tPLZ
DIR
A
or
B
221 2 16
ns
†For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: Control inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS648 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS648A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN54ALS648 SN74ALS648A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –12 –15 mA
IOL Low-level output current 12 24 mA
fclock Clock frequency 0 35 0 40 MHz
twPulse duration, CLKBA or CLKAB high or low 14.5 12.5 ns
tsu Setup time, A before CLKAB↑ or B before CLKBA↑15 10 ns
thHold time, A after CLKAB↑ or B after CLKBA↑0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS648 SN74ALS648A
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2
VOH
IOH = –3 mA 2.4 3.2 2.4 3.2
V
V
OH VCC = 4.5 V IOH = –12 mA 2
V
IOH = –15 mA 2
VOL
VCC =45V
IOL = 12 mA 0.25 0.4 0.25 0.4
V
V
OL
V
CC =
4
.
5
V
IOL = 24 mA 0.35 0.5
V
II
Control inputs
VCC =55V
VI = 7 V 0.1 0.1
mA
I
IA or B ports
V
CC =
5
.
5
V
VI = 5.5 V 0.1 0.1
mA
I
Control inputs
V55V
20 20
A
I
IH A or B ports‡
V
CC =
5
.
5
V
,
I =
.
20 20 µ
A
I
Control inputs
V55V
–0.2 –0.2
mA
I
IL A or B ports‡
V
CC =
5
.
5
V
,
I =
.
–0.2 –0.2 m
A
IO§VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
Outputs high 47 76 47 76
ICC VCC = 5.5 V Outputs low 57 88 57 88 mA
Outputs disabled 57 88 57 88
†All typical values are at VCC = 5 V, TA = 25°C.
‡For I/O ports, the parameters IIH and IIL include the off-state output current.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN54ALS648 SN74ALS648A
MIN MAX MIN MAX
fmax 35 40 MHz
tPLH
CLKBA or CLKAB
AorB
839 7 33
ns
tPHL
CLKBA
or
CLKAB
A
or
B
5 23 5 20
ns
tPLH
AorB
BorA
320 2 17
ns
tPHL
A
or
B
B
or
A
2 12 2 10
ns
tPLH SBA or SAB
‡
AorB
5 44 5 39
ns
tPHL (stored data low)
A
or
B
4 26 4 22
ns
tPLH SBA or SAB
‡
AorB
6 30 6 25
ns
tPHL (stored data high)
A
or
B
6 25 6 21
ns
tPZH
OE
AorB
425 2 22
ns
tPZL
OE
A
or
B
425 4 22
ns
tPHZ
OE
AorB
1 12 1 10
ns
tPLZ
OE
A
or
B
221 2 15
ns
tPZH
DIR
AorB
435 2 27
ns
tPZL
DIR
A
or
B
325 3 19
ns
tPHZ
DIR
AorB
1 17 1 14
ns
tPLZ
DIR
A
or
B
222 2 15
ns
†For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: Control inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54AS646 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS646 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN54AS646 SN74AS646
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –12 –15 mA
IOL Low-level output current 32 48 mA
fclock*Clock frequency 0 75 0 90 MHz
t
*
Pulse duration
CLKBA or CLKAB high 6 5
ns
t
w
*
P
u
lse
d
u
ration
CLKBA or CLKAB low 7 6
ns
tsu*Setup time, A before CLKAB↑ or B before CLKBA↑7 6 ns
th*Hold time, A after CLKAB↑ or B before CLKBA 0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS646 SN74AS646
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2
VOH
IOH = –3 mA 2.4 3.2 2.4 3.2
V
V
OH VCC = 4.5 V IOH = –12 mA 2
V
IOH = –15 mA 2
VOL
VCC =45V
IOL = 32 mA 0.25 0.5
V
V
OL
V
CC =
4
.
5
V
IOL = 48 mA 0.35 0.5
V
II
Control inputs VCC = 5.5 V, VI = 7 V 0.1 0.1
mA
I
IA or B ports VCC = 5.5 V, VI = 5.5 V 0.1 0.1
mA
I
Control inputs
V55V
20 20
A
I
IH A or B ports‡
V
CC =
5
.
5
V
,
I =
.
70 70 µ
A
I
Control input
V55V
–0.5 –0.5
mA
I
IL A or B ports‡
V
CC =
5
.
5
V
,
I =
.
–0.75 –0.75 m
A
IO§VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
Outputs high 120 195 120 195
ICC VCC = 5.5 V Outputs low 130 211 130 211 mA
Outputs disabled 130 211 130 211
†All typical values are at VCC = 5 V, TA = 25 °C.
‡For I/O ports, the parameters IIH and IIL include the off-state output current.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN54AS646 SN74AS646
MIN MAX MIN MAX
fmax*75 90 MHz
tPLH
CLKBA or CLKAB
AorB
29.5 2 8.5
ns
tPHL
CLKBA
or
CLKAB
A
or
B
2 10 2 9
ns
tPLH
AorB
BorA
211.5 2 9
ns
tPHL
A
or
B
B
or
A
1 8 1 7
ns
tPLH
SBA or SAB‡
AorB
213.5 2 11
ns
tPHL
SBA
or
SAB‡
A
or
B
211 2 9
ns
tPZH
OE
AorB
211 2 9
ns
tPZL
OE
A
or
B
315 3 14
ns
tPHZ
OE
AorB
211 2 9
ns
tPLZ
OE
A
or
B
211 2 9
ns
tPZH
DIR
AorB
321 3 16
ns
tPZL
DIR
A
or
B
324 3 18
ns
tPHZ
DIR
AorB
2 12 2 10
ns
tPLZ
DIR
A
or
B
212 2 10
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
†For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI: Control inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN74AS648 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN74AS648
UNIT
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –15 mA
IOL Low-level output current 48 mA
fclock Clock frequency 0 90 MHz
t
Pulse duration
CLKBA or CLKAB high 5
ns
t
w
P
u
lse
d
u
ration
CLKBA or CLKAB low 6
ns
tsu Setup time, A before CLKAB↑ or B before CLKBA↑6 ns
thHold time, A after CLKAB↑ or B before CLKBA 0 ns
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN74AS648
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP‡MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2
VOH
VCC =45V
IOH = –3 mA 2.4 3.2 V
V
CC =
4
.
5
V
IOH = –15 mA 2
VOL VCC = 4.5 V, IOL = 48 mA 0.35 0.5 V
II
Control inputs
VCC =55V
VI = 7 V 0.1
mA
I
IA or B ports
V
CC =
5
.
5
V
VI = 5.5 V 0.1
mA
I
Control inputs
V55V
V27V
20
A
I
IH A or B ports§
V
CC =
5
.
5
V
,
V
I =
2
.
7
V
70 µ
A
I
Control input
V55V
V04V
–0.5
mA
I
IL A or B ports§
V
CC =
5
.
5
V
,
V
I =
0
.
4
V
–0.75 m
A
IOVCC = 5.5 V, VO = 2.25 V –30 –112 mA
Outputs high 110 185
ICC VCC = 5.5 V Outputs low 120 195 mA
Outputs disabled 120 195
‡All typical values are at VCC = 5 V, TA = 25 °C.
§For I/O ports, the parameters IIH and IIL include the off-state output current.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX†UNIT
SN74AS648
MIN MAX
fmax 90 MHz
tPLH
CLKBA or CLKAB
AorB
28.5
ns
tPHL
CLKBA
or
CLKAB
A
or
B
2 9
ns
tPLH
AorB
BorA
2 8
ns
tPHL
A
or
B
B
or
A
1 7
ns
tPLH
SBA or SAB‡
AorB
211
ns
tPHL
SBA
or
SAB‡
A
or
B
2 9
ns
tPZH
OE
AorB
2 9
ns
tPZL
OE
A
or
B
315
ns
tPHZ
OE
AorB
2 9
ns
tPLZ
OE
A
or
B
2 9
ns
tPZH
DIR
AorB
316
ns
tPZL
DIR
A
or
B
318
ns
tPHZ
DIR
AorB
2 10
ns
tPLZ
DIR
A
or
B
210
ns
†For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡These parameters are measured with the internal output state of the storage register opposite that of the bus input.
SN54ALS646, SN54ALS648, SN54AS646
SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPHZ
tPLZ
tPHL tPLH 0.3 V
tPZL
tPZH
TEST S1
Open
Open
Open
tPHL
tPZH
tPZL Closed
Open
Closed
tPHZ
tPLZ
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test Point
R1 = 500 Ω
S1
CL = 50 pF
(see Note A)
7 V
Open
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
Out-of-Phase
Output
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B) 0 V
VOH
VOL
3.5 V
In-Phase
Output
0.3 V
tPLH
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
SWITCH POSITION TABLE
R2 = 500 Ω
VCC
RL
Test Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-87595013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8759501KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
5962-8759501LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
5962-89956013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
5962-8995601LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
5962-9052301LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
SN54AS646JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
SN74ALS646A-1DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1DWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1DWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1DWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646A-1NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS646A-1NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS646ADW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ADWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS646ANT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS646ANTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS648ADW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS648ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS648ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALS648ANT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74ALS648ANTE4 ACTIVE PDIP NT 24 15 Pb-Free CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
SN74AS646DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS646DWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS646DWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS646NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74AS646NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74AS648DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS648DWE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS648DWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AS648NT ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74AS648NT3 OBSOLETE PDIP NT 24 TBD Call TI Call TI
SN74AS648NTE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SNJ54ALS646FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
SNJ54ALS646JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
SNJ54ALS646W OBSOLETE CFP W 24 TBD Call TI Call TI
SNJ54ALS648FK OBSOLETE LCCC FK 24 TBD Call TI Call TI
SNJ54ALS648JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
SNJ54ALS648W OBSOLETE CFP W 24 TBD Call TI Call TI
SNJ54AS646FK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AS646JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type
SNJ54AS646W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS646, SN54ALS648, SN54AS646, SN74AS646 :
•Catalog: SN74ALS646,SN74ALS648
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS646A-1DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74ALS646ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS646A-1DWR SOIC DW 24 2000 346.0 346.0 41.0
SN74ALS646ADWR SOIC DW 24 2000 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
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