General Description
The DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their ±5% frequency deviations:
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
Frequency margining is a circuit operation to change
the output frequency to 5% higher or 5% lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-level voltage signal
to control the output frequency. In a low-level state, the
output frequency is set to the nominal frequency. When
set to a high-level state, the frequency output is set to
the nominal frequency plus 5%. When set to the mid-
level state, the frequency output is equal to the nominal
frequency minus 5%. If left open, the MS pin is pulled
low by an internal 100kΩ(nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are available with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN levels of the LVPECL driver go to
the LVPECL bias voltage, while the output of the LVDS
driver is a logical one. The OE input is an active-high
logic signal and has an internal 100kΩpullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
The devices operate from a single 3.3V supply voltage.
Applications
Memory Clocks
RAID Systems
Features
♦Frequency Margining: ±5%
♦Nominal Clock Output Frequencies: 125MHz,
133.33MHz, and 200MHz
♦Jitter < 0.9ps RMS from 12kHz to 20MHz
♦LVPECL or LVDS Output
♦3.3V Operating Voltage
♦Operating Temperature Range: -40°C to +85°C
♦Supply Current: < 100mA at 3.3V
♦Excellent Power-Supply Noise Rejection
♦5mm x 3.2mm Ceramic LCCC Package
♦Output Enable/Disable
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
DS4M125/
DS4M133/
DS4M200
DS4M125/
DS4M133/
DS4M200
VCC OUTP
OUTN
LVDS OPTION
OE
MS
GND
0.01μF
0.1μF
100Ω
OE
MS
GND
VCC OUTP
OUTN
LVPECL OPTION
0.01μF
0.1μF
50Ω
50Ω
PECL_BIAS AT
VCC - 2.0V
Typical Operating Circuit
Rev 0; 12/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
DS4M125P+33 -40°C to +85°C 10 LCCC
DS4M125D+33 -40°C to +85°C 10 LCCC
DS4M133P+33 -40°C to +85°C 10 LCCC
DS4M133D+33 -40°C to +85°C 10 LCCC
DS4M200P+33 -40°C to +85°C 10 LCCC
DS4M200D+33 -40°C to +85°C 10 LCCC
+
Denotes a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Pin Configuration and Selector Guide appear at end of
data sheet.
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage Range (VCC) .....................-0.3V to +4.0V
Continuous Power Dissipation (TA= +70°C) ...................330mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+125°C
Storage Temperature Range ...............................-55°C to +85°C
Soldering Temperature
(3 passes max of reflow)..........................................Refer to the
IPC/JEDEC J-STD-020 Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range VCC (Note 1) 3.135 3.3 3.465 V
ICC_D LVDS, output loaded or unloaded 52 75
ICC_PU LVPECL, output unloaded 49 70
Operating Current
ICC_PI LVPECL, output loaded 74 100
mA
Inactive Current ICC_OEZ V
OE = VIL 52 85 mA
OUTPUT FREQUENCY SPECIFICATIONS
DS4M125 MS = 0, OE = 1 125
DS4M133 MS = 0, OE = 1 133.33
Frequency
DS4M200
fO
MS = 0, OE = 1 200
MHz
Frequency Stability fTOTAL/fOOver temperature range, aging, load,
supply, and initial tolerance (Note 3) -50 +50 ppm
Frequency Stability Over
Temperature fTEMP/f VCC = 3.3V -35 +35 ppm
Initial Tolerance fINITIAL/fV V
CC = 3.3V, TA = +25°C ±20 ppm
Frequency Change Due to VCC fVCC/f VCC = 3.3V ±5% -3 +3 ppm/V
Frequency Change Due to Load
Variation fLOAD/fO
±10% variation in termination
resistance ±1 ppm
Aging (15 Years) fAGING -7 +7 ppm
Phase Jitter JRMS Integrated phase RMS; 12kHz to 80MHz,
VCC = 3.3V, TA = +25°C < 0.9 ps
Accumulated Deterministic Jitter
Due to Reference Spurs No margin 155.52MHz output 0.6 ps
10kHz 12.9
100kHz (Note 4) 26.3
200kHz (Note 4) 20.1
Accumulated Deterministic Jitter
Due to Power-Supply Noise
1MHz (Note 4) 6.4
ps
Startup Time tSTRT 1.0 ms
Frequency Switch Time tSWITCH 0.5 ms
Input-Voltage High (OE) VIH (Note 5) 0.7 x
VCC V
CC V
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Voltage Low (OE) VIL (Note 5) 0
0.3 x
VCC V
Input-Leakage High (OE) ILEAKH OE voltage = VCC -5 +5 μA
Input-Leakage Low (OE) ILEAKL OE voltage = GND -20 -50 μA
Input-Leakage High (MS) ILEAKH MS voltage = VCC 20 50 μA
Input-Leakage Low (MS) ILEAKL MS voltage = GND -5 +5 μA
Input Voltage: High Level (MS) VIH (Note 5)
0.75 x
VCC +
0.15V
V
CC V
Input Voltage: Mid Level (MS) VIM (Note 5)
0.25 x
VCC +
0.15V
0.75 x
VCC -
0.15V
V
Input Voltage: Low Level (MS) VIL (Note 5) 0
0.25 x
VCC -
0.15V
V
LVDS
Output High Voltage VOH 100 differential load (Notes 2, 5) 1.475 V
Output Low Voltage VOL 100 differential load (Notes 2, 5) 0.925 V
Differential Output Voltage |VOD|100 differential load 250 425 mV
Change in VOD for
Complementary States |VOD| 100 differential load 25 mV
Offset Output Voltage VOS 100 differential load (Note 2) 1.125 1.275 V
Change in VOS for
Complementary States |VOS| 100 differential load 150 mV
Differential Output Impedance ROLVDS 80 140
LVSSLVDSO OUTN or OUTP shorted to ground and
measure the current in the shorting path 40
Output Current
LLVDSO OUTN and OUTP shorted together and
measure the change in ICC 6.5
mA
Output Rise Time (Differential) tRLVDSO 20% to 80% 175 ps
Output Fall Time (Differential) tFLVDSO 80% to 20% 175 ps
Duty Cycle DCYCLE_LVDS 45 55 %
Propagation Delay from OE Going
LOW to Logical 1 at OUTP tPA1 (Figure 2) 200 ns
Propagation Delay from OE Going
HIGH to Output Active tP1A (Figure 2) 200 ns
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVPECL
Output High Voltage (Note 2) VOH Output connected to 50 at PECL_BIAS
at VCC - 2.0V
VCC -
1.085
VCC -
0.88 V
Output Low Voltage (Note 2) VOL Output connected to 50 at PECL_BIAS
at VCC - 2.0V
VCC -
1.825
VCC -
1.62 V
Differential Voltage VDIFF_PECL Output connected to 50 at PECL_BIAS
at VCC - 2.0V 0.595 0.710 V
Rise Time tR-PECL 20% to 80% 200 ps
Fall Time tF-PECL 80% to 20% 200 ps
Duty Cycle DCYCLE_PECL 45 55 %
Propagation Delay from OE Going
LOW to Output Three-Stated tPAZ (Figure 3) 200 ns
Propagation Delay from OE Going
HIGH to Output Active tPZA (Figure 3) 200 ns
Note 1: Limits at -40°C are guaranteed by design and are not production tested. Typical values are at +25°C and 3.3V, unless
otherwise noted.
Note 2: AC parameters are guaranteed by design and characterization and are not production tested.
Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfINITIAL + ΔfTEMP + (ΔfVCC x 0.165) + ΔfLOAD + ΔfAGING.
Note 4: Supply induced jitter is measured with a 50mVP-P sine wave forced on VCC. Deterministic jitter is calculated by measuring
the power of the resulting tone seen on a spectrum analyzer.
Note 5: Voltage referenced to ground.
SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz)
fM = 125MHz 133.33MHz 200MHz
10Hz -70 -75 -70
100Hz -100 -105 -100
1kHz -118 -121 -115
10kHz -118 -122 -117
100kHz -124 -126 -122
1MHz -142 -141 -138
10MHz -150 -150 -150
20MHz -150 -150 -150
SINGLE-SIDEBAND PHASE NOISE AT fO= fNOM
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 OE Active-High Output Enable. Has an internal pullup 100k resistor.
2 MS Margin Select. Three-level input with a 100k pulldown resistor.
3 GND Ground
4 OUTP Positive Output for LVPECL or LVDS
5 OUTN Negative Output for LVPECL or LVDS
6 VCC Supply Voltage
7–10 N.C. No Connection. Must be floated.
— EP
Exposed Paddle. The exposed pad must be used for thermal relief. This pad must be connected to
ground.
FREQUENCY vs. TEMPERATURE
DS4M125/DS4M133/DS4M200 toc01
TEMPERATURE (°C)
fOUT DEVIATION (ppm)
8060-20 0 20 40
-13
-10
-8
-5
-3
0
3
5
-15
-40
fO + 5%
fO - 5%
fO
CURRENT vs. TEMPERATURE
DS4M125/DS4M133/DS4M200 toc02
TEMPERATURE (°C)
ICC (mA)
8060-20 0 20 40
47
49
51
53
55
57
59
45
-40
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
DS4M125/DS4M133/DS4M200
Detailed Description
The DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100kΩ
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of VCC - 2.0V, while the LVDS
outputs are a logical one. The OE pin has an internal
100kΩpullup resistor. When the pin is left floating, the
device output is active.
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
6 _______________________________________________________________________________________
DIVP
DIVFB
X1
X2
THREE-
STATE
PHASE
DET
FILTER
LC-VCO
THREE-
LEVEL
DECODER
DIVOUT
OUTSELN
FREQUENCY SELECTION
OUTDRV
VCC
OE
OUTP
OUTN
MS
GND
DS4M125/
DS4M133/
DS4M200
Figure 1. Functional Diagram
OE
OUTP
tP1A tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
OE
OUTP PECL_BIAS PECL_BIAS
PECL_BIAS PECL_BIAS
OUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________
7
© 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Selector Guide
PART FREQUENCY
(NOM) (MHz)
OUTPUT
TYPE TOP MARK
DS4M125P+33 125 LVPECL MEP
DS4M125D+33 125 LVDS MED
DS4M133P+33 133.33 LVPECL MFP
DS4M133D+33 133.33 LVDS MFD
DS4M200P+33 200 LVPECL MJP
DS4M200D+33 200 LVDS MJD
+
Denotes a lead-free package. The lead finish is JESD97 cate-
gory e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes. A + appears anywhere on
the top mark.
Chip Information
SUBSTRATE CONNECTED TO GROUND
PROCESS: BiPOLAR SiGe
THETA-JA (°C/W)
90
1
2
3
6
5
4
TOP VIEW
OE
MS
N.C. N.C.
N.C. N.C.
GND
VCC
OUTN
OUTP
+
(5.00mm
×
3.20mm
×
1.49mm)
DS4M125/
DS4M133/
DS4M200
*EP
*EXPOSED PAD
Pin Configuration
Thermal Information
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 LCCC L1053+H2 21-0389
