M485L2829MT0-LA0 - Samsung Semiconductor Division

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

1GB DDR SDRAM MODULE

200pin DIMM

(128Mx72 based on stacked 128Mx8 DDR SDRAM)

72-bit ECC/Parity

Revision 0.0

Sep. 2002

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

Revision History

Revision 0.0 (Sep. 2002)

1. First release for internal usage

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

GENERAL DESCRIPTION

M485L2829MT0 200pin DDR SDRAM SODIMM

128Mx72 200pin DDR SDRAM SODIMM based on stacked 128Mx8

The Samsung M485L2829MT0 is 128M bit x 72 Double Data

Rate SDRAM high density memory modules.

The Samsung M485L2829MT0 consists of nine CMOS stacked

128M x 8bit with 4banks Double Data Rate SDRAMs in 66pin

TSOP-II (400mil) packages mounted on a 200pin glass-epoxy

substrate. three 0.1uF decoupling capacitors are mounted on

the printed circuit board in parallel for each DDR SDRAM.

The M485L2829MT0 is Dual In-line Memory Modules and

intended for mounting into 200pin edge connector sockets.

Synchronous design allows precise cycle control with the use of

system clock. Data I/O transactions are possible on both edges

of DQS. Range of operating frequencies, programmable laten-

cies and burst lengths allow the same device to be useful for a

variety of high bandwidth, high performance memory system

applications.

• Performance range

( C : Normal Power_IDD6 , L : Low Power_IDD6 )

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,400 mil, double sided component

Part No. Max Freq. Interface

M485L2829MT0-C(L)A2 133MHz(7.5ns@CL=2)

SSTL_2

M485L2829MT0-C(L)B0 133MHz(7.5ns@CL=2.5)

M485L2829MT0-C(L)A0 100MHz(10ns@CL=2)

FEATURE

PIN DESCRIPTION

* These pins are not used in this module.

Pin Name Function

A0 ~ A12 Address input (Multiplexed)

BA0 ~ BA1 Bank Select Address

DQ0 ~ DQ63 Data input/output

CB0 ~ CB7 Check bit (Data-in/Data-out)

DQS0 ~ DQS7 Data Strobe input/output

CK0~CK1

CK0~CK1 Clock input

CKE0~CKE1 Clock enable input

CS0 ~CS1 Chip select input

RAS Row address strobe

CAS Column address strobe

WE Write enable

DM0 ~ DM7 Data - in mask

VDD Power supply (2.5V)

VDDQ Power Supply for DQS(2.5V)

VSS Ground

VREF Power supply for reference

VDDSPD Serial EEPROM Power

Supply (2.3V to 3.6V)

SDA Serial data I/O

SCL Serial clock

SA0 ~ 2 Address in EEPROM

NC No connection

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

KeyKey

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

VREF

VSS

DQ0

DQ1

VDD

DQS0

DQ2

VSS

DQ3

DQ8

VDD

DQ9

DQS1

VSS

DQ10

DQ11

VDD

CK0

/CK0

VSS

DQ16

DQ17

VDD

DQS2

DQ18

VSS

DQ19

DQ24

VDD

DQ25

DQS3

VSS

DQ26

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

DQ27

VDD

CB0

CB1

VSS

*DQS8

CB2

VDD

CB3

VSS

*CK2

*/CK2

VDD

CKE1

A12

VSS

VDD

A10/AP

BA0

/WE

/CS0

DU(A13)

VSS

DQ32

DQ33

VDD

DQS4

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

DQ34

VSS

DQ35

DQ40

VDD

DQ41

DQS5

VSS

DQ42

DQ43

VDD

VSS

DQ48

DQ49

VDD

DQS6

DQ50

VSS

DQ51

DQ56

VDD

DQ57

DQS7

VSS

DQ58

DQ59

VDD

SDA

SCL

VDDSPD

VDDID

VREF

VSS

DQ4

DQ5

VDD

DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14

DQ15

VDD

VSS

DQ20

DQ21

VDD

DM2

DQ22

VSS

DQ23

DQ28

VDD

DQ29

DM3

VSS

DQ30

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/(RESET)

VSS

VDD

CKE0

DU(BA2)

A11

VSS

VDD

BA1

/RAS

/CAS

/CS1

VSS

DQ36

DQ37

VDD

DM4

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

DQ38

VSS

DQ39

DQ44

VDD

DQ45

DM5

VSS

DQ46

DQ47

VDD

/CK1

CK1

VSS

DQ52

DQ53

VDD

DM6

DQ54

VSS

DQ55

DQ60

VDD

DQ61

DM7

VSS

DQ62

DQ63

VDD

SA0

SA1

SA2

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

Functional Block Diagram

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

DM0

I/O 5

I/O 4

I/O 3

I/O 2

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

DM4

I/O 5

I/O 4

I/O 3

I/O 2

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM7

A0 - A12 A0-A12: DDR SDRAMs D0 - D8

CS0

CS CS

BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D8

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15 I/O 2

DQS

*D8 is assigned for ECC component.

* Clock Wiring

Clock

Input DDR SDRAMs

CK0/CK0

CK1/CK1

5 DDR SDRAMs

4 DDR SDRAMs

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

VSS

D0 - D8

VDD/VDDQ D0 - D8

D0 - D8

VREF

VDDSPD SPD Notes:

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms

+ 5%.

RAS RAS: DDR SDRAMs D0 - D8

CAS CAS: DDR SDRAMs D0 - D8

CKE0,1 CKE: DDR SDRAMs D0 - D8

WE WE: DDR SDRAMs D0 - D8

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 7

I/O 6

I/O 1

I/O 0

D10

I/O 5

I/O 4

I/O 3

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 7

I/O 6

I/O 1

I/O 0

D11

I/O 5

I/O 4

I/O 3

I/O 2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 7

I/O 6

I/O 1

I/O 0

D12

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DQ15 I/O 2

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 7

I/O 6

I/O 1

I/O 0

D13

I/O 5

I/O 4

I/O 3

I/O 2

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 7

I/O 6

I/O 1

I/O 0

D14

I/O 5

I/O 4

I/O 3

I/O 2

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 7

I/O 6

I/O 1

I/O 0

D15

I/O 5

I/O 4

I/O 3

I/O 2

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 7

I/O 6

I/O 1

I/O 0

D16

I/O 5

I/O 4

I/O 3

I/O 2

DQS

CS1

*Clock Net Wiring

Card

Edge

D0(D4) / D9D13)

D1(D5) / D10(D14)

D2(D6) / D11(D15)

D3(D7) / D12(D16)

D8(D17)/Cap

R=120

Ω

CK0/1

Cap/Cap

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS8

DM8

DQS

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 7

I/O 6

I/O 1

I/O 0

D17

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled

TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.

2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter Symbol Min Max Unit Note

Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7

I/O Supply voltage VDDQ 2.3 2.7 V

I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1

I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2

Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4

Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ+0.6 V 3

Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5

Input leakage current II-2 2 uA

Output leakage current IOZ -5 5 uA

Output High Current(Normal strengh driver)

;VOUT = VTT + 0.84V IOH -16.8 mA

Output High Current(Normal strengh driver)

;VOUT = VTT - 0.84V IOL 16.8 mA

Output High Current(Half strengh driver)

;VOUT = VTT + 0.45V IOH -9 mA

Output High Current(Half strengh driver)

;VOUT = VTT - 0.45V IOL 9mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD27 W

Short circuit current IOS 50 mA

Absolute Maximum Rate

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

DDR SDRAM IDD spec table

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol A2

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2) Unit Notes

IDD0 2,340 2,340 2,070 mA

IDD1 2,560 2,560 2,290 mA

IDD2P 105 105 90 mA

IDD2F 900 900 720 mA

IDD2Q 450 450 360 mA

IDD3P 900 900 720 mA

IDD3N 1,710 1,710 1,440 mA

IDD4R 2,835 2,835 2,430 mA

IDD4W 3,100 3,100 2,700 mA

IDD5 3,640 3,640 3,330 mA

IDD6 Normal 90 90 90 mA

Low power 54 54 54 mA Optional

IDD7A 5,170 5,170 4,500 mA

AC Operating Conditions

Parameter/Condition Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V 3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V 3

Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1

Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)

Parameter Value Unit Note

Input reference voltage for Clock 0.5 * VDDQ V

Input signal maximum peak swing 1.5 V

Input Levels(VIH/VIL)VREF+0.31/VREF-0.31 V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Load Circuit

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

Output Load Circuit (SSTL_2)

Output Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

RT=50Ω

Vtt=0.5*VDDQ

Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

Parameter Symbol Min Max Unit

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE )CIN1 74 pF

Input capacitance(CKE0, CKE1) CIN2 47 pF

Input capacitance( CS0, CS1 )CIN3 47 pF

Input capacitance( CLK0, CLK1) CIN4 34 pF

Input capacitance(DM0~DM8)CIN5 14 pF

Data & DQS input/output capacitance(DQ0~DQ63)COUT1 14 pF

Data input/output capacitance(CB0~CB7)COUT2 14 pF

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

AC Timming Parameters & Specifications

Parameter Symbol A2 B0 A0 Unit Note

Min Max Min Max Min Max

Row cycle time tRC 65 65 70 ns

Refresh row cycle time tRFC 75 75 80 ns

Row active time tRAS 45 120K 45 120K 48 120K ns

RAS to CAS delay tRCD 20 20 20 ns

Row precharge time tRP 20 20 20 ns

Row active to Row active delay tRRD 15 15 15 ns

Write recovery time tWR 15 15 15 ns

Last data in to Read command tWTR 1 1 1 tCK

Col. address to Col. address delay tCCD 1 1 1 tCK

Clock cycle time CL=2.0 tCK 7.51210121012ns5

CL=2.5 7.5 12 7.5 12 ns 5

Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

DQS-out access time from CK/CK tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Output data access time from CK/CK tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Data strobe edge to ouput data edge tDQSQ - 0.5 - 0.5 - 0.6 ns 5

Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS-in setup time tWPRES 0 0 0 ns 2

DQS-in hold time tWPRE 0.25 0.25 0.25 tCK

DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK

DQS-in high level width tDQSH 0.35 0.35 0.35 tCK

DQS-in low level width tDQSL 0.35 0.35 0.35 tCK

DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Address and Control Input setup time(fast) tIS 0.9 0.9 1.1 ns 6

Address and Control Input hold time(fast) tIH 0.9 0.9 1.1 ns 6

Address and Control Input setup time(slow) tIS 1.0 1.0 1.1 ns 6

Address and Control Input hold time(slow) tIH 1.0 1.0 1.1 ns 6

Data-out high impedence time from CK/CK tHZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Data-out low impedence time from CK/CK tLZ -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

Input Slew Rate(for input only pins) tSL(I) 0.5 0.5 0.5 V/ns 6

Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7

Output Slew Rate(x4,x8) tSL(O) 1.0 4.5 1.0 4.5 1.0 4.5 V/ns 10

Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

1. Maximum burst refresh cycle : 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

4. A write command can be applied with tRCD satisfied after this command.

5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period

jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.

6. Input Setup/Hold Slew Rate Derating

This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

7. I/O Setup/Hold Slew Rate Derating

This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate

based on the lesser of AC-AC slew rate and DC-DC slew rate.

Parameter Symbol A2 B0 A0 Unit Note

Min Max Min Max Min Max

Mode register set cycle time tMRD 15 15 16 ns

DQ & DM setup time to DQS tDS 0.5 0.5 0.6 ns 7,8,9

DQ & DM hold time to DQS tDH 0.5 0.5 0.6 ns 7,8,9

Control & Address input pulse width tIPW 2.2 2.2 2.5 ns

DQ & DM input pulse width tDIPW 1.75 1.75 2 ns

Power down exit time tPDEX 7.5 7.5 10 ns

Exit self refresh to non-Read command tXSNR 75 75 80 ns 4

Exit self refresh to read command tXSRD 200 200 200 tCK

Refresh interval time tREFI 7.8 7.8 7.8 us 1

Output DQS valid window tQH tHP

-tQHS -tHP

-tQHS -ns5

Clock half period tHP tCLmin

or tCHmin -tCLmin

or tCHmin -ns

Data hold skew factor tQHS 0.75 0.75 0.8 ns

DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 3

Active to Read with Auto precharge

command tRAP 20 20 20

Autoprecharge write recovery +

Precharge time tDAL

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

tCK 11

Input Setup/Hold Slew Rate ∆tIS ∆tIH

(V/ns) (ps) (ps)

0.5 0 0

0.4 +50 +50

0.3 +100 +100

I/O Setup/Hold Slew Rate ∆tDS ∆tDH

(V/ns) (ps) (ps)

0.5 0 0

0.4 +75 +75

0.3 +150 +150

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

8. I/O Setup/Hold Plateau Derating

This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of

up to 2ns.

9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate

is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall

Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.

10. This parameter is fir system simulation purpose. It is guranteed by design.

11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

I/O Input Level ∆tDS ∆tDH

(mV) (ps) (ps)

± 280 +50 +50

Delta Rise/Fall Rate ∆tDS ∆tDH

(ns/V) (ps) (ps)

000

±0.25 +50 +50

±0.5 +100 +100

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.

CK slew rate

(Single ended)

∆tIH/tIS

(ps)

∆tDSS/tDSH

(ps)

∆tAC/tDQSCK

(ps)

∆tLZ(min)

(ps)

∆tHZ(max)

(ps)

1.0V/ns 00000

0.75V/ns +50 +50 +50 -50 +50

0.5V/ns +100 +100 +100 -100 +100

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9

A11, A12 Note

Refresh

Auto Refresh HHLL LH X 3

Self

Refresh

Entry L 3

Exit L H LH HH X3

HX XX 3

Bank Active & Row Addr. H X L L H H V Row Address

Read &

Column Address

Auto Precharge Disable HXLHLHV

LColumn

Address

(A0~A9,A11)

Auto Precharge Enable H 4

Write &

Column Address

Auto Precharge Disable HXLHLLV

LColumn

Address

(A0~A9,A11)

Auto Precharge Enable H 4, 6

Burst Stop H X L H H L X 7

Precharge Bank Selection HXLLHL

VL X

All Banks X H 5

Active Power Down Entry H L HX XX

XLV VV

Exit L H X X X X

Precharge Power Down Mode

Entry H L HX XX

LH HH

Exit L H HX XX

LV VV

DM H X X 8

No operation (NOP) : Not defined H X HX X X X9

LH HH 9

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 0.0 Sep. 2002

M485L2829MT0 200pin DDR SDRAM SODIMM

Tolerances : ±.006(.15) unless otherwise specified

The used device is stacked 128Mx8 DDR SDRAM, TSOP2

DDR SDRAM Part No. : K4H1G0738M - TC/L

PACKAGE DIMENSIONS

2.70

2.50

Units : Inches (Millimeters)

Full R 2x

0.17

(4.20)

0.456

11.40

1.896

(47.40)

0.24

(6.0)

0.086

0.79

(20.00)

2.15

(63.60)

(67.60)

Detail Z

0.16 ± 0.0039

(4.00 ± 0.10)

0.04 ± 0.0039

(1.00 ± 0.1)

2-φ 0.07

(1.80)

1.40

(35.56)

0.16 ± 0.039

(4.00 ± 0.10)

0.096

(2.40)

0.07

(1.8)

0.024 TYP

0.018 ± 0.001

0.01

(0.25)

(0.45 ± 0.03)

(0.60 TYP)

0.102 Min

(2.55 Min)

Detail Y

0.098

2.45

Z Y

199

200

39 41

0.268 Max

0.04 ± 0.0039

(1.00 ± 0.10)

(6.81 Max)

(4.00)

(0.157)