LTC4417HGN#PBF - LINEAR TECHNOLOGY

LTC4417

4417f

Typical applicaTion

FeaTures DescripTion

Prioritized PowerPath™

Controller

The LT C

4417 connects one of three valid power supplies

to a common output based on priority. Priority is defined

by pin assignment, with V1 assigned the highest priority

and V3 the lowest priority. A power supply is defined as

valid when its voltage has been within its overvoltage (OV)

and undervoltage (UV) window continuously for at least

256ms. If the highest priority valid input falls out of the

OV/UV window, the channel is immediately disconnected

and the next highest priority valid input is connected to the

common output. Tw o or more LTC4417s can be cascaded

to provide switchover between more than three inputs.

The LTC4417 incorporates fast non-overlap switching

circuitry to prevent both reverse and cross conduction

while minimizing output droop. The gate driver includes

a 6V clamp to protect external MOSFETs. A controlled

output ramp feature minimizes start-up inrush current.

Open drain VALID outputs indicate the input supplies have

been within their OV/UV window for 256ms.

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

PowerPath, ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

Priority Switching from 12V V1 to 14.8V V2

applicaTions

n Selects Highest Priority Supply from Three Inputs

n Blocks Reverse and Cross Conduction Currents

n Wide Operating Voltage Range: 2.5V to 36V

n –42V Protection Against Reverse Battery

Connection

n Fast Switchover Minimizes Output Voltage Droop

n Low 28µA Operating Current

n <1µA Current Draw from Supplies Less than VOUT

n 1.5% Input Overvoltage/Undervoltage Protection

n Adjustable Overvoltage/Undervoltage Hysteresis

n P-Channel MOSFET Gate Protection Clamp

n Cascadable for Additional Input Supplies

n 24-Lead Narrow SSOP and 4mm × 4mm QFN

Packages

n Industrial Handheld Instruments

n High Availability Systems

n Battery Backup Systems

n Servers and Computer Peripherals

IRF7324

VS1

VOUT

VALID1

VALID2

VALID3

V1: 12V

WALL ADAPTER 2A

OUTPUT

V2: 14.8V Li-Ion

MAIN/SWAPPABLE

V3: 12V SLA

BACKUP

UV1

OV1

806k

1M 1M 1M

39.2k

60.4k

UV2

OV2

1.05M

31.6k

68.1k

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA01a

698k

16.9k

49.9k

G1 VS2 VS3G2

GND

LTC4417

V3 = 0V, IL = 2A

CL = 120µF

50ms/DIV 4417 TA01b

2V/DIV

VOUT

V1 UV FAULT

14.8V

12V

14.8V

LTC4417

4417f

absoluTe MaxiMuM raTings

Supply Voltages

V1, V2, V3 ............................................... –42V to 42V

VOUT, VS1, VS2, VS3 .............................. –0.3V to 42V

Voltage from V1, V2, V3 to VOUT ................. –84V to 42V

Voltage from VS1, VS2, VS3 to

G1, G2, G3 ..................................................–0.3V to 7.5V

Input Voltages

EN, SHDN .............................................. –0.3V to 42V

OV1, OV2, OV3, UV1, UV2, UV3 ............... –0.3V to 6V

HYS ......................................................... –0.3V to 1V

Input Currents

OV1, OV2, OV3, UV1, UV2, UV3, HYS ............... –3mA

Output Voltages

VALID1, VALID2, VALID3 ........................ –0.3V to 42V

CAS .......................................................... –0.3V to 6V

Output Currents

VALID1, VALID2, VALID3, CAS .............................2mA

Operating Ambient Temperature Range

LTC4417C ................................................ 0°C to 70°C

LTC4417I..............................................–40°C to 85°C

LTC4417H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature

GN Package (Soldering, 10 sec) ........................300°C

(Notes 1, 2)

TOP VIEW

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

SHDN

HYS

UV1

OV1

UV2

OV2

UV3

OV3

VALID1

VALID2

VALID3

VS1

VS2

VS3

VOUT

CAS

GND

TJMAX = 150°C, θJA = 85°C/W, θJC = 30°C/W

24 23 22 21 20 19

789

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

10 11 12

UV1

OV1

UV2

OV2

UV3

OV3

VS1

VS2

VS3

HYS

SHDN

VALID1

VALID2

VALID3

GND

CAS

VOUT

TJMAX = 150°C, θJA = 47°C/W, θJC = 4.5°C/W

EXPOSED PAD (PIN 25) PCB GND CONNECTION OPTIONAL

pin conFiguraTion

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4417CGN#PBF LTC4417CGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP 0°C to 70°C

LTC4417IGN#PBF LTC4417IGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 85°C

LTC4417HGN#PBF LTC4417HGN#TRPBF LTC4417GN 24-Lead Narrow Plastic SSOP –40°C to 125°C

LTC4417CUF#PBF LTC4417CUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C

LTC4417IUF#PBF LTC4417IUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C

LTC4417HUF#PBF LTC4417HUF#TRPBF 4417 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LT C Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4417

4417f

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted,

V1 = V2 = V3 = VOUT = 12V, HYS = GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Start-Up

V1-V3,VOUT V1 to V3,VOUT Operating Supply Range l2.5 36 V

IV1-V3,VOUT(EN) Total Supply Current with Channels Enabled V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V,

(Notes 3, 4)

l28 78 µA

IV1-V3(EN)Total Supply Current with Channels Disabled V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V,

(Notes 3, 4)

l31 93 µA

IV1-V3(SHDN)Total Supply Current When Shutdown V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = SHDN =

0V, (Notes 3, 4)

l15.4 84 µA

IVOUT VOUT Supply Current V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V l14 30 µA

IPRIORITY Current from Highest V1 to V3 Priority Input

Source (V1)

V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V

V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V

2.6

µA

IHIGHEST Current from Highest V1 to V3 Voltage Input

Source

V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V,

(Note 3, 4)

l11 72 µA

V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = EN = 0V,

SHDN = 0V, (Note 3, 4)

l15 80 µA

ILOWER Current from V1 to V3 Input Voltage Sources

Lower than VOUT

V1 = 5V, V2 = 12V, V3 = 2.5V, VOUT = 4V

Not Highest Valid Priority

–5 0.2 1 µA

Gate Control

∆VGOpen (VS – VG) Clamp Voltage VOUT = 11V, G1 to G3 = Open l5.4 6.2 6.7 V

∆VG(SOURCE) Sourcing (VS – VG) Clamp Voltage VOUT = 11V, I = –10µA l5.8 6.6 7 V

∆VG(SINK) Sinking (VS – VG) Clamp Voltage VOUT = 11V, I = 10µA l4.5 5.2 6 V

∆VG(OFF) G1 to G3 Off (VS – VG) Threshold V1 = V2 = V3 = 2.8V, VOUT = 2.6V, G1 to G3

Rising Edge

l0.12 0.35 0.6 V

∆VG(SLEW,ON) G1 to G3 Pull-Down Slew Rate VOUT = 11V, CGATE = 10nF (Note 5) l4 9 20 V/µs

∆VG(SLEW,OFF) G1 to G3 Pull-Up Slew Rate VOUT = 11V, CGATE = 10nF (Note 6) l7.5 13 22 V/µs

IG(DN) G1 to G3 Low Pull-Down Current VOUT = 2.6V, V1 to V3 = 2.8V, (G1 to G3) = ∆VG

+ 300mV

0.8 2 7 µA

RG(OFF) G1 to G3 OFF Resistance VOUT = 4V, V1 to V3 = 5V, IG = –10mA l9 16 26 Ω

VREV Reverse Voltage Threshold Measure (V1 to V3) – VOUT, VOUT Falling l30 120 200 mV

tG(SWITCHOVER) Pin Break-Before-Make Time VOUT = 11V, CGATE = 10nF, (Note 7) l0.7 2 3 µs

tpG(SHDN)G1 to G3 Turn-Off Delay From SHDN VOUT = 11V, Falling Edge SHDN to

(G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF

l20 50 100 µs

tpG(EN,OFF) G1 to G3 Turn-Off Delay From EN VOUT = 11V, Falling EN Edge to

(G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF

l0.3 0.7 1.4 µs

tpG(EN,ON) G1 to G3 Turn-On Delay From EN VOUT = 11V, Rising EN Edge to

(G1 to G3) = (VS1 to VS3) – 3V, CGATE = 10nF

l1 1.4 2 µs

LTC4417

4417f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

specified.

Note 3: Each V1 to V3 supply current specification includes current into

the corresponding VS1 to VS3 for the channel(s) being tested.

Note 4: Specification represents the total diode-ORed current of V1 to V3

input supplies, selecting the highest voltage as the input source. If two

input supplies are similar in voltage and higher than the remaining input

supply voltage, the current is split evenly between the two higher voltage

supplies. Current is split evenly if all supplies are equal.

Note 5: Falling edge of G1 to G3 measured from 11V to 8V.

Note 6: Rising edge of G1 to G3 measured from 7V to 11V.

Note 7: UV1 driven below VOV,UV(THR). Time is measured from respective

rising edge G1 to G3 crossing (VS1 to VS3) – 3V to next valid priority

falling edge G1 to G3 crossing (VS1 to VS3) – 3V.

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. For all tests, V1 = VS1, V2 = VS2, V3 = VS3. Unless otherwise noted,

V1 = V2 = V3 = VOUT = 12V, HYS = GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input/Output Pins

VVALID(OL) VALID1 to VALID3 Output Low Voltage I = 1mA, (V1 to V3) = 2.5V, VOUT = 0V l0.25 0.55 V

tpVALID(OFF) VALID1 to VALID3 Delay OFF From OV/UV Fault l5 8 13 µs

VCAS(OH) CAS Output High Voltage I = –1µA l1.4 2 3 V

VCAS(OL) CAS Output Low Voltage I = 1mA l0.2 0.4 V

ICAS CAS Pull-Up Current SHDN = 0V, CAS = 1V l–6 –20 –40 µA

tpCAS(EN) CAS Delay from VG(OFF) VOUT = 11V l0.4 0.7 1.3 µs

VEN(THR) EN Threshold Voltage EN Rising l 0.6 1 1.4 V

VSHDN(THR) SHDN Threshold Voltage SHDN Rising l 0.4 0.8 1.2 V

VSHDN_EN(HYS) SHDN, EN Threshold Hysteresis 100 mV

ISHDN_EN SHDN, EN Pull-Up Current SHDN = EN = 0V l–0.5 –2 –5 µA

ILEAK SHDN, EN, VALID1 to VALID3, CAS Leakage

Current

SHDN = EN = (VALID1 to VALID3) = 36V,

CAS = 5.5V

l±1 µA

OV, UV Protection Circuitry

VOV_UV(THR) OV1 to OV3, UV1 to UV3 Comparator Threshold VOUT = 11V, OV1 to OV3 Rising, UV1 to UV3

Falling

l0.985 1 1.015 V

VOV_UV(HYS) OV1 to OV3, UV1 to UV3 Comparator

Hysteresis

VOUT = 11V l15 30 45 mV

IUV_OV(LEAK) OV1 to OV3, UV1 to UV3 Leakage Current OV1 to OV3 = 1.015V, UV1 to UV3 = 0.985V l±20 nA

IOV_UV(MIN) Minimum External Hysteresis Current IHYS = –400nA l35 50 75 nA

IOV_UV(MAX) Maximum External Hysteresis Current IHYS = –4µA l420 520 620 nA

VHYS HYS Voltage IHYS = –4µA l470 495 520 mV

tVALID V1 to V3 Validation Time 100 256 412 ms

LTC4417

4417f

Typical perForMance characTerisTics

ΔVG vs Temperature

Gate Falling Slew Rate

vs Temperature

Gate Rising Slew Rate

vs Temperature

IG(DN) vs Temperature Switchover Time vs Temperature

Valid Delay Off Time

vs Temperature

Total Shutdown Supply Current

vs Supply Voltage

Total Enabled Supply Current

vs Supply Voltage IV1-V3,VOUT(EN) vs Supply Voltage

SUPPLY VOLTAGE (V)

TOTAL ENABLE SUPPLY CURRENT (µA)

010 20 30

4417 G02

ALL SUPPLY, VS AND VOUT

PINS CONNECTED TOGETHER

SUPPLY VOLTAGE (V)

TOTAL SHUTDOWN SUPPLY CURRENT (µA)

010 20 30

4417 G01

ALL SUPPLY AND VS PINS CONNECTED

TOGETHER, VOUT = 0V

TEMPERATURE (°C)

–50

∆V

(V)

6.40

6.35

6.25

6.30

6.20

6.10

6.15

6.05

6.00 0 50–25 25 100

4417 G04

12575

TEMPERATURE (°C)

–50

G(DN)

(µA)

3.0

2.5

1.5

2.0

1.0

0.5

00 50–25 25 100

4417 G07

12575

TEMPERATURE (°C)

–50

tG(SWITCHOVER) (µs)

3.0

2.5

1.5

2.0

1.0

0.5

00 50–25 25 100

4417 G08

12575

TEMPERATURE (°C)

–50

VALID DELAY TIME (µs)

8.5

8.4

8.2

8.3

8.1

7.9

8.0

7.8

7.7 0 50–25 25 100

4417 G09

12575

TEMPERATURE (°C)

–50

GATE FALLING SLEW RATE (V/µs)

00 50–25 25 100

4417 G05

12575

V1 = 2.7V

V1 = 5V

V1 = 12V

V1 = 36V

CGATE = 10nF

V1 = V2 = V3

V1 = 24V

TEMPERATURE (°C)

–50

GATE RISING SLEW RATE (V/µs)

00 50–25 25 100

4417 G06

12575

V1 = 2.7V

V1 = 5V

V1 = 12V, 24V, 36V

V1 = V2 = V3

CGATE = 10nF

V2 = VS2 VOLTAGE (V)

V1-V3,VOUT(EN)

(µA)

010 20 30

4417 G03

V1 = VS1 = 5V

V2 = VS2

V3 = VS3 = 2.8V

VOUT = 4.9V

LTC4417

4417f

Typical perForMance characTerisTics

VOUT Switching from Higher to

Lower Voltage

VOUT Switching from Lower to

Higher Voltage with Slew Rate

Control Circuitry Reverse Voltage Blocking

VVALID(OL) vs Pull-Up Current VOV,UV vs Temperature Deglitched Connection

pin FuncTions

CAS: Cascade Output. Digital output used for cascad-

ing multiple LTC4417s. Connect CAS to EN of another

LTC4417 to increase the number of multiplexed input

supplies. CAS is pulled up to the internal VLDO voltage

by an internal 20µA current source to indicate when all

inputs are invalid, the external P-channel MOSFETs are

determined to be off, and EN is above 1V. CAS also pulls

high when SHDN is driven below 1V. CAS is pulled low

when any input supply is within the OV/UV window for at

least 256ms and both SHDN and EN are above 1V. CAS

also pulls low when EN is driven below 1V. CAS can be

driven to 5.5V independent of the input supply voltages.

Leave open if not used.

EN: Channel Enable Input. EN is a high voltage input that

allows the user to quickly connect and disconnect chan-

nels without resetting the OV/UV timers. When below 1V,

all external back-to-back P-channel MOSFETs are driven

off by pulling G1, G2 and G3 to their respective VS1, VS2

and VS3. When above 1V, the highest valid priority chan-

nel is connected to the output. EN is pulled to the internal

VLDO voltage with a 2µA current source and can be pulled

up externally to a maximum voltage of 36V. Leave open

when not used.

Exposed Pad (UF Package Only): Exposed pad may be

left open or connected to device ground.

PULL-UP CURRENT (mA)

VVALID(OL) (V)

0.5

0.4

0.2

0.3

0.1

00.5 1.0 1.5

4417 G10

2.0

TEMPERATURE (°C)

–50

OV,UV

(V)

1.04

1.03

1.01

1.02

1.00

0.98

0.99

0.97

0.96 0 50–25 25 100

4417 G11

12575

VUV(RISING)

VOV(FALLING)

VOV,UV(THR)

CL = 122µF

IL = 1A

–40V PCH FDD4685

100ms/DIV 4417 G12

2V/DIV

VOUT

V1 = –20V

V1 = 20V

CL = 122µF

IL = 1A

–40V PCH FDD4685

5µs/DIV 4417 G15

V2, VOUT

10V/DIV

CL = 122µF

IL = 1A

–40V PCH FDD4685

100µs/DIV 4417 G13

2V/DIV

VOUT

2V/DIV

IVOUT

5A/DIV

RS = 1.43kΩ

CS = 6.8nF

CL = 100µF

IL = 1A

–40V PCH FDD4685

20µs/DIV 4417 G14

VOUT

LTC4417

4417f

pin FuncTions

G1, G2, G3: P-Channel MOSFET Gate Drive Outputs. G1,

G2 and G3 are used to control external back-to-back P-

channel MOSFETs. When driven low, G1, G2 and G3 are

clamped 6V below their corresponding VS1, VS2 and VS3.

Connect G1, G2 and G3 to external P-channel MOSFET

gate pins. See Dual Channel Applications Section for con-

necting unused channels.

GND: Device Ground.

HYS: OV/UV Comparator Hysteresis Input. Connecting HYS

to ground sets a fixed 30mV hysteresis for the OV and UV

comparators. Connecting a resistor, RHYS, between HYS

and ground disables the internal 30mV hysteresis and sets

a 63mV/RHYS hysteresis current which is sourced from

each OV1, OV2 and OV3 and sunk into each UV1, UV2 and

UV3 pin. Connect to ground when not used.

OV1, OV2, OV3: Overvoltage Comparator Inputs. Rising

voltages above 1V signal an over voltage event, invalidating

the respective input supply channel. Connect OV1, OV2 and

OV3 to an external resistive divider from its respective V1,

V2 and V3 to achieve the desired overvoltage threshold.

The comparator hysteresis can be set to an internally fixed

30mV or set externally via the HYS pin. Connect unused

pins to ground.

SHDN: Shutdown Input. Driving SHDN below 0.8V turns

off all external back-to-back P-channel MOSFET devices,

forces the LTC4417 into a low current state, and resets

the 256ms timers used to validate V1, V2 and V3. Driving

SHDN above 0.8V allows channels to validate and connect.

SHDN is pulled high to the internal VLDO voltage with a

2µA current source and can be pulled up externally to a

maximum voltage of 36V. Leave open when not used.

UV1, UV2, UV3: Undervoltage Comparator Inputs. Falling

voltages below 1V signal an undervoltage event, invalidat-

ing the respective input supply channel. Connect UV1, UV2

and UV3 through a resistive divider between the respec-

tive V1, V2 and V3 and ground to achieve the desired

undervoltage threshold. The comparator hysteresis can

be set to an internally fixed 30mV or set externally via the

HYS pin. Connect pins from unused channels to ground.

V1: Highest Priority Input Supply. When V1 is within its user

defined OV/UV window for 256ms, it is connected to VOUT

via its external back-to-back P-channel MOSFETs. Connect

V1 to ground when channel is not used. See Applications

Information for bypass capacitor recommendations.

V2: Second Priority Input Supply. When V2 is within its

OV/UV window for 256ms, it is connected to VOUT via

its external back-to-back P-channel MOSFETs only if V1

does not meet its OV/UV requirements. Connect to ground

when channel is not used. See Applications Information

for bypass capacitor recommendations.

V3: Third Priority Input Supply. When V3 is within its OV/UV

window for 256ms, it is connected to VOUT via its external

back-to-back P-channel MOSFETs only if V1 and V2 do

not meet their OV/UV requirements. Connect to ground

when channel is not used. See Applications Information

for bypass capacitor recommendations.

VALID1, VALID2, VALID3: Valid Channel Indicator Outputs.

VALID1, VALID2 and VALID3 are high voltage open drain

outputs that pull low when the respective V1, V2 and V3 are

within the OV/UV window for at least 256ms and release

when the respective V1, V2 and V3 are outside the OV/

UV window. Connect a resistor between VALID1, VALID2

and VALID3 and a desired supply, up to a maximum of

36V, to provide the pull-up. Leave open when not used.

VS1, VS2, VS3: External P-Channel MOSFET Common

Source Connection. VS1, VS2 and VS3 supply the higher

voltage of V1, V2 and V3 or VOUT to the gate drivers.

Connect VS1, VS2 and VS3 to the respective common

source connection of the back-to-back P-channel MOS-

FETs. Connect to ground when channel is not used. See

Applications Information section for bypass capacitor

recommendations.

VOUT: Output Voltage Supply and Sense. VOUT is an output

voltage sense pin used to prevent any input supply from

connecting to the output if the output voltage is not at

least 120mV below the input supply voltage. During nor-

mal operation, VOUT powers most of the internal circuitry

when its voltage exceeds 2.4V. Connect VOUT to the output.

See Applications Information section for bypass capacitor

recommendations.

LTC4417

4417f

FuncTional block DiagraM

–

LDO

PRIORITIZER

HIGHEST VALID PRIORITY

VBLDO

VOUT

VBLDO

SHDN

ISHDN

2µA

SHDN

V3V2V1

LDO

SHDN

VLDO

VBEST

V1 P2

2.4V

PRIORITIZED

NONOVERLAP

CONTROL

LOGIC

VBESTGEN

–

VS1

350mV

120mV

GATE

DRIVER

REV

VGS

VS1

VLDO

BANDGAP

UVLO

GND

CAS

VLDO

ICAS

20µA

–

HYS

IEN

2µA

0.24V

0.5V

VLDO

ILIM

5µA

VLDO

CURRENT SENSE/8

–

VLDO

–

VLDO

IHYS/8

VLDO

HYS

–

OTA 30mV

256ms

TIMER

EXTERNAL

HYS

HYSTERESIS

CH1

VALID

UV1

UV2

UV3

OV1

OV2

OV3

CHANNEL 1

VALID1

VALID2

VALID3

–

CHANNEL 2

CHANNEL 3

+–

–

VS1

VS2

VS3

DZ1

6.2V

4417 BD

+–

LTC4417

4417f

TiMing DiagraM

tVALID tpVALID(OFF) tpG(EN,OFF) tpG(EN,ON) tpG(SHDN)

4417 TD

tG(SWITCHOVER)

UV2

UV1

SHDN

VALID2

VALID1

LTC4417

4417f

operaTion

The Functional Block Diagram displays the main functional

blocks of this device. The LTC4417 connects one of three

power supplies to a common output, VOUT, based on user

defined priority. Connection is made by enhancing external

back-to-back P-channel MOSFETs. Unlike a diode-OR,

which always passes the highest supply voltage to the

output, the LTC4417 lets one use a lower voltage supply

for primary power and a higher voltage supply as second-

ary or backup power.

During normal operation the LTC4417 continuously moni-

tors V1, V2 and V3 through its respective OV1, OV2 and OV3

and UV1, UV2 and UV3 pins using precision overvoltage

and undervoltage comparators. The highest priority input

supply whose voltage is within its respective OV/UV window

for at least 256ms is considered valid and is connected to

VOUT through external back-to-back P-channel MOSFETs.

VALID1, VALID2 and VALID3 pull low to indicate when the

V1, V2 and V3 input supplies are valid.

Hysteresis on the OV and UV threshold is adjustable.

Connecting a resistor, RHYS, between HYS and ground

forces 63mV/RHYS current to flow out of OV1, OV2 and

OV3 and into UV1, UV2 and UV3 to create hysteresis when

outside their respective OV/UV windows. Connecting HYS

to ground sets the OV and UV comparator hysteresis to

30mV. See the Application Information for more details.

During channel transitions, monitoring circuitry prevents

cross conduction between input channels and reverse con-

duction from VOUT using a break-before-make architecture.

The VGS comparator monitors the disconnecting channel’s

gate pin voltage (G1, G2 or G3). When the gate voltage is

350mV from its common source connection (VS1, VS2 or

VS3), the VGS comparator latches the output to indicate

the channel is off and allows the next valid priority input

supply to connect to VOUT, preventing cross conduction

between channels. The latch is reset when the channel is

turned on.

To prevent reverse conduction from VOUT to V1, V2 and V3

during channel switchover, the REV comparator monitors

the connecting input supply (V1, V2 or V3) and output

voltage (VOUT). The REV comparator delays the connection

until the output voltage droops lower than the input voltage

by the reverse current blocking threshold of 120mV. The

output of the REV comparator is latched, resetting when

its respective channel is turned off.

The LTC4417 gate driver pulls down on G1, G2 and

G3 with a strong P-channel source follower and a 2µA

current source. When the clamp voltage is reached, the

P-channel source follower is back biased, leaving the

2µA current source to hold G1, G2 and G3 at the clamp

voltage. To minimize inrush current at start-up, the gate

driver soft-starts the first input supply to connect VOUT,

at a rate of around 5V/ms terminating when any channel

disconnects or 32ms has elapsed. Once slew rate control

has terminated, the gate driver quickly turns on and off

external back-to-back P-channel MOSFETs as needed. A

SHDN low to high transition or VOUT drooping below 0.7V

reactivates soft-start.

When EN is driven above 1V the highest valid priority

input supply is connected to VOUT. The high voltage EN

comparator disconnects all channels when EN is driven

below 1V. The LTC4417 continues to monitor the OV and

UV pins and reflects the current input supply status with

VALID1, VALID2 and VALID3. When four or more sup-

plies need to be prioritized, connect the higher priority

LTC4417’s CAS to the lower priority LTC4417’s EN. If

VOUT is allowed to fall below 0.7V, the next connecting

input supply is soft-started.

The high voltage SHDN comparator forces the LTC4417 into

a low current state when SHDN is forced below 0.8V. While

in the low current state, all channels are disconnected, OV

and UV comparators are disabled, and all 256ms timers

are reset. When SHDN transitions from low to high, the

first validated input to connect to VOUT is soft-started.

Tw o separate internal power rails ensure the LTC4417 is

functional when one or more input supply is present and

above 2.3V. VBESTGEN generates a VBLDO rail from the

highest V1, V2 and V3 and VOUT voltage. VBLDO powers

the UVLO, bandgap, and VOUT comparator. The internal

VLDO powers all other circuits from VOUT provided VOUT is

greater than 2.4V. If VOUT is less than 2.3V, VLDO powers

all other circuits from the highest priority supply available.

If all sources are invalid or the LTC4417 is shut down,

VLDO connects to VBLDO.

LTC4417

4417f

applicaTions inForMaTion

INTRODUCTION

The LTC4417 is an intelligent high voltage triple load switch

which automatically connects one of three input supplies

to a common output based on predefined pin priorities

and validity. V1 is defined to be the highest priority and

V3 the lowest priority, regardless of voltage. An input

supply is defined valid when the voltage remains in the

user defined overvoltage (OV) and undervoltage (UV)

window for at least 256ms.

If a connected input supply falls out of the user defined

OV/UV window and remains outside the OV/UV window

for at least 8µs, the channel is disconnected and the next

highest valid priority is connected to the common output.

If a lower priority input supply is connected to VOUT and a

higher priority input supply becomes valid, the LTC4417

disconnects the lower priority supply and connects the

higher priority input supply to VOUT.

Typical LTC4417 applications are systems where predict-

able autonomous load control of multiple input supplies is

desired. These supplies may not necessarily be different

in voltage, nor must the highest voltage be the primary

supply. A typical LTC4417 application circuit is shown in

Figure 1. External component selection is discussed in

detail in the following sections.

VS1

V1 VOUT

3.3V

VALID1

VALID2

VALID3

12V WALL

ADAPTER

CIN1

2200µF

7.4V Li-Ion

PRIMARY

BATTERY

UV1

OV1

806k

39.2k

60.4k

931k

63.4k

137k

931k

63.4k

137k

R10

R11

R12

PRIMARY INVALID

SECONDARY INVALID

ADAPTER

INVALID

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 F01

G1 VS2 VS3G2

CVS3

0.1µF

GND

LTC4417

IRF7324

M5 M6

IRF7324

M3 M4

IRF7324

M1 M2

CVS2

0.1µF

CVS1

0.1µF

CV1

0.1µF

CV2

0.1µF

CV3

0.1µF

+CL

100µF

VOUT

7.4V Li-Ion

SECONDARY

BATTERY

+LTC3690

SWITCHING

REGULATOR

Figure 1. Typical Hand Held Computer Application.

LTC4417

4417f

IHYS/8

UV1

V1 INPUT

SUPPLY

LTC4417

1V VALID1

HYS

4417 F03

IHYS

RHYS

124k

1.24M

UV1

VALID

OV1

R3R7

UV1

GND

IHYS/8

VLDO

DUAL-

RESISTIVE

CONNECTION

–

OV1

VALID

VOUT

–

256ms

TIMER

OV1

UV1

T-RESISTIVE

CONNECTION

OPTIONAL INDEPENDENT

HYSTERESIS

R10

R11

OV1

R12

applicaTions inForMaTion

Figure 2. OV and UV Thresholds and Hysteresis Voltage

DEFINING OPERATIONAL RANGE

To guard against noise and transient voltage events during

live insertion, the LTC4417 requires an input supply remain

in the OV/UV window for at least 256ms to be valid. The

OV/UV window for each input supply is set by a resistive

divider (for example, R1, R2 and R3 for V1 input supply)

connected from the input supply to GND, as shown in

Figure 1. When setting the resistive divider values for the

OV and UV input supply threshold, take into consideration

the tolerance of the input supply, 1.5% error in the OV

and UV comparators, tolerance of R1, R2 and R3, and the

±20nA maximum OV/UV pin leakage currents.

In addition to tolerance considerations, hysteresis reduces

the valid input supply operating range. Input supplies will

need to be within the reduced input supply operating range

to validate. Referring to Figure 2, V1 supply voltage must

be greater than UVHYS to exit the UV fault. If an OV fault

occurs, the V1 supply voltage must return to a voltage

lower than the OVHYS voltage to exit the OV fault.

REDUCED

OPERATING

WINDOW

OV/UV

WINDOW

4417 F02

UV1 FAULT

OV1 FAULT

V1 VALID

OVHYS

UVHYS

Hysteresis for the OV and UV comparators are set via the

HYS pin. Two options are available. Connecting a resistor,

RHYS, between HYS and GND, as shown in Figure 3, sets

the hysteresis current IOV_UV(HYS) that is sunk into UV1,

UV2 and UV3 and sourced out of OV1, OV2 and OV3. The

value of RHYS is calculated with Equation (1). Choose RHYS

to limit the hysteresis current to between 50nA and 500nA.

RHYS =63mV

IOVUV(HYS)

(1)

where 50nA ≤ IOVUV(HYS) ≤ 500nA

Figure 3. LTC4417 External Hysteresis

Independent OV and UV hysteresis values are available

by separating the single string resistive dividers R1, R2

and R3, shown in Figure3, into two resistive strings, R4-

R5 and R6-R7. In such a configuration, the top resistor

defines the amount of hysteresis and the bottom resistor

defines the threshold. Use Equations (2) and (3) to cal-

culate the values.

RTOP =HYST

IOVUV(HYS)

(2)

where HYST is the desired hysteresis voltage at V1.

RBOTTOM =RTOP

OV/ UV Threshold

( )

– 1

(3)

When large independent hysteresis voltages are required,

a resistive T structure can be used to define hysteresis

values, also shown in Figure 3. After the desired OV and

UV thresholds are set with resistors R8 through R10, R11

and R12 are calculated using:

R11=R8 •OV

HYS – IOVUV(HYS) •(R9+R10)

⎡

⎣⎤

⎦

IOVUV(HYS) •(R8 +R9+R10)

(4)

R12 =(R8+R9) •UV

HYS – IOVUV(HYS) •R10

⎡

⎣⎤

⎦

IOVUV(HYS) •(R8+R9+R10)

(5)

where OVHYS, UVHYS are the desired OV and UV hysteresis

voltage magnitudes at V1 through V3, and IOVUV(HYS) is

the programmed hysteresis current.

LTC4417

4417f

applicaTions inForMaTion

Reduction of the valid operating range can be used to

prevent disconnected high impedance input supplies

from reconnecting. For example, if 3 series connected AA

Alkaline batteries with a total series resistance of 675mΩ

is used to source 500mA, the voltage drop due to the se-

ries resistance would be 337.5mV. Once the batteries are

discharged and are disconnected due to a UV fault, the AA

battery stack would recover the 337.5mV drop across the

internal series resistance. Using the 30mV fixed internal

hysteresis allows only 81mV of hysteresis at the input

pin, possibly allowing the input supply to revalidate and

reconnect. Using external hysteresis, the hysteresis volt-

age can be increased to 400mV, reducing or eliminating

the reconnection issue, as shown in Figure 4.

FILTERING NOISE ON OV AND UV PINS

The LTC4417 provides an 8µs OV/UV fault filter time. If

the 8µs filter time is not sufficient, add a filter capacitor

between the OV or UV pin and GND to extend the fault

filter time and ride through transient events. A UV pin fault

filter time extension capacitor, CUVF, is shown in Figure 5.

Use Equation (6) to select CUVF for the UV pin and Equa-

tion (7) to select COVF for the OV pin.

CUVF =tDELAY •R1+R2+R3

R3 •(R1+R2) •ln Vi– Vf

1V – Vf

⎡

⎣

⎢⎤

⎦

⎥

(6)

COVF =tDELAY •R1+R2+R3

R1•(R2+R3) •ln Vi– Vf

1V – Vf

⎡

⎣

⎢⎤

⎦

⎥

(7)

where the final input voltage Vf and the initial voltage Vi

are the resistively divided down values of the input supply

step, as shown in Figure 6.

Connecting HYS to GND, as shown in Figure 5, selects

an internal 30mV fixed hysteresis, resulting in 3% of the

input supply voltage.

Figure 6. Fault Filter Time Extension

4417 F05

WITHOUT FAULT FILTER

TIME EXTENSION

1V VOVUV(THR)

IN(INIT)

VIN(FINAL)

tDELAY

WITH FAULT FILTER

TIME EXTENSION

INPUT SUPPLY STEP

Vi=

VIN(INIT) •(R1+R2)

R1+R2+R3

Vf=

VIN(FINAL) •(R1+R2)

R1+R2+R3

Figure 4. Setting a Higher UV Hysteresis to Prevent

Unwanted Reconnections

400mV HYSTERESIS

FULLY CHARGED 3 × AA BATTERY

VALID UV

RANGE

FOR 81mV

HYSTERESIS

VALID UV

RANGE

FOR 400mV

HYSTERESIS

V1 UV FAULT AND

DISCONNECTS

337.5mV RECOVERY

WHEN LOAD IS

DISCONNECTED

81mV HYSTERESIS

2.7V UV THRESHOLD

4417 F06

CUVF

UV1

V1 INPUT

SUPPLY

LTC4417

1.03V

VALID1

HYS

4417 F04

UV1

VALID

OV1

R2M2

GND

OPTIONAL

FILTER

CAPACITOR

OPTIONAL

DISCONNECT

–

OV1

VALID

VOUT

–

256ms

TIMER

0.97V

Figure 5. LTC4417 Internal Hysteresis with Optional Filter

Capacitor and Manual Disconnect MOSFET

Extending the filter time delay will result in a slower

response to fast UV and OV faults. Extending the UV pin

fault filter time delay will also add delay to the OV pin. If

this is not desirable, separate the single resistive string

into two resistive strings, as shown in Figure 3.

PRIORITY REASSIGNMENT

A connected input supply can be manually disconnected

by artificially creating a UV fault. An example is shown in

Figure 5. When N-channel MOSFET, M2, is turned on, the

LTC4417

4417f

applicaTions inForMaTion

UV1 pin is pulled below 1V. The LTC4417 then discon-

nects V1 and connects the next highest valid priority to

VOUT. When selecting the external N-channel MOSFET,

be sure to account for drain leakage current when setting

UV and OV thresholds by adjusting the resistive divider to

consume more current.

SELECTING EXTERNAL P-CHANNEL MOSFETS

The LTC4417 drives external back-to-back P-channel

MOSFETs to conduct or block load current between an

input supply and load. When selecting external P-channel

MOSFETs, the key parameters to consider are on-resistance

(RDS(ON)), absolute maximum rated drain to source break-

down voltage (BVDSS(MAX)), threshold voltage (VGS(TH)),

power dissipation, and safe operating area (SOA).

To determine the required RDS(ON) use Equation (8), where

VDROP is the maximum desired voltage drop across the

two series MOSFETs at full load current, IL(MAX), for the

application. External P-channel MOSFET devices may be

paralleled to further decrease resistance and decrease

power dissipation of each paralleled MOSFET.

RDS(ON) ≤

DROP

2•IL(MAX)

(8)

The clamped gate drive output is 4.5V (minimum) from

the common source connection. Select logic level or lower

threshold external MOSFETs to ensure adequate overdrive.

For applications with input supplies lower than the clamp

voltage, choose external MOSFET with thresholds suf-

ficiently lower than the input supply voltage to guarantee

full enhancement.

It is imperative that external P-channel MOSFET devices

never exceed their BVDSS(MAX) rating in the application.

Select devices with BVDSS(MAX) ratings higher than seen

in the application. Switching inductive supply inputs with

low value input and/or output capacitances may require

additional precautions; see Transient Supply Protection

section in this data sheet for more information.

In normal operation, the external P-channel MOSFET de-

vices are either fully on, dissipating relatively low power,

or off, dissipating no power. However, during slew-rate

controlled start-up, significant power is dissipated in the

external P-channel MOSFETs. The external P-channel

MOSFETs dissipate the maximum amount of power during

the initial slew-rate limited turn on, where the full input

voltage is applied across the MOSFET while it sources

current. Power dissipation immediately starts to decrease

as the output voltage rises, decreasing the voltage drop

across the MOSFETs.

A conservative approach for determining if a particular

device is capable of supporting soft-start, is to ensure its

maximum instantaneous power, at the start of the output

slewing, is within the manufacturer’s SOA curve. First

determine the duration of soft-start using Equation (9)

and find the inrush current into the load capacitor using

Equation (10).

tSTARTUP =

5 V/ ms

[ ]

(9)

IMAXCAP = CL • 5000[V/s] (10)

Using VIN and IMAXCAP, the power dissipated by the external

MOSFETs during start-up, PSS, is defined by Equation(11).

If the LTC4417 soft-starts with a live IL, the extra load cur-

rent needs to be added to IMAXCAP, and PSS is calculated

by Equation (12).

PSS = VIN • IMAXCAP (11)

PSS = VIN • (IMAXCAP + IL) (12)

Check to ensure PSS with a tSTARTUP single pulse duration

lies within the safe operating area (SOA) of the chosen

MOSFET. Ensure the resistive dividers can sink the drain-

source leakage current at the maximum operating tem-

perature. Refer to manufacturer’s data sheet for maximum

drain to source leakage currents, IDSS.

A list of suggested P-channel MOSFETs is shown in

Table1. Use procedures outlined in this section and the

SOA curves in the chosen MOSFET manufacturer’s data

sheet to verify suitability for the application.

LTC4417

4417f

applicaTions inForMaTion

Table 1. List of Suggested P-Channel MOSFETs

V1, V2, V3 MOSFET VTH(MAX)VGS(MAX)VDS(MAX)

MAX RATED

RDS(ON) AT 25°C

≤5V Si4465ADY –1V ±8V –8V 9mΩ at –4.5V

11mΩ at –2.5V

≤10V Si4931DY* –1V ±8V –12V 18mΩ at –4.5V

22mΩ at –2.5V

≤18V FDS8433A –1V ±8V –20V 47mΩ at –4.5V

70mΩ at –2.5V

≤18V IRF7324* –1V ±12V –20V 18mΩ at –4.5V

26mΩ at –2.5V

≤28V Si7135DP –3V ±20V –30V 6.2mΩ at –4.5V

≤28V FDS6675BNZ –3V ±20V –30V 22mΩ at –4.5V

≤28V AO4803A* –2.5V ±20V –30V 46mΩ at –4.5V

≤36V SUD50P04 –2.5V ±20V –40V 30mΩ at –4.5V

≤36V FDD4685 –3V ±20V –40V 35mΩ at –4.5V

≤36V FDS4685 –3V ±20V –40V 35mΩ at –4.5V

≤36V Si4909DY* –2.5V ±20V –40V 34mΩ at –4.5V

≤36V Si7489DP –3V ±20V –100V 47mΩ at –4.5V

*Denotes Dual P-Channel

REVERSE VOLTAGE PROTECTION

The LTC4417 is designed to withstand reverse voltages

applied to V1, V2 and V3 with respect to VOUT of up to

–84V. The large reverse voltage rating protects 36V input

supplies and downstream devices connected to VOUT

against high reverse voltage connections of –42V (absolute

maximum) with margin.

Select back-to-back P-channel MOSFETS with BVDSS(MAX)

ratings capable of handling any anticipated reverse voltages

between VOUT and V1, V2 or V3. Ensure transient voltage

suppressors (TVS) connected to reverse connection pro-

tected inputs (V1, V2 and V3) are bidirectional and input

capacitors are rated for the negative voltage.

REVERSE CURRENT BLOCKING

When switching channels from higher voltages to lower

voltages, the REV comparator verifies the VOUT voltage is

below the connecting channel’s voltage by 120mV before

the new channel is allowed to connect to VOUT. This ensures

little to no reverse conduction occurs during switching.

An example is shown in Figure 7. V2 is initially connected

to VOUT when a higher priority input supply, V1, is inserted.

The LTC4417 validates V1 and disconnects V2, allowing

VOUT to decay from 18V to 11.88V at a slew rate determined

by the load current divided by the load capacitance. Once

VOUT falls to 11.88V, the LTC4417 connects V1 to VOUT.

SELECTING VOUT CAPACITANCE

To ensure there is minimal droop at the output, select a

low ESR capacitor large enough to ride through the dead

time between channel switchover. A low ESR bulk capacitor

will reduce IR drops to the output voltage while the load

current is sourced from the capacitor. Use Equation (13)

to calculate the load capacitor value that will ride through

the OV/UV comparator delay, tpVALID(OFF), plus the break-

before-make time, tG(SWITCHOVER).

IL(MAX) •tG(SWITCHOVER) +tpVALID(OFF)

( )

VOUT _DROOP(MAX)

(13)

where IL(MAX) is the maximum load current drawn and

VOUT_DROOP(MAX) is the maximum acceptable amount of

voltage droop at the output.

Equation (13) assumes no inrush current limiting circuitry

is required. If it is required, refer to Figure 8 and use the

following Equation (14) for CL.

()

≥

I•tt0.79 •R •C

L(MAX) G(SWITCHOVER)pVALID(OFF)

OUT _DROOP(MAX)

(14)

Figure 7. Reverse Current Blocking

V1 VALIDATES

V2 DISCONNECTS

V1 CONNECTS AT

VOUT = 11.88V

4417 F07

256ms

VOUT

V1 = 12V

VREV =

120mV

VOUT

V2 = 18V

V1 = 12V

dVOUT

dt =IL

LTC4417

4417f

applicaTions inForMaTion

where RS and CS are component values shown in Figure8.

The selection of RS and CL involves an iterative process.

Begin by assuming 0.79 • RS • CS = 10µs and choosing

CL using Equation (14). See the Inrush Current and Input

Voltage Droop section for more details regarding inrush

current limiting circuitry, and for selecting RS.

Figure 8. Slew Rate Limiting Gate Drive

CIN1

68µF CS

VS1

LTC4417

G1 VOUT VOUT

4417 F08

BAT54

12V WALL

ADAPTER

V1 IRF7324

M1 M2

47µF

CVS1

channel disconnects or 32ms has elapsed. Once soft-start

has terminated, the gate driver quickly turns on and off

external back-to-back P-channel MOSFETs as needed. A

SHDN low to high transition or VOUT drooping below 0.7V

reactivates soft-start.

INRUSH CURRENT AND INPUT VOLTAGE DROOP

When switching control of VOUT from a lower voltage supply

to a higher voltage supply, the higher voltage supply may

experience significant voltage droop due to high inrush

current during a fast connection to a lower voltage output

bulk capacitor with low ESR. This high inrush current may

be sufficient to trigger an undesirable UV Fault.

To prevent a UV fault when connecting a higher voltage

input to a lower voltage output, without adding any inrush

current limiting, size the input bypass capacitor large

enough to provide the required inrush current, as shown

by Equation (15).

CV1 ≥CL•V1– VOUT(INIT)

V1DROOP

– 1

⎛

⎝

⎜⎞

⎠

⎟

(15)

where VOUT(INIT) is the initial output voltage when being

powered from a supply voltage less than V1, CV1 is the

bypass capacitor connected to V1, CL is the output capaci-

tor and V1DROOP is the maximum allowed voltage droop

on V1. Make sure CV1 is a low ESR capacitor to minimize

the voltage step across the ESR.

In situations where input and output capacitances can-

not be chosen to set the desired maximum input voltage

droop, or the peak inrush current violates the maximum

Pulsed Drain Current (IDM) of the external P-channel MOS-

FETs, inrush current can be limited by slew rate limiting

the output voltage. The gate driver can be configured to

slew rate limit the output with a resistor, capacitor and

Schottky diode, as shown in Figure 8. The series resistor

RS and capacitor, CS, slew rate limit the output, while the

Schottky diode, DS, provides a fast turn off path when G1

is pulled to VS1.

With a desired input voltage drop, V1DROOP, and known

supply resistance RSRC, the series resistance, RS, can

be calculated with Equation (16), where ∆VG(SINK) is

the LTC4417’s sink clamp voltage, VGS is the external

GATE DRIVER

When turning a channel on, the LTC4417 pulls the common

gate connection (G1, G2 and G3) down with a P-channel

source follower and a 2µA current source. VS1, VS2 and

VS3 voltages at or above 5V will produce rising slew rates

of 12V/µs and falling slew rates of 4V/µs with 10nF between

the VS and G pins. VS1, VS2 and VS3 voltages lower than

5V will result in lower slew rates, see typical curves for

more detail. As G1, G2 and G3 approaches the 6.2V clamp

voltage, the source follower smoothly reduces its current

while the 2µA hold current continues to pull G1, G2 and

G3 to the final clamp voltage, back biasing the source

follower. Clamping the G1, G2 and G3 voltage prevents

any overvoltage stress on the gate to source oxide of the

external back-to-back P-channel MOSFETs. If leakage into

G1, G2 and G3 exceeds the 2µA hold current, the G1, G2

and G3 voltage will rise above the clamp voltage, where

the source follower enhances to sink the excess current.

When turning a channel off, the gate driver pulls the com-

mon gate to the common source with a switch having an

on-resistance of 16Ω, to effect a quick turn-off.

To minimize inrush current at start-up, the gate driver soft-

starts the gate drive of the first input to connect to VOUT.

The gate pin is regulated to create a constant 5V/ms rise

rate on VOUT. Slew rate control is terminated when any

LTC4417

4417f

applicaTions inForMaTion

P-channel’s gate to source voltage when driving the load

and inrush current, CS is the slew rate capacitor and CL

is the VOUT hold up capacitance. The output load current

IL is neglected for simplicity. Choose CS to be at least ten

times the external P-channel MOSFET’s CRSS(MAX), and

CVS to be ten times CS.

RS≥ΔVG(SINK) – VGS

( )

•CL•RSRC

CS•V1

DROOP

(16)

Use Equation (17) to verify the inrush current limit is lower

than the absolute maximum pulsed drain current, IDM.

IINRUSH =

DROOP

RSRC

(17)

If the external P-channel MOSFET’s reverse transfer

capacitance, CRSS, is used instead of CS, replace CS with

CRSS in Equation (16), where CRSS is taken at the minimum

VDS voltage, and calculate for RS. Depending on the size

of CRSS, RS may be large. Care should be used to ensure

gate leakages do not inadvertently turn off the channel over

temperature. This is particularly true of built in Zener gate-

source protected devices. Careful bench characterization

is strongly recommended, as CRSS is non-linear.

The preceding analysis assumes a small input inductance

between the input supply voltage and the drain of the ex-

ternal P-channel MOSFET. If the input inductance is large,

choose CV1 to be much greater than CL and replace RSRC

with the ESR of CV1.

When slew rate limiting the output, ensure power dis-

sipation does not exceed the manufacturer’s SOA for the

chosen external P-channel MOSFET. Refer to the Selecting

External P-channel MOSFETs section.

TRANSIENT SUPPLY PROTECTION

The LTC4417’s abrupt switching due to OV or UV faults

can create large transient overvoltage events with inductive

input supplies, such as supplies connected

by a long cable.

At times the transient overvoltage condition can exceed

twice the nominal voltage. Such events can damage external

devices and the LTC4417. It is imperative that external

back-to-back P-channel MOSFET devices do not exceed

their single pulse avalanche energy specification (EAS) in

unclamped inductive applications and input voltages to the

LTC4417 never exceed the Absolute Maximum Ratings.

To minimize inductive voltage spikes, use wider and/or

heavier trace plating. Adding a snubber circuit will dampen

input voltage spikes as discussed in Linear Application

Note 88, and a transient surge suppressor at the input will

clamp the voltage. Transient voltage suppressors (TVS)

should be placed on any input supply pin, V1, V2 and V3,

where input shorts, or reverse voltage connection can be

made. If short-circuit of input sources powering VOUT are

possible, transient voltage suppressors should also be

placed on VOUT, as shown in Figure 9.

When selecting transient voltage suppressors, ensure the

reverse standoff voltage (VR) is equal to or greater than

the application operating voltage, the peak pulse current

(IPP) is higher than the peak transient voltage divided by

the source impedance, the maximum clamping voltage

(VCLAMP) at the rated IPP is less than the absolute maxi-

mum ratings of the LTC4417 and BVDSS of all the external

back-to-back P-channel MOSFETs.

In applications below 20V, transient voltage suppressors

may not be required if the voltage spikes are lower than the

BVDSS of the external P-channel MOSFETs and the LTC4417

Figure 9. Transient Voltage Suppression

FDD4685 FDD4685

M1 M2

24V WALL

ADAPTER

VS1 G1

VOUT

LTC4417

INPUT

PARASITIC

INDUCTANCE

OUTPUT

PARASITIC

INDUCTANCE

CV1

0.1µF

CSN

RSN COUT

10µF

330µF

VOUT

4417 F09

SMBJ26A

SMBJ26CA

SNUBBER

LTC4417

4417f

Absolute Maximum Ratings. If the BVDSS of the external

P-channel MOSFET is momentarily exceeded, ensure the

avalanche energy absorbed by the MOSFETs do not exceed

the single pulse avalanche energy specification (EAS).

Voltage spikes can be dampened further with a snubber.

INPUT SUPPLY AND VOUT SHORTS

Input shorts can cause high current slew rates. Coupled

with series parasitic inductances in the input and output

paths, potentially destructive transients may appear at the

input and output pins. If the short occurs on an input that

is not powering VOUT, the impact to the system is benign.

Back-to-back P-channel MOSFETs with their common gates

connected to their common sources naturally prevent any

current flow regardless of the applied voltages on either

side of the drain connections, as long as the BVDSS is not

exceeded.

If the short occurs on an input that is powering VOUT, the

issue is compounded by high conduction current and low

impedance connection to the output via the back-to-back

P-channel MOSFETs. Once the LTC4417 blocks the high

input short current, V1, V2 and V3 may experience large

negative voltage spikes while the output may experience

large positive voltage spikes.

To prevent damage to the LTC4417 and associated de-

vices in the event of an input or output short, it may be

necessary to protect the input pins and output pins as

shown in Figure 9. Protect the input pins, V1, V2 and V3,

with either unidirectional or bidirectional TVS and VOUT

with a unidirectional TVS. An input and output capacitor

between 0.1µF and 10µF with intentional or parasitic series

resistance will aid in dampening voltage spikes; see Linear

Technology’s Application Note 88 for general consideration.

Due to the low impedance connection from V1, V2 and V3

to VOUT, shorts to the output will result in an input supply

UV fault. If the UV threshold is high enough and the short

resistive enough, the LTC4417 will disconnect the input.

The fast change in current may force the output below

GND, while the input will increase in voltage.

If UV thresholds are set close to the minimum operating

voltage of the LTC4417, it may not disconnect the input

Figure 10. R-C Filter to Ride Through Input Shorts

10nF

100Ω

VS3

LTC4417

G3VS2 G2

VOUT

VOUT OUTPUT

4417 F10

IRF7324

M5 M6

IRF7324

M3 M4

CLIL

applicaTions inForMaTion

from the output before the output is dragged below the

operating voltage of the LTC4417. The event would cause

the LTC4417’s internal VLDO supply voltage to collapse. A

100Ω and 10nF R-C filter on VOUT will allow the LTC4417

to ride through such shorts to the input and output, as

shown in Figure 10. Because VOUT is also a sense pin

for the REV comparator, care should be taken to ensure

the voltage drop across the resistor is low enough to not

affect the reverse comparator’s threshold. If the 1µs R-C

time constant does not address the issue, increase the

capacitance to lengthen the time constant.

The initial lag due to the R-C filter on the LTC4417’s VOUT

sense and supply pin will cause additional delay in sensing

when a reverse condition has cleared, resulting in addi-

tional droop when transitioning from a higher voltage to

a lower voltage. If the reverse voltage duration is longer

than the R-C delay, the voltage differential between the

output and the filtered VOUT, ∆V, can be calculated with

Equation (18). IL is the output load current during the

reverse voltage condition and IVOUT is current into VOUT,

specified in the electrical table.

ΔV=IL

•CF–IVOUT

⎛

⎝

⎜⎞

⎠

⎟•RF

(18)

ICC PAT H SELECTION

Tw o separate internal power rails ensure the LTC4417 is

functional when one or more input supplies are present

and above 2.4V as well as limit current draw from lower

LTC4417

4417f

priority back up input supplies. An internal diode-OR

structure selects the highest voltage input supply as the

source for VBLDO. If two supplies are similar in voltage and

higher than the remaining input supply, the current will be

equally divided between the similar voltage supplies. If all

input supplies are equal in voltage, the current is divided

evenly between them.

To limit current consumption from lower priority backup

supplies, the LTC4417 prioritizes the internal VLDO’s source

supply. The highest priority source is VOUT, which powers

the VLDO when VOUT is above 2.4V. If VOUT is lower than

2.4V, VLDO switches to the highest valid priority input

supply, V1, V2 and V3. If no input supply is valid, VLDO

is connected to VBLDO, where the diode-OR selects high-

est input voltage input supply as the source. See Typical

Performance Characteristics for more detail.

DUAL SUPPLY OPERATION

For instances where only two supplies are prioritized and

no features of the third channel are used, ground the

V3, OV3, UV3, VS3 and G3 pins of the unused channel.

Alternatively, the lowest priority OV and UV comparators

can be utilized for voltage monitoring when V3 and VS3

are connected to the output and G3 is left open. Figure11

shows an example of the spare OV and UV comparators

used to monitor the 5V output of the LTC3060. VALID3

acts as an open drain OV/UV window comparator output.

Figure 11. Dual Channel with Output Voltage Monitoring

VS1

V1 VOUT

5V OUTPUT

VALID1

VALID2

VALID3

12V WALL

ADAPTER

CIN

2200µF

14.4V NiCd

BATTERY

UV1

OV1

806k

39.2k

60.4k

845k

26.1k

51.1k

340k

21.5k

78.7k

R10

R11

R12

V1 INVALID

V2 INVALID

5V OUTPUT INVALID

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 F11

G1 VS2 VS3G2

GND

LTC4417

CV1

0.1µF

CVS2

1µF

CVS1

0.1µF

CV2

0.1µF

CV3

0.1µF

+CL

100µF

VOUT

LTC3060

LINEAR

REGULATOR

IRF7324

M3 M4

IRF7324

M1 M2

6.8nF

2.21k

BAT54

LTC4417

4417f

applicaTions inForMaTion

DISABLING ALL CHANNELS WITH EN AND SHDN

Driving EN below 1V turns off all external back-to-back

P-channel MOSFETs but does not interrupt input supply

monitoring or reset the 256ms timers. Driving EN above

1V enables the highest valid priority channel. This feature

is essential in cascading applications. For applications

where EN could be driven below ground, limit the current

from EN with a 10k resistor.

Forcing SHDN below 0.8V turns off all external back-to-back

P-channel MOSFETs, disables all OV and UV comparators

and resets all 256ms timers. VALID1, VALID2 and VALID3

release high to indicate all inputs are invalid, regardless

of the input supply condition. The LTC4417 enters into a

low current state, consuming only 15µA. When SHDN is

released or driven above 0.8V, the LTC4417 is required

to revalidate the input supplies before connecting the

inputs to VOUT, as described in the Operation section. For

applications where SHDN could be driven below ground,

limit the current from SHDN with a 10k resistor.

CASCADING

The LTC4417 can be cascaded to prioritize four or more

input supplies. To prioritize four to six supplies, use two

LTC4417s with their VOUT pins connected together and the

master LTC4417’s CAS connected to the slave LTC4417’s

EN as shown in Figure 12. The first LTC4417 to validate an

input will soft-start the common output. Once the output

is above 2.4V, power will be drawn from VOUT by the other

LTC4417 regardless of its input supply conditions.

When the master LTC4417 wants to connect one of its

input supplies to the VOUT, it simultaneously initiates a

channel turn on and pulls its CAS pin low to force the slave

LTC4417 to disconnect its channels. A small amount of

reverse conduction may occur in this case. The amount

of cross conduction will depend on the total turn-on delay

of the master channel compared with the turn-off delay

of the slave channel. Care should be taken to ensure the

connection between CAS and EN is as short as possible,

to minimize the capacitance and hence the turn-off delay

of the slave channel.

When all of the inputs to the master LTC4417 are invalid,

the master confirms that all its inputs are disconnected

from VOUT before releasing CAS. CAS is pulled to the in-

ternal VLDO rail with a 20µA current source, allowing the

slave LTC4417 to connect its highest valid priority channel

to VOUT. Confirmation that all channels are off before the

slave is allowed to connect its channel to VOUT prevents

cross conduction from occurring.

Driving the master LTC4417’s EN low forces both master

and slave to disconnect all channels from the common

output and continue monitoring the input supplies. Driv-

ing the master LTC4417’s SHDN low places it in to a low

current state. While in the low current state, all of its chan-

nels are disconnected and CAS is pulled high with a 20µA

current source, allowing the slave LTC4417 to become the

Figure 12. Cascading Application

VS1

VOUT

SHDN

CAS

LTC4417

MASTER

IRF7324

M1 M2

DISABLE ALL CHANNELS

SHDN MASTER

VOUT

VS1

VOUT

SHDN

CAS

4417 F12

LTC4417

SLAVE

IRF7324

M3 M4

CVS1_2

0.1µF

CVS1_1

0.1µF

47µF

LTC4417

4417f

applicaTions inForMaTion

master and connect its highest valid priority channel to

the common output. If seven, or more, input supplies are

prioritized, additional LTC4417s can be added by connect-

ing all individual VOUT pins together and connecting each

LTC4417’s CAS to the next lower priority LTC4417’s EN.

DESIGN EXAMPLE

A 2A multiple input supply system consisting of a 12V

supply with a source resistance of 20mΩ, 7.4V main

lithium-ion battery, and a backup 7.4V lithium-ion battery

is designed with priority sourcing from the 12V supply,

as shown in Figure 13. Power is sourced from the main

battery when the 12V supply is absent and the backup

battery is only used when the main battery and 12V supply

are not available. The ambient conditions of the system

will be between 25°C and 85°C.

The design limits the output voltage droop to 800mV

during switchover. The load capacitor is assumed to have

a minimum ESR of 50mΩ at 85°C and 80mΩ at 25°C

through paralleling low ESR rated aluminum electrolytic

capacitors. The input source is allowed to drop 1V.

Selecting External P-Channel MOSFET

The design starts with selecting a suitable 2A rated

P-channel MOSFET with desired RDS(ON). Reviewing several

MOSFET options, the low 18mΩ RDS(ON), dual P-channel

IRF7324 with a –20V BVDSS, is chosen for this application.

The low 18mΩ RDS(ON) results in a 72mV combined drop

at 25°C and 85mV drop at 85°C. Each P-channel MOSFET

dissipates 72mW at 25°C and 85mW at 85°C.

Inrush Current Limiting

When connecting a higher voltage source to a lower voltage

output, significant inrush current can occur. The magnitude

of the inrush current can be calculated with Equation (19).

IINRUSH =V1– VOUT(INIT)

RSRC +ESR(CL)+2•RDS(ON)

(19)

where VOUT(INIT) is the VOUT voltage when initially powered

from a supply voltage less than V1, V1 is the higher voltage

source, RSRC is source resistance of V1, ESR(CL) is the

ESR of the load capacitor, and RDS(ON) is the on-resistance

of the external back-to-back MOSFET.

Given a total series resistance from input to output, the

worst case inrush current will occur when V1 is running

20% high, at 14.4V, and VOUT is at its undervoltage limit

of 5.6V. During this condition, a maximum inrush current

of 83A will occur, as shown in Equation (20).

IINRUSH =

14.4V – 5.6V

20mΩ+ 50mΩ+ 36mΩ

=83A

(20)

Because the 83A of inrush current exceeds the 71A ab-

solute maximum pulsed drain current rating, IDM, of the

IRF7324, inrush current limiting is required.

Calculating the load capacitance, CL, and inrush current

limiting circuitry component, RS, is an iterative process.

To start, use Equation (14), with 0.79 • RS • CS initially set

to 10µs. To limit the output voltage droop to the desired

800mV, reserve 200mV for initial droop due to the load

current flowing in the ESR of the output capacitor. Next,

choose CL to set the maximum VOUT droop to 600mV, as

shown in Equation (21).

CL=2A •(3µs+12µs+10µs)

600mV

CL=83.3µF

(21)

For margin, choose the initial CL value equal to 100µF and

use Equation (16) to determine RS. With an allowable 1V

input voltage drop and source resistance, RSRC, of 20mΩ,

the input voltage droop of 700mV is used to set the inrush

current of 35A. The other terms in the equation come

from the external P-channel MOSFET manufacturer’s data

sheet. The transfer characteristics curve shows the gate

voltage, VGS, is approximately 1.8V when driving the 35A

inrush current and the capacitance verses drain-to-source

voltage curve shows the maximum CRSS is approximately

600pF. CS is set to be greater than ten times CRSS, or

6.8nF. To ensure the designed inrush current is lower

than the absolute maximum pulse drain current rating,

IDM, calculate RS using the maximum value for ∆VG(SINK)

and CL, and the minimum value for CS. For aluminum

LTC4417

4417f

applicaTions inForMaTion

Figure 13. Industrial Hand Held Computer

electrolytic capacitors, add 20% to CL and for ceramic

NP0 CS capacitors subtract 5%.

RS=(6V – 1.8V) •120µF •20mΩ

6.5nF •700mV

RS=2.22kΩ

(22)

The standard value of 2.21kΩ is chosen for RS and CVS1

is chosen to be ten times CS or 68nF. Although 1.8V is a

typical value for VGS, there is sufficient margin – even if

VGS = 0V, the resulting IDM is lower than the 71A rating.

With RS and CS known, the desired load capacitance with

inrush current limiting is checked with Equation(14)

as shown in Equation (23). Because the required load

capacitance of 90µF is lower than the chosen load ca-

pacitor of 100µF, the initial choice of 100µF is suitable.

CL≥2A •(3µs+12µs+0.79 •2.21kΩ•6.8nF)

600mV

CL≥90µF

(23)

VS1

V1 VOUT

VALID1

VALID2

VALID3

12V SUPPLY

CIN

2700µF

7.4V Li-Ion

BATTERY

(2 × 3.7V)

UV1

OV1

806k

41.2k

60.4k

768k

53.6k

113k

768k

53.6k

113k

R10

R11

R12

V2 INVALID

V3 INVALID

V1 INVALID

RHYS

255k

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 F13

G1 VS2 VS3G2

CVS3

0.1µF

GND

LTC4417

IRF7324

M5 M6

IRF7324

M3 M4

IRF7324

M1 M2

CVS2

0.1µF

CVS1

68nF

CV1

0.1µF

CV2

0.1µF

CV3

0.1µF

100µF

VOUT

7.4V Li-Ion

BATTERY

(2 × 3.7V)

2.21k

BAT54

6.8nF

140k

LTC4417

4417f

applicaTions inForMaTion

Significant power is dissipated during the channel transi-

tion time. The SOA of the P-channel MOSFET should be

checked to make sure their SOA is not violated.

Worst case slew rate limited channel transition time

would occur when the lithium-ion batteries are running

low at 5.6V, and the supply connects while running 20%

high, at 14.4V. This results in a time of 25µs, as shown

in Equation (24).

dt =

(14.4V – 5.6V) •100µF

35A

dt =25µs

(24)

The IRF7324 thermal response curve at 25µs shows ZθJA

to be approximately 0.18 for a single pulse. The ZθJA of

0.18 results in a maximum transient power dissipation of

694W at 25°C and 361W at 85°C. The external P-channel

MOSFETs will dissipate no more than 8.8V • 37A = 325W

during this period, below the available 361W at 85°C.

The initial soft-start period will also force the external

back-to-back MOSFETs to dissipate significant power. To

check the SOA during this period, start with Equation (9).

tSTARTUP(ms) =12V

5[V/ms]

tSTARTUP(ms) =2.4ms

(25)

IMAXCAP current of 500mA is calculated using Equation (10).

IMAXCAP = 100µF • 5[V/ms]

IMAXCAP = 500mA (26)

The worst case soft-start power dissipation from Equa-

tion (11) is:

PSS(W) = 12V • 500mA

PSS(W) = 6W (27)

The soft-start power dissipation of 6W is well below the

calculated transient power dissipation (PDM) of 79.4W at

a TC of 25°C. An ambient temperature, TA, of 85°C results

in a PDM of 41.3W, indicating it is sufficient to handle the

2.4ms transient 6W power dissipation. A graphical check

with the manufacturer’s SOA curves confirms sufficient

operating margin.

Setting Operational Range

Assuming the 12V source has a tolerance of ±20%, the

input source has an operational undervoltage limit of

9.6V and an overvoltage limit of 14.4V. Ideally the UV1,

UV2 and UV3 and OV1, OV2 and OV3 thresholds would

be set to these limits. However, since the actual threshold

varies by 1.5% and resistor tolerances are 1%, OV and

UV limits must be adjusted to ±26% or 8.9V and 15.1V.

Further, instead of using the internal fixed 30mV, a UV

hysteresis of 200mV is set using an external hysteresis

current of 250nA.

The design process starts with setting RHYS using

Equation (1).

RHYS =

63mV

250nA

=252kΩ

(28)

The nearest standard value is 255kΩ.

Now set the UV hysteresis value using R3

R3 =Desired Hysteresis

IOVUV(HYS)

=200mV

247nA =810kΩ

(29)

The nearest standard value is 806kΩ.

With R3 set, the remaining resistance can be determined

with

R1,2 =

UVTH(FALLING) – VOVUV(THR)

=806kΩ

8.9V – 1V

=102kΩ

(30)

R1 is

R1=R1,2+R3

OVTH(RISING)

=102kΩ+ 806kΩ

15.1V =60.1kΩ

(31)

The nearest 1% standard value is: 60.4kΩ.

R2 is

R2 = R1,2 – R3 = 102kΩ – 60.4kΩ = 41.6kΩ (32)

The nearest 1% standard value is 41.2kΩ.

LTC4417

4417f

applicaTions inForMaTion

Because this is a single resistive string R2, R3, and

IOV_UV(HYS) sets the hysteresis voltage with Equation (30)

OVHYS = (R2 + R3) • IOVUV(HYS) =

(41.2kΩ + 806kΩ) • 247nA = 209mV (33)

This results in an OV threshold of 15.0V and UV threshold

of 8.9V. With hysteresis, the OVHYS threshold is 14.8V

and the UVHYS threshold is 9.1V. For the desired OV and

UV 6% accuracy, 1% resistors used in this example are

acceptable.

Values for R4 to R6 and R7 to R9 for V2 and V3 are

similarly calculated.

Layout Considerations

Sheet resistance of 1oz copper is ~530µΩ per square.

Although small, resistances add up quickly in high current

applications. Keep high current traces short with minimum

trace widths of 0.02" per amp to ensure traces stay at a

reasonable temperatures. Using 0.03" per amp or wider

is recommended. To improve noise immunity, place OV/

UV resistive dividers as close to the LTC4417 as possible.

Transient voltage suppressors should be located as close

to the input connector as possible with short wide traces

to GND. Figure 14 shows a partial layout that addresses

these issues.

Figure 14. Recommended PCB Layout

TO V3 COMMON SOURCE

TO V3 COMMON GATE

TRANSIENT

VOLTAGE

SUPPRESSOR

GNDGND

FROM V1

INPUT SOURCE

0.03" PER

AMPERE

NOT TO SCALE

SHDN

HYS

UV1

OV1

UV2

OV2

UV3

OV3

VALID1

VALID2

VALID3

VS1

VS2

VS3

VOUT

CAS

GND

CV1

CV2

CV3

FROM V2

INPUT SOURCE

TO V3 INPUT SUPPLY

TO OUTPUT

LTC4417

4417f

Typical applicaTions

VS1

V1 VOUT

VALID1

VALID2

VALID3

12V WALL

ADAPTER

CIN1

2200µF

12V NiCd

BATTERY

UV1

OV1

1.02M

48.7k

76.8k

1.02M

36.5k

76.8k

1.0M

40.2k

90.9k

R10

R11

R12

V2 INVALID

V3 INVALID

V1 INVALID

RHYS

316k

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA02

G1 VS2 VS3G2

CVS3

0.1µF

GND

LTC4417

IRF7324

M5 M6

IRF7324

M3 M4

IRF7324

M1 M2

CVS2

1µF

CVS1

0.1µF

CV1

0.1µF

CV2

0.1µF

CV3

0.1µF

100µF

VOUT

11.1V Li-Ion

BATTERY

(3 × 3.7V)

2.21k

BAT54

6.8nF

12V System Using Swappable and Backup Batteries

LTC4417

4417f

Typical applicaTions

18V System with Reverse Voltage Protection

VS1

V1 VOUT

VALID1

VALID2

VALID3

18V

WALL ADAPTER

11.1V Li-Ion

BATTERY

SMBJ26A

UV1

OV1

1.02M

11.8k

54.9k

768k

90.9k

75k

698k

16.9k

49.9k

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA03

G1 VS2 VS3G2

GND

LTC4417

VOUT

FDS4685 FDS4685

M5 M6

FDS4685 FDS4685

M3 M4

FDS4685 FDS4685

M1 M2

12V LEAD-ACID

BATTERY

SMBJ26CA

CVS3

0.1µF

CVS2

0.1µF

CVS1

0.1µF

CIN1

2200µF

CV1

0.1µF

CV2

0.1µF

CV3

0.1µF

100µF

LTC4417

4417f

Typical applicaTions

28V Transient Hold-Up Supply for Solid State Drives (SSD)

VS1

VOUT

VALID1

VALID2

VALID3

12V SYSTEM SUPPLY

CV2

35V

TANTALUM

UV1

OV1

806k

R10

INVALID 12V SYSTEM

LTC3851-1.5V/15A BUCK

PLEASE REFER TO THE LTC3851 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION

INVALID SUPERCAP

SUPERCAP NOT FULLY CHARGED

15.8k

66.5k

806k

127k

33.2k

1.02M

41.2k

124k

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA04

G1 VS2 VS3G2

GND

LTC4417

VOUT

FDS4685 FDS4685

M3 M4

FDS4685 FDS4685

M1 M2

100µF

PGO0D

RUN

TK/SS

ITH

FREQ/PLLFLTR

VIN

PLLIN/MODE

SENSE+

SENSE–

VFB

GND

C16

0.22µF

0.1µF

R17

10k

LTC3851

5V, 15A

OUTPUT

0.68µH

0.1µF

CVS2

0.1µF

CVS1

1µF

2200pF

C17

0.1µF

4.7µF

BOOST

R13

100k

R15

255k

R19

13k

R16

48.7k

R20

82.5k

R14

15k

R18

100k

CMDSH2-3

INTVCC

MBRS360

330µF

×2

MBRS340

STD30NFL06L

C15

47pF

LT3956 SUPERCAP CHARGER WITH INPUT CURRENT LIMIT

PLEASE REFER TO THE LT3956 DATA SHEET FOR SPECIFIC APPLICATION INFORMATION

R12

R11

LT3956

GND

INTVCC EN/UVLO

VREF

VIN

R23

1Ω

4.7µF

10nF

C10

10µF

VMODE

PWM

L1A

33µH CTRL

R27

30.1k

R32

ISP

ISN

PWMOUT

R24

28.7k

R29

40.2k

R30

R28

R21

536k

R22

25k

R31

59k

R26

10k

R25

14k

BC817-25

L1B

33µH

C11

10µF

330pF

1.43k

BAT54

6.8nF

CV1

470µF

LTC4417

4417f

Typical applicaTions

Selecting from USB, FireWire, and Li-Ion Battery Power Sources

VS1

V1 VOUT

VALID1

VALID2

VALID3

4.35V TO 5.25V

USB

CIN1

10µF

8V TO 30V

FireWire

IEEE1394

UV1

OV1

309k R10

USB INVALID

FireWire INVALID

Li_Ion INVALID

R11

R12

24.9k

75k

576k

78.7k

20.5k

931k

63.4k

137k

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA05

G1 VS2 VS3G2

GND

LTC4417

VOUT

FDS4685 FDS4685

M5 M6

FDS4685 FDS4685

M3 M4

FDS4685 FDS4685

M1 M2

7.4V Li-Ion

BATTERY

CIN2

22µF

47µF

CVS3

0.1µF

CVS2

1µF

CVS1

0.1µF RS

BAT54

6.8nF

CV3

0.1µF

CV2

0.1µF

CV1

0.1µF

LTC4417

4417f

Typical applicaTions

Wall Adapter and USB Input with Battery Backup

VS1

V1 VOUT

VALID1

VALID2

VALID3

5V WALL

ADAPTER

4.35V TO 5.25V

USB

UV1

OV1

412k R13

R12

R14

37.4k

95.3k

412k

33.2k

100k

432k

80.6k

86.6k

R11

562k

UV2

OV2

R10

52.3k

RHYS

249k

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA06

G1 VS2 VS3G2

GND

LTC4417

VOUT

Si4931DY

M5 M6

Si4931DY

M3 M4

Si4931DY

M1 M2

4 × AA

BATTERY

CIN2

10µF

CVS3

0.1µF

CVS2

0.1µF

CVS1

0.1µF

CV3

0.1µF

CV2

0.1µF

WALL ADAPTER INVALID

USB INVALID

4 × AA BATTERY INVALID

47µF

CIN1

1000µF

CV1

0.1µF

LTC4417

4417f

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

.337 – .344*

(8.560 – 8.738)

GN24 REV B 0212

1 2 345678 9 10 11 12

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

161718192021222324 15 1413

.016 – .050

(0.406 – 1.270)

.015 ±.004

(0.38 ±0.10) × 45°

0° – 8° TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

LTC4417

4417f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

4.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ±0.10

(4-SIDES)

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ±0.05

(4 SIDES)

3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697 Rev B)

LTC4417

4417f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2012

LT 1112 • PRINTED IN USA

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal 2.6A P-channel, 2.6V to 5.5V, 40µA IQ, SOT-23 Package

LTC4412HV 36V Low Loss PowerPath Controller in ThinSOT 2.5V to 36V, P-channel, 11µA IQ, SOT-23 Package

LTC4415 Dual 4A Ideal Diodes with Adjustable Current Limit Dual Internal P-channel, 1.7V to 5.5V, MSOP-16 and DFN-16 Packages

LTC4416 36V Low Loss Dual PowerPath Controller for Large PFETs 3.6V to 36V, 35µA IQ per Supply, MSOP-10 Package

LTC4355 Positive High Voltage Ideal Diode-OR with Supply and

Fuse Monitors

Dual N-channel, 9V to 80V, SO-16, MSOP-16 and DFN-14 Packages

LTC4359 Ideal Diode Controller with Reverse Input Protection N-channel, 4V to 80V, MSOP-8 and DFN-6 Packages

LTC2952 Pushbutton PowerPath Controller with Supervisor 2.7V to 28V, On/Off Timers, ±8kV HBM ESD, TSSOP-20 and QFN-20

Packages

Dual Channel LTC4417 Application with Output Voltage Monitoring Using Third Channel

10µF

VS1

V1 VOUT

5V OUTPUT

VALID1

VALID2

VALID3

12V WALL

ADAPTER

CIN

2200µF

14.4V NiCd

BATTERY

UV1

OV1

806k

39.2k

60.4k

845k

26.1k

51.1k

357k

15.4k

84.5k

R10

R11

R12

V1 INVALID

V2 INVALID

5V OUTPUT INVALID

UV2

OV2

V3 EN

SHDN

HYS

CAS

UV3

OV3

4417 TA07

G1 VS2 VS3G2

GND

LTC4417

IRF7324

M3 M4

IRF7324

M1 M2

CV1

0.1µF

CVS2

1µF

10nF

CVS1

0.1µF

CV2

0.1µF

CV3

0.1µF

+CL

100µF

VOUT

INOUT

REF/BYP

10nF

ADJ

GND

SHDN

LT3060-5

2.21k

BAT54

6.8nF