January 2009 Rev 4 1/104
ST6208C ST6209C
ST6210C ST6220C
8-bit MCUs with A/D converter,
two timers, oscillator safeguard & safe reset
Memories
1K, 2K or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
64 bytes RAM
Clock, Reset and Supply Management
Enhanced reset system
Low Voltage Detector (LVD) for Safe Reset
Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
Oscillator Safeguard (OSG)
2 Power Saving Modes: Wait and Stop
Interrupt Management
4 interrupt vectors plus NMI and RESET
12 external interrupt lines (on 2 vectors)
12 I/O Ports
12 multifunctional bidirectional I/O lines
8 alternate function lines
4 high sink outputs (20mA)
2 Timers
Configurable watchdog timer
8-bit timer/counter with a 7-bit prescaler
Analog Peripheral
8-bit ADC with 4 or 8 input channels (except
on ST6208C)
Instruction Set
8-bit data manipulation
40 basic instructions
9 addressing modes
Bit manipulation
Development Tools
Full hardware/software development package
Device Summary
(See Section 11.5 for Ordering Information)
PDIP20
SO20
CDIP20W
SSOP20
Features ST6208C ST6209C ST6210C ST6220C
Program memory
- bytes 1K 2K 4K
RAM - bytes 64
Operating Supply 3.0V to 6V
Analog Inputs - 48
Clock Frequency 8MHz Max
Operating
Temperature -40°C to +125°C
Packages PDIP20/SO20/SSOP20
1
Obsolete Product(s) - Obsolete Product(s)
Table of Contents
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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9
3.1 MEMORY AND REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.3 Readout Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.6 Data ROM Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 CLOCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 Oscillator Safeguard (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 Low Frequency Auxiliary Oscillator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.9 EXTERNAL INTERRUPTS (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.1 Notes on using External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.10 INTERRUPT HANDLING PROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10.1Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.11 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Obsolete Product(s) - Obsolete Product(s)
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6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 NOTES RELATED TO WAIT AND STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.1 Exit from Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.2 Recommended MCU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1 Digital Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.3 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) 39
7.2.6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3.4 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.1Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.4Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.5Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.1General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 65
10.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.1RUN Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.1General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.3Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.5.5Oscillator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 75
10.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.6.1RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.6.2EPROM Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.7.1Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.9.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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11.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.3 ECOPACK INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6.2ROM VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13 ST6 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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1 INTRODUCTION
The ST6208C, 09C, 10C and 20C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E20C is the erasable EPROM version of
the ST62T08C, T09C, T10C and T20C devices,
which may be used during the development phase
for the ST62T08C, T09C, T10C and T20C target
devices, as well as the respective ST6208C, 09C,
10C and 20C ROM devices.
OTP and EPROM devices are functionally identi-
cal. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ROM based versions offer the same function-
ality, selecting the options defined in the program-
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 11.6 on page
96).
The ST62P08C/P09C/P10C/P20C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T08C, T09C, T10C and T20C
OTP devices.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 11 on page 90).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable prescaler, an 8-bit A/D Converter with up to
8 analog inputs (depending on device) and a Dig-
ital Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
For easy reference, all parametric data are located
in Section 11 on page 90.
Figure 1. Block Diagram
NMI INTERRUPTS
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY OSCILLATOR RESET
DATA ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
8-BIT CORE
8-BIT *
A/D CONVERTER PA0..PA3 (20mA Sink)
PB0..PB7 / Ain*
TIMER
VDD VSS OSCin OSCout RESET
WATCHDOG
:
MEMORY
TIMER
(1K, 2K
* Depending on device. Please refer to I/O Port section.
or 4K Bytes)
VPP
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2 PIN DESCRIPTION
Figure 2. 20-Pin Package Pinout
Table 1. Device Pin Description
VDD
TIMER
Ain*/PB5
Ain*/PB6
Ain*/PB7
RESET
VPP
NMI
OSCout
OSCin
VSS
PA0/20mA Sink
PB4/Ain*
PB3/Ain*
PB2/Ain*
PB1/Ain*
PB0/Ain*
PA3/20mA Sink
PA2/20mA Sink
PA1/20mA Sink
itX associated interrupt vector
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
* Depending on device. Please refer to I/O Port section.
it2
it1
it2
Pin n° Pin Name
Type
Main Function
(after Reset) Alternate Function
1 VDD S Main power supply
2 TIMER I/O Timer input or output
3 OSCin I External clock input or resonator oscillator inverter input
4 OSCout O Resonator oscillator inverter output or resistor input for RC oscillator
5 NMI I Non maskable interrupt (falling edge sensitive)
6V
PP Must be held at Vss for normal operation, if a 12.5V level is applied to the pin
during the reset phase, the device enters EPROM programming mode.
7 RESET I/O Top priority non maskable interrupt (active low)
8 PB7/Ain* I/O Pin B7 (IPU) Analog input
9 PB6/Ain* I/O Pin B6 (IPU) Analog input
10 PB5/Ain* I/O Pin B5 (IPU) Analog input
11 PB4/Ain* I/O Pin B4 (IPU) Analog input
12 PB3/Ain* I/O Pin B3 (IPU) Analog input
13 PB2/Ain* I/O Pin B2 (IPU) Analog input
14 PB1/Ain* I/O Pin B1 (IPU) Analog input
15 PB0/Ain* I/O Pin B0 (IPU) Analog input
16 PA3/ 20mA Sink I/O Pin A3 (IPU)
17 PA2/ 20mA Sink I/O Pin A2 (IPU)
18 PA1/ 20mA Sink I/O Pin A1 (IPU)
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Legend / Abbreviations for Table 1:
* Depending on device. Please refer to Section 7 "I/O PORTS" on page 37.
I = input, O = output, S = supply, IPU = input with pull-up
The input with pull-up configuration (reset state) is valid as long as the user software does not change it.
Refer to Section 7 "I/O PORTS" on page 37 for more details on the software configuration of the I/O ports.
19 PA0/ 20mA Sink I/O Pin A0 (IPU)
20 VSS S Ground
Pin n° Pin Name
Type
Main Function
(after Reset) Alternate Function
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3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS
3.1.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
Figure 3. Memory Addressing Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS ACCUMULATOR
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
DATA SPACE
000h
0FF0h
0FFFh
MEMORY
WINDOW
DATA ROM
RESERVED
HARDWARE
CONTROL
REGISTERS
0BFh
(see Table 2)
(see Figure 4
on page 10)
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MEMORY MAP (Cont’d)
Figure 4. Program Memory Map
(*) Reserved areas should be filled with 0FFh
0000h
0AFFh
0B00h
0B9Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
1024 BYTES
0BA0h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
0000h
07Fh
USER
PROGRAM MEMORY
3872 BYTES
080h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
RESERVED*
0000h
07FFh
0800h
087Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
1824 BYTES
0880h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
ST6208C, 09C ST6210C ST6220C
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MEMORY MAP (Cont’d)
3.1.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register). Thus, the MCU is capable of ad-
dressing 4K bytes of memory directly.
3.1.3 Readout Protection
The Program Memory in OTP, EPROM or ROM
devices can be protected against external readout
of memory by setting the Readout Protection bit in
the option bytes (Section 3.3 on page 16).
In the EPROM parts, Readout Protection option
can be desactivated only by U.V. erasure that also
results in the whole EPROM context being erased.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP or ROM contents. Re-
turned parts can therefore not be accepted if the
Readout Protection bit is set.
3.1.4 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
3.1.4.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
3.1.4.2 Data RAM
The data space includes the user RAM area, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and control registers, the
interrupt option register and the Data ROM Win-
dow register (DRWR register).
3.1.5 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
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MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 7 "I/O PORTS" on page 37 for more details)
4. Depending on device. See device summary on page 1.
Address Block Register
Label Register Name Reset
Status Remarks
080h
to 083h CPU X,Y,V,W X,Y index registers
V,W short direct registers xxh R/W
0C0h
0C1h I/O Ports DRA 1) 2) 3)
DRB 1) 2) 3) Port A Data Register
Port B Data Register
00h
00h
R/W
R/W
0C2h
0C3h Reserved (2 Bytes)
0C4h
0C5h I/O Ports DDRA 2)
DDRB 2) Port A Direction Register
Port B Direction Register
00h
00h
R/W
R/W
0C6h
0C7h Reserved (2 Bytes)
0C8h CPU IOR Interrupt Option Register xxh Write-only
0C9h ROM DRWR Data ROM Window register xxh Write-only
0CAh
0CBh Reserved (2 Bytes)
0CCh
0CDh I/O Ports ORA 2)
ORB 2) Port A Option Register
Port B Option Register
00h
00h
R/W
R/W
0CEh
0CFh Reserved (2 bytes)
0D0h
0D1h ADC 4) ADR
ADCR
A/D Converter Data Register
A/D Converter Control Register
xxh
40h
Read-only
Ro/Wo
0D2h
0D3h
0D4h
Timer1
PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
7Fh
0FFh
00h
R/W
R/W
R/W
0D5h
to 0D7h Reserved (3 Bytes)
0D8h Watchdog
Timer WDGR Watchdog Register 0FEh R/W
0D9h
to 0FEh Reserved (38 Bytes)
0FFh CPU A Accumulator xxh R/W
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MEMORY MAP (Cont’d)
3.1.6 Data ROM Window
The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 0FFFh.
There are 64 blocks of 64 bytes in a 4K device:
Block 0 is related to the address range 0000h to
003Fh.
Block 1 is related to the address range 0040h to
007Fh.
and so on...
All the program memory can therefore be used to
store either instructions or read-only data. The
Data ROM window can be moved in steps of 64
bytes along the program memory by writing the
appropriate code in the Data ROM Window Regis-
ter (DRWR).
Figure 5. Data ROM Window
3.1.6.1 Data ROM Window Register (DRWR)
The DRWR can be addressed like any RAM loca-
tion in the Data Space.
This register is used to select the 64-byte block of
program memory to be read in the Data ROM win-
dow (from address 40h to address 7Fh in Data
space). The DRWR register is not cleared on re-
set, therefore it must be written to before access-
ing the Data read-only memory window area for
the first time.
Address: 0C9h Write Only
Reset Value = xxh (undefined)
Bits 7:6 = Reserved, must be cleared.
Bit 5:0 = DRWR[5:0] Data read-only memory Win-
dow Register Bits. These are the Data read-only
memory Window bits that correspond to the upper
bits of the data read-only memory space.
Caution: This register is undefined on reset, it is
write-only, therefore do not read it nor access it us-
ing Read-Modify-Write instructions (SET, RES,
INC and DEC).
0000h
0FFFh
000h
040h
07Fh
0FFh
DATA ROM
WINDOW
DATA SPACE
64-BYTE
ROM
PROGRAM
SPACE
70
- - DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
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MEMORY MAP (Cont’d)
3.1.6.2 Data ROM Window memory addressing
In cases where some data (look-up tables for ex-
ample) are stored in program memory, reading
these data requires the use of the Data ROM win-
dow mechanism. To do this:
1. The DRWR register has to be loaded with the
64-byte block number where the data are located
(in program memory). This number also gives the
start address of the block.
2. Then, the offset address of the byte in the Data
ROM Window (corresponding to the offset in the
64-byte block in program memory) has to be load-
ed in a register (A, X,...).
When the above two steps are completed, the
data can be read.
To understand how to determine the DRWR and
the content of the register, please refer to the ex-
ample shown in Figure 6. In any case the calcula-
tion is automatically handled by the ST6 develop-
ment tools.
Please refer to the user manual of the correspod-
ing tool.
3.1.6.3 Recommendations
Care is required when handling the DRWR regis-
ter as it is write only. For this reason, the DRWR
contents should not be changed while executing
an interrupt service routine, as the service routine
cannot save and then restore the register’s previ-
ous contents. If it is impossible to avoid writing to
the DRWR during the interrupt service routine, an
image of the register must be saved in a RAM lo-
cation, and each time the program writes to the
DRWR, it must also write to the image register.
The image register must be written first so that, if
an interrupt occurs between the two instructions,
the DRWR is not affected.
Figure 6. Data ROM Window Memory Addressing
DATA
PROGRAM SPACE
DATA SPACE
0000h
0400h
0421h
07FFh
64 bytes
OFFSET
000h
040h
061h
07Fh
OFFSET
21h
0FFh
DRWR
DATA address in Program memory : 421h
DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h
64-byte window start address : 10h x 3Fh = 400h
Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h
10h
DATA
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3.2 PROGRAMMING MODES
3.2.1 Program Memory
EPROM/OTP programming mode is set by a
+12.5V voltage applied to the TEST/VPP pin. The
programming flow of the ST62T08C,T09C,T10C,
T20C and E20C is described in the User Manual of
the EPROM Programming Board.
Table 3. ST6208C/09C Program Memory Map
Table 4. ST6210C Program Memory Map
Table 5. ST6220C Program Memory Map
Note: OTP/EPROM devices can be programmed
with the development tools available from
STMicroelectronics (please refer to Section 12 on
page 99).
3.2.2 EPROM Erasing
The EPROM devices can be erased by exposure
to Ultra Violet light. The characteristics of the MCU
are such that erasure begins when the memory is
exposed to light with a wave lengths shorter than
approximately 4000Å. It should be noted that sun-
light and some types of fluorescent lamps have
wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCU packages be covered by an opaque label to
prevent unintentional erasure problems when test-
ing the application in such an environment.
The recommended erasure procedure is exposure
to short wave ultraviolet light which have a wave-
length 2537Å. The integrated dose (i.e. U.V. inten-
sity x exposure time) for erasure should be a mini-
mum of 30W-sec/cm2. The erasure time with this
dosage is approximately 30 to 40 minutes using an
ultraviolet lamp with 12000µW/cm2 power rating.
The EPROM device should be placed within
2.5cm (1inch) of the lamp tubes during erasure.
Device Address Description
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
Device Address Description
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Interrupt Vector
Reset Vector
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3.3 OPTION BYTES
Each device is available for production in user pro-
grammable versions (OTP) as well as in factory
coded versions (ROM). OTP devices are shipped
to customers with a default content (00h), while
ROM factory coded parts contain the code sup-
plied by the customer. This implies that OTP de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST6 program-
ming tool).
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see Section
11.6.2 "ROM VERSION" on page 98). It is there-
fore impossible to read the option bytes.
The option bytes can be only programmed once. It
is not possible to change the selected options after
they have been programmed.
In order to reach the power consumption value in-
dicated in Section 10.4, the option byte must be
programmed to its default value. Otherwise, an
over-consumption will occur.
MSB OPTION BYTE
Bits 15:10 = Reserved, must be always cleared.
Bit 9 = EXTCNTL External STOP MODE control.
0: EXTCNTL mode not available. STOP mode is
not available with the watchdog active.
1: EXTCNTL mode available. STOP mode is avail-
able with the watchdog active by setting NMI pin
to one.
Bit 8 = LVD Low Voltage Detector on/off.
This option bit enable or disable the Low Voltage
Detector (LVD) feature.
0: Low Voltage Detector disabled
1: Low Voltage Detector enabled
LSB OPTION BYTE
Bit 7 = PROTECT Readout Protection.
This option bit enables or disables external access
to the internal program memory.
0: Program memory not read-out protected
1: Program memory read-out protected
Bit 6 = OSC Oscillator selection.
This option bit selects the main oscillator type.
0: Quartz crystal, ceramic resonator or external
clock
1: RC network
Bit 5 = Reserved, must be always cleared.
Bit 4 = Reserved, must be always set.
Bit 3 = NMI PULL NMI Pull-Up on/off.
This option bit enables or disables the internal pull-
up on the NMI pin.
0: Pull-up disabled
1: Pull-up enabled
Bit 2 = TIM PULL TIMER Pull-Up on/off.
This option bit enables or disables the internal pull-
up on the TIMER pin.
0: Pull-up disabled
1: Pull-up enabled
Bit 1 = WDACT Hardware or software watchdog.
This option bit selects the watchdog type.
0: Software (watchdog to be enabled by software)
1: Hardware (watchdog always enabled)
Bit 0 = OSGEN Oscillator Safeguard on/off.
This option bit enables or disables the oscillator
Safeguard (OSG) feature.
0: Oscillator Safeguard disabled
1: Oscillator Safeguard enabled
MSB OPTION BYTE
15 8
LSB OPTION BYTE
70
Reserved EXT
CTL LVD PRO-
TECT OSC Res. Res. NMI
PULL
TIM
PULL
WD
ACT
OSG
EN
Default
Value XXXXXXXXXXXXX X X X
1
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4 CENTRAL PROCESSING UNIT
4.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses.
4.2 MAIN FEATURES
40 basic instructions
9 main addressing modes
Two 8-bit index registers
Two 8-bit short direct registers
Low power modes
Maskable hardware interrupts
6-level hardware stack
4.3 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
Space as a RAM location at address FFh. Thus
the ST6 can manipulate the accumulator just like
any other register in Data Space.
Index Registers (X, Y). These two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bit Direct
addressing modes. They are mapped in Data
Space at addresses 80h (X) and 81h (Y) and can
be accessed like any other memory location.
Short Direct Registers (V, W). These two regis-
ters are used in Short Direct addressing mode.
This means that the data stored in V or W can be
accessed with a one-byte instruction (four CPU cy-
cles). V and W can also be accessed using Direct
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 82h (V) and
83h (W) and can be accessed like any other mem-
ory location.
Note: The X and Y registers can also be used as
Short Direct registers in the same way as V and W.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next instruction to be executed by the core. This
ROM location may be an opcode, an operand, or
the address of an operand.
Figure 7. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
70
70
70
0
11
RESET VALUE = xxh
RESET VALUE = xxh
RESET VALUE = xxh
x = Undefined value
V SHORT INDIRECT
70
RESET VALUE = xxh
W SHORT INDIRECT
70
RESET VALUE = xxh
NORMAL FLAGS CN ZN
CI ZI
CNMI ZNMI
INTERRUPT FLAGS
NMI FLAGS
SIX LEVEL
STACK
REGISTER
REGISTER
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CPU REGISTERS (Cont’d)
The 12-bit length allows the direct addressing of
4096 bytes in Program Space.
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
ROM Page register.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
JP (Jump) instruction PC = Jump address
CALL instruction PC = Call address
Relative Branch InstructionPC = PC +/- offset
Interrupt PC = Interrupt vector
Reset PC = Reset vector
RET & RETI instructions PC = Pop (stack)
Normal instruction PC = PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (or the NMI flags) in-
stead of the Normal flags. When the RETI instruc-
tion is executed, the previously used set of flags is
restored. It should be noted that each flag set can
only be addressed in its own context (Non Maska-
ble Interrupt, Normal Interrupt or Main routine).
The flags are not cleared during context switching
and thus retain their status.
C : Carry flag.
This bit is set when a carry or a borrow occurs dur-
ing arithmetic operations; otherwise it is cleared.
The Carry flag is also set to the value of the bit
tested in a bit test instruction; it also participates in
the rotate left instruction.
0: No carry has occured
1: A carry has occured
Z : Zero flag
This flag is set if the result of the last arithmetic or
logical operation was equal to zero; otherwise it is
cleared.
0: The result of the last operation is different from
zero
1: The result of the last operation is zero
Switching between the three sets of flags is per-
formed automatically when an NMI, an interrupt or
a RETI instruction occurs. As NMI mode is auto-
matically selected after the reset of the MCU, the
ST6 core uses the NMI flags first.
Stack. The ST6 CPU includes a true LIFO (Last In
First Out) hardware stack which eliminates the
need for a stack pointer. The stack consists of six
separate 12-bit RAM locations that do not belong
to the data space RAM area. When a subroutine
call (or interrupt request) occurs, the contents of
each level are shifted into the next level down,
while the content of the PC is shifted into the first
level (the original contents of the sixth stack level
are lost). When a subroutine or interrupt return oc-
curs (RET or RETI instructions), the first level reg-
ister is shifted back into the PC and the value of
each level is popped back into the previous level.
Figure 8. Stack manipulation
Since the accumulator, in common with all other
data space registers, is not stored in this stack,
management of these registers should be per-
formed within the subroutine.
Caution: The stack will remain in its “deepest” po-
sition if more than 6 nested calls or interrupts are
executed, and consequently the last return ad-
dress will be lost.
It will also remain in its highest position if the stack
is empty and a RET or RETI is executed. In this
case the next instruction will be executed.
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
ON
INTERRUPT,
OR
SUBROUTINE
CALL
ON RETURN
FROM
INTERRUPT,
OR
SUBROUTINE
PROGRAM
COUNTER
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5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources:
external clock signal
external AT-cut parallel-resonant crystal
external ceramic resonator
external RC network (RNET).
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup oscillator in the event of main oscil-
lator failure. It also automatically limits the internal
clock frequency (fINT) as a function of VDD, in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
Table 6 illustrates various possible oscillator con-
figurations using an external crystal or ceramic
resonator, an external clock input, an external re-
sistor (RNET), or the lowest cost solution using only
the LFAO.
For more details on configuring the clock options,
refer to the Option Bytes section of this document.
The internal MCU clock frequency (fINT) is divided
by 12 to drive the Timer, the Watchdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.
With an 8 MHz oscillator, the fastest CPU cycle is
therefore 1.625µs.
A CPU cycle is the smallest unit of time needed to
execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five CPU cycles for execution.
Figure 9. Clock Circuit Block Diagram
MAIN
OSCILLATOR
OSG
LFAO
CORE
: 13
: 12
8-BIT TIMER
WATCHDOG
fINT
OSCOFF BIT
ADC
0
1
filtering
OSCILLATOR SAFEGUARD (OSG)
OSG ENABLE OPTION BIT (See OPTION BYTE SECTION)
(ADCR REGISTER)
fOSC
* Depending on device. See device summary on page 1.
*
*
Oscillator
Divider
SPI
: 1
: 3
8-BIT ARTIMER
8-BIT ARTIMER
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CLOCK SYSTEM (Cont’d)
5.1.1 Main Oscillator
The oscillator configuration is specified by select-
ing the appropriate option in the option bytes (refer
to the Option Bytes section of this document).
When the CRYSTAL/RESONATOR option is se-
lected, it must be used with a quartz crystal, a ce-
ramic resonator or an external signal provided on
the OSCin pin. When the RC NETWORK option is
selected, the system clock is generated by an ex-
ternal resistor (the capacitor is implemented inter-
nally).
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register (not
available on some devices). This will automatically
start the Low Frequency Auxiliary Oscillator
(LFAO).
The main oscillator can be turned off by resetting
the OSCOFF bit of the A/D Converter Control Reg-
ister or by resetting the MCU. When the main os-
cillator starts there is a delay made up of the oscil-
lator start-up delay period plus the duration of the
software instruction at a clock frequency fLFAO.
Caution: It should be noted that when the RC net-
work option is selected, the accuracy of the fre-
quency is about 20% so it may not be suitable for
some applications (For more details, please refer
to the Electrical Characteristics Section).
Table 6. Oscillator Configurations
Notes:
1. To select the options shown in column 1 of the above
table, refer to the Option Byte section.
2.This schematic are given for guidance only and are sub-
ject to the schematics given by the crystal or ceramic res-
onator manufacturer.
3. For more details, please refer to the Electrical Charac-
teristics Section.
Hardware Configuration
Crystal/Resonator Option1)
Crystal/Resonator Option1)
RC Network Option1)
OSG Enabled Option1)
OSCin OSCout
EXTERNAL
ST6
CLOCK
NC
External Clock
OSCin OSCout
LOAD
CAPACITORS 3)
ST6
CL2
CL1
Crystal/Resonator Clock 2)
OSCin OSCout
ST6
RNET
NC
RC Network
OSCin OSCout
ST6
LFAO
NC
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CLOCK SYSTEM (Cont’d)
5.1.2 Oscillator Safeguard (OSG)
The Oscillator Safeguard (OSG) feature is a
means of dramatically improving the operational
integrity of the MCU. It is available when the OSG
ENABLED option is selected in the option byte (re-
fer to the Option Bytes section of this document).
The OSG acts as a filter whose cross-over fre-
quency is device dependent and provides three
basic functions:
Filtering spikes on the oscillator lines which
would result in driving the CPU at excessive fre-
quencies
Management of the Low Frequency Auxiliary
Oscillator (LFAO), (useable as low cost internal
clock source, backup clock in case of main oscil-
lator failure or for low power consumption)
Automatically limiting the fINT clock frequency as
a function of supply voltage, to ensure correct
operation even if the power supply drops.
5.1.2.1 Spike Filtering
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
10). In all cases, when the OSG is active, the max-
imum internal clock frequency, fINT, is limited to
fOSG, which is supply voltage dependent.
5.1.2.2 Management of Supply Voltage
Variations
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequen-
cy with OSG enabled.
5.1.2.3 LFAO Management
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator can be used (see Section
5.1.3).
Note: The OSG should be used wherever possible
as it provides maximum security for the applica-
tion. It should be noted however, that it can in-
crease power consumption and reduce the maxi-
mum operating frequency to fOSG (see Electrical
Characteristics section).
Caution: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and may vary
depending on both VDD and temperature. For pre-
cise timing measurements, it is not recommended
to use the OSG.
Figure 10. OSG Filtering Function
Figure 11. LFAO Oscillator Function
fOSC
fOSG
fINT
fOSC<fOSG
fOSC>fOSG
MAIN OSCILLATOR
STOPS
MAIN OSCILLATOR
RESTARTS
INTERNAL CLOCK DRIVEN BY LFAO
fOSC
fINT
fLFAO
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CLOCK SYSTEM (Cont’d)
5.1.3 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a backup oscillator in case of main oscillator fail-
ure.
This oscillator is available when the OSG ENA-
BLED option is selected in the option byte (refer to
the Option Bytes section of this document). In this
case, it automatically starts one of its periods after
the first missing edge of the main oscillator, what-
ever the reason for the failure (main oscillator de-
fective, no clock circuitry provided, main oscillator
switched off...). See Figure 11.
User code, normal interrupts, WAIT and STOP in-
structions, are processed as normal, at the re-
duced fLFAO frequency. The A/D converter accura-
cy is decreased, since the internal frequency is be-
low 1.2 MHz.
At power on, until the main oscillator starts, the re-
set delay counter is driven by the LFAO. If the
main oscillator starts before the 2048 cycle delay
has elapsed, it takes over.
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as soon as the main oscilla-
tor starts.
5.1.4 Register Description
ADC CONTROL REGISTER (ADCR)
Address: 0D1h Read/Write
Reset value: 0100 0000 (40h)
Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0] ADC Control
Register.
These bits are used to control the A/D converter (if
available on the device) otherwise they are not
used.
Bit 2 = OSCOFF Main Oscillator Off.
0: Main oscillator enabled
1: Main oscillator disabled
Note: The OSG must be enabled using the OS-
GEN option in the Option Byte, otherwise the OS-
COFF setting has no effect.
70
ADCR
7
ADCR
6
ADCR
5
ADCR
4
ADCR
3
OSC
OFF
ADCR
1
ADCR
0
1
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5.2 LOW VOLTAGE DETECTOR (LVD)
The on-chip Low Voltage Detector is enabled by
setting a bit in the option bytes (refer to the Option
Bytes section of this document).
The LVD allows the device to be used without any
external RESET circuitry. In this case, the RESET
pin should be left unconnected.
If the LVD is not used, an external circuit is manda-
tory to ensure correct Power On Reset operation,
see figure in the Reset section. For more details,
please refer to the application note AN669.
The LVD generates a static Reset when the supply
voltage is below a reference value. This means
that it secures the power-up as well as the power-
down keeping the ST6 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated in Figure 12.
If the LVD is enabled, the MCU can be in only one
of two states:
Over the input threshold voltage, it is running un-
der full software control
Below the input threshold voltage, it is in static
safe reset
In these conditions, secure operation is guaran-
teed without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Figure 12. Low Voltage Detector Reset
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5.3 RESET
5.3.1 Introduction
The MCU can be reset in three ways:
A low pulse input on the RESET pin
Internal Watchdog reset
Internal Low Voltage Detector (LVD) reset
5.3.2 RESET Sequence
The basic RESET sequence consists of 3 main
phases:
Internal (watchdog or LVD) or external Reset
event
A delay of 2048 clock (fINT) cycles
RESET vector fetch
The reset delay allows the oscillator to stabilise
and ensures that recovery has taken place from
the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
When a reset occurs:
The stack is cleared
The PC is loaded with the address of the Reset
vector. It is located in program ROM starting at
address 0FFEh.
A jump to the beginning of the user program must
be coded at this address.
The interrupt flag is automatically set, so that the
CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
Figure 13. RESET Sequence
1
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