CD74FCT540
BiCMOS OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS740 – JULY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
BiCMOS Technology With Low Quiescent
Power
D
Buffered Inputs
D
Inverted Outputs
D
Input/Output Isolation From VCC
D
Controlled Output Edge Rates
D
64-mA Output Sink Current
D
Output Voltage Swing Limited to 3.7 V
D
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D
Package Options Include Plastic
Small-Outline (M) Package and Standard
Plastic (E) DIP
description
The CD74FCT540 is an octal buffer/driver with 3-state ouputs that is ideal for driving bus lines or buffer memory
address registers and uses a small-geometry BiCMOS technology . The output stage is a combination of bipolar
and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering
of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and
minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output
configuration also enhances switching speed and is capable of sinking 64 mA.
The 3-state control gate is a two-input AND gate with active-low inputs, so that if either output-enable (OE1 or
OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide inverted data
when they are not in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT540 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS OUTPUT
OE1 OE2 AY
L L L H
LLH L
HXX Z
X H X Z
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
E OR M PACKAGE
(TOP VIEW)
CD74FCT540
BiCMOS OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS740 – JULY 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
A1 3
A2 4
A3
1
Y1
18
Y2
17
Y3
16
&EN
5
A4 6
A5 7
A6
Y4
15
Y5
14
Y6
13
19
OE1
OE2
8
A7 9
A8
Y7
12
Y8
11
1
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
218
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
DC supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input clamp current, IIK (VI < –0.5 V) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output clamp current, IOK (VO < –0.5 V) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output sink current per output pin, IOL 70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output source current per output pin, IOH –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC, ICC 140 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through GND 528 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): E package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
CD74FCT540
BiCMOS OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS740 – JULY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 2)
MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
IOH High-level output current –15 mA
IOL Low-level output current 64 mA
∆t/∆vInput transition rise or fall rate 0 10 ns/V
TAOperating free-air temperature 0 70 °C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN MAX
MIN
MAX
UNIT
VIK II = –18 mA 4.75 V –1.2 –1.2 V
VOH IOH = –15 mA 4.75 V 2.4 2.4 V
VOL IOL = 64 mA 4.75 V 0.55 0.55 V
IIVI = VCC or GND 5.25 V ±0.1 ±1
m
A
IOZ VO = VCC or GND 5.25 V ±0.5 ±10
m
A
IOS†VI = VCC or GND, VO = 0 5.25 V –60 –60 mA
ICC VI = VCC or GND, IO = 0 5.25 V 8 80
m
A
∆ICC‡One input at 3.4 V,
Other inputs at VCC or GND 5.25 V 1.6 1.6 mA
CiVI = VCC or GND 10 10 pF
CoVO = VCC or GND 15 15 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
‡This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating conditions, VCC = 5 V ±0.25 V (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C
MIN
MAX
UNIT
PARAMETER
(INPUT) (OUTPUT) TYP
MIN
MAX
UNIT
tpd AY6.4 2 8.5 ns
ten OE Y 7.5 2 10 ns
tdis OE Y 7.1 2 9.5 ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 1 V
VOH(V) Quiet output, minimum dynamic VOH 0.5 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
CD74FCT540
BiCMOS OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS740 – JULY 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 37 pF
CD74FCT540
BiCMOS OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCBS740 – JULY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
1.5 V1.5 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
(see Note B)
Output
W aveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V ≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
7 V
Open
7 V
TEST S1
3 V
0 V
1.5 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 7 V
500 ΩGND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V1.5 V
500 Ω
500 Ω
1.5 V 1.5 V
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.5 V
1.5 V 10%10% 90% 90% 3 V
0 V
trtf
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD74FCT540E OBSOLETE PDIP N 20 TBD Call TI Call TI
CD74FCT540M OBSOLETE SOIC DW 20 TBD Call TI Call TI
CD74FCT540M96 OBSOLETE SOIC DW 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Mar-2005
Addendum-Page 1
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