CS5330A-KSR - Cirrus Logic, Inc.

http://www.cirrus.com

8-Pin, Stereo A/D Converter for Digital Audio

Features

Single +5 V Power Supply

18-Bit Resolution

94 dB Dynamic Range

Linear Phase Digital Anti-Alias Filtering

– 0.05dB Passband Ripple

– 80dB Stopband Rejection

Low Power Dissipation: 150 mW

– Power-Down Mode for Portable

Applications

Complete CMOS Stereo A/D System

– Delta-Sigma A/D Converters

– Digital Anti-Alias Filtering

– S/H Circuitry and Voltage Reference

Adjustable System Sampling Rates including

32kHz, 44.1 kHz & 48kHz

General Description

The CS5330A /31A is a comple te stereo an alog-t o-digi-

tal converter that performs anti-alias filtering, sampling

and analog-to-digital conversion generating 18-bit val-

ues for both left and right inputs in serial form. The

output sample rate can be infinitely adjusted between

2 kHz and 50 kHz.

The CS5330A/31A operates from a single +5 V supply

and requires only 150 mW for normal operation, making

it ideal for battery-powered applications.

The ADC uses delta-sigma modulatio n with 128X over-

sampling, followed by digital filtering and decimation,

which removes the need for an external anti-alias filter.

The linear-phase digital filter has a passband to

21.7 kHz, 0.05 dB passband ripple and >80 dB stop-

band rejection. The de vice also contains a high-pass fil-

ter to remove DC offsets.

The device is available in an 8-pin SOIC package in

both Commeri cal (-10° to +70° C) and Automotive grades

(- 40° to +85° C). Please refer to “Ordering Information”

on page 16 for complete details.

High

Pass

Filter

AINR

S/H

GND

AINL

S/H

DAC

Serial Output Interface

Voltage Reference

Comparator

LP Filter

VA+

SCLK

Digital Decimation

Filter

SDAT

MCLK

DAC

High

Pass

Filter

LRCK

423

Digital Decimation

Filter

APRIL '06

DS138F5

CS5330A/31A

2DS138F5
CS5330A/31A
TABLE OF CONTENTS
1.  PIN DESCRIPTIONS .............. ... ... ................ .... ... ... ... .... ................ ... ... ... .... ... ................ ... ........ 3
2.  CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
SPECIFIED OPERATING CONDITIONS................................................................................. 4
ABSOLUTE MAXIMUM RATINGS........................................................................................... 4
ANALOG INPUT CHARACTERISTICS.................................................................................... 5
DIGITAL CHARACTERISTI CS......................... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... .... . 6
DIGITAL FILTER CHAR ACTERI S TI CS ........... ... ... ... .... ... ... ... .... ................ ... ... ... ................ .... . 6
SWITCHING CHARACTERI S TI CS........... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ........... 7
3.  GENERAL DESCRIPTION ........... .... ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ................ ... .... . 9
3.1 System Design  .................................................................................................................. 9
3.1.1 Master Clock ......................................................................................................... 9
3.1.2 Serial Data Interface  ............................................................................................ 9
3.1.3 Master Mode ......................................................................................................... 9
3.1.4 Slave Mode ......................................................................................................... 10
3.1.5 CS5330A ............................................................................................................. 10
3.1.6 CS5331A ............................................................................................................. 10
3.1.7 Analog Connections ............................................................................................ 11
3.1.8 High-Pass Filter  .................................................................................................. 11
3.1.9 Initialization and Power-Down ....... ... ................................................................... 11
3.1.10 Grounding and Power Supply Decoupling ........................................................ 12
3.1.11 Digital Filter .................... ... ... ... .... ... ................ ... .... ... ... ... ... .... ................ ... ... ... ... 13
4.  PARAMETER DEFINITIONS .................................................................................................. 14
5.  REFERENCES ........................................................................................................................ 15
6.  PACKAGE DESCRIPTIONS  .................................................................................................. 15
7.  ORDERING INFORMATION   ....... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ... 16
8.  REVISION HISTORY .............................................................................................................. 16
LIST OF FIGURES
Figure 1. Typical Connection Diagram......................................................................................... 8
Figure 2. Data Output Timing-CS5330A.... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ... 10
Figure 3. Data Output Timing - CS5331A (I²S Compatible)....................................................... 10
Figure 4. CS5330A/31A Initialization and Power-Down Sequence... ... ... ... .... ... ... ... .... ... ... ... ... ... 12
Figure 5. CS5330A/31A Digital Filter Stopband Rejection............. ... ... ... ... .... ... ... ... .... ... ... ... ... ... 13
Figure 6. CS5330A/31A Digital Filter Transition Band............................................................... 13
Figure 7. CS5330A/31A Digital Filter Passband Ripple............................................................. 13
Figure 8. CS5330A/31A Digital Filter Transition Band............................................................... 13
LIST OF TABLES
Table 1. Common Clock Frequencies......................................................................................... 9

DS138F5 3

CS5330A/31A

1. PIN DESCRIPTIONS

Pin Name #Pin Description

SDATA 1Audio Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this

pin. A 47 kΩ resistor on this pin will place the CS5330A/31A into Master Mode.

SCLK 2Serial Dat a Clock (Input/Output) - SCLK is an inpu t clock at any frequen cy from 32x to 64x the

output word rate. SCLK can also be an output clock at 64x if in the Master Mode. Data is

clocked out on the falling edge of SCLK.

LRCK 3

Left/Right Clock (Input/Output) - LRCK selects the left or right channel for output on SDATA.

The LRCK frequency must be at the output sample rate. LRCK is an output clock if in Master

Mode. Although the output s o f each channel a re transmitted at dif fer ent times, the two words in

an LRCK cycle represent simultaneously sampled analog inputs.

MCLK 4Master Clock Input (Input) - Source for the de lta-sigma modulator sampling and digital filter

clock. Sample rates and digital filter characteristics scale to the MCLK frequency.

AINR 5Analog Right Channel Input (Input) - Analog input fo r the righ t ch an ne l. Typically 4 Vpp for a

full-scale input signal.

AGND 6Analog Ground (Input) - Analog ground reference.

VA+ 7Positive Analog Power (Input) - Positive analog supply (Nominally +5 V).

AINL 8Analog Left Channel Input (Input) - Analog input for the left channel. Typically 4 Vpp for a full-

scale input signal.

72 63 54

ERIAL DATA OUTPUT

SERIAL DATA CLOCK

LEFT/RIGHT CLOCK

MASTER CLOCK

LEFT ANALOG INPUT

ANALOG POWER

ANALOG GROUND

RIGHT ANALOG INPU

SDATA

SCLK

LRCK

MCLK

AINL

VA+

AGND

AINR

4DS138F5

CS5330A/31A

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance character istic s an d spe cif icat ion s ar e de riv e d from measurements taken at nominal supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(AGND = 0V, all voltages with respect to ground)

ABSOLUTE MAXIMUM RATINGS

(AGND = 0V, all voltages with respect to ground.) (Note 1)

Notes: 1. Operation at or beyo nd these lim its may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

2. Any Pin except supplies. Transient current of up to +/- 100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Unit

Analog Supply Voltage VA+ 4.75 5.0 5.25 V

Ambient Operating Temperature (Power Applied) KS, KSZ

BS, DS TA-10

-40 -

-+70

+85 °C

°C

Parameter Symbol Min Typ Max Unit

Analog Supply Voltage VA+ -0.3 - +6.0 V

Input Current, Any Pin Except Supplies (Note 2) lin - - ±10 mA

Analog Input Voltage (Note 3) VINA -0.7 - VA+0.7 V

Digital Input Voltage (Note 3) VIND -0.7 - VA+0.7 V

Ambient Temperature (power applied) TA-55 - +125 °C

Storage Temperature Tstg -65 - +150 °C

DS138F5 5

CS5330A/31A

ANALOG INPUT CHARACTERISTICS

(-1 dBFS Input Sinewave, 997 Hz; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Logic

0 = 0V, Logic 1 = VD+)

4. Referenced to typical full-scale inpu t voltage.

5. Internal highpass filter removes offset.

Parameter Symbol 5330A/31A-KS/KSZ

Min Typ Max 5331A-DSZ

Min Typ Max Unit

Dynamic Performance

Dynamic Range A-weighted

unweighted 88

86 94

92 -

-86

84 94

92 -

-dB

Total Harmonic Distortion + Noise

(Note 4) -1 dB

-20 dB

-60 dB

THD+N -

-84

-72

-32

-84

-72

-32

Total Harmonic Distortion -1 dB THD - 0.003 0.02 - 0.003 0.2 %

Interchannel Phase Deviation -0--0-Degree

Interchannel Isolation (dc to 20 kHz) -90--90-dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Error --±10--±10%

Gain Drift - 150 - - 150 - ppm/°C

Offset Error (Note 5) --0--0LSB

Analog Inpu t

Full-scale Input Voltage VIN 3.6 4.0 4.4 3.6 4.0 4.4 Vpp

Input Impedance (Fs = 48 kHz) ZIN - 100 - - 100 - kΩ

Input Bias Voltage 2.2 2.4 2.6 2.2 2.4 2.6 V

Power Supplies

Power Supply Current VA+

Power down IA+ -

-30

100 42

1000 -

-30

100 42

1000 mA

µA

Power Dissipation Normal

Power down -

-150

0.5 220

5.25 -

-150

0.5 220

5.25 mW

Power Supply Rejection Ratio PSRR - 50 - - 50 - dB

* Refer to Parameter Definitions at the end of this data sheet.

6DS138F5

CS5330A/31A

DIGITAL CHARACTERISTICS

DIGITAL FILTER CHARACTERISTICS

(FS = 48 kHz)

6. Filter characteristics scale with output sample rate.

7. The analog modulato r samples the input at 6.144 MHz for an output sample ra te of 48 kHz. There is no

rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.7 kHz where

n = 0,1,2,3…).

8. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 312µs.

Parameter Symbol Min Typ Max Unit

High-Level Input Voltage VIH 2.4 - - V

Low-Level Input Voltage VIL --0.8V

High-Level Output Voltage at lo = -20 µA VOH VA-1.0 - - V

Low-Level Output Voltage at lo = 20 µA VOL --0.4V

Input leakage Current Iin - - ±10.0 µA

Parameter Symbol Min Typ Max Unit

Passband (0.05) (Not e 6) 0.02 - 21.7 kHz

Passband Ripple --±0.05dB

Stopband (Note 6) 29 - 6115 kHz

Stopband Attenuation (Note 7) 80 - - dB

Group Delay (Note 8) tgd -15/Fs-s

Group Delay Variation vs. Frequency ∆tgd --0µs

High Pass Filter Characteristics

Frequency Response: -3 dB (Note 6)

-0.1 dB -

-3.7

20 -

-Hz

Phase Deviation @ 20 Hz (Note 6) - 10 - Degree

Passband Ripple --0dB

DS138F5 7

CS5330A/31A

SWITCHING CHARACTERISTICS

(Inputs: Logic 0 = 0V, Logic 1 = VA+; CL = 20 pF) Switchin g characte ristics are g uarante ed by char acterization.

10.

11.

Parameter Symbol Min Typ Max Unit

Output Sample Rate Fs 2 - 50 kHz

MCLK Period MCLK/LRCK = 256 tclkw 78 - 1000 ns

MCLK Low MCLK/LRCK = 256 tclkl 31 - 1000 ns

MCLK High MCLK/LRCK = 256 tclkh 31 - 1000 ns

MCLK Period MCLK/LRCK = 384 tclkw 52 - 1000 ns

MCLK Low MCLK/LRCK = 384 tclkl 20 - 1000 ns

MCLK High MCLK/LRCK = 384 tclkh 20 - 1000 ns

MCLK Period MCLK/LRCK = 512 tclkw 39 - 1000 ns

MCLK Low MCLK/LRCK = 512 tclkl 13 - 1000 ns

MCLK High MCLK/LRCK = 512 tclkh 13 - 1000 ns

MASTER MODE

SCLK falling to LRCK tmslr -10 - 10 ns

SCLK falling to SDATA valid tsdo -10 - 35 ns

SCLK Duty cycle -50-%

SLAVE MODE

LRCK duty cycle 25 50 75 %

SCLK Period tclkw (Note 9) --ns

SCLK Pulse Width Low tclkl (Note 10) --ns

SCLK Pulse Widt h High tclkh 20 - - ns

SCLK falling to SDATA valid tdss - - (Note 11) ns

LRCK edge to MSB valid tlrdss - - (Note 11) ns

SCLK rising to LRCK edge delay tslr1 20 - - ns

LRCK edge to rising SCLK setup time tslr2 (Note 11) --ns

64 Fs

128 Fs- 15 ns

256 Fs+ 5 ns

8DS138F5

CS5330A/31A

C LK out put

SDATA

sdo

RCK output

tmslr

SCLK to SDATA LRCK - MASTER mode ( CS5330A)

CLK output

mslr

SDATA

sdo

RCK output

SCLK to SDATA LRCK - MASTER mode (CS5331A)

SDATA

SC LK input

(

SLAVE mode)

(

SLAVE mode)

LRCK input

sclkh

MSB MSB-

sclkl

slr1

tslr2

sclkw

SCLK to LRCK & SDATA - SLAVE mode (CS5331A)

SDATA

SC LK input

(

SLAVE mode)

(

SLAVE mode)

LRCK input

sclkh

MSB MSB-1 MSB-

lrdss

sclkl

slr1

tslr2

sclkw

SCLK to LRCK & SDATA - SLAVE mod e (CS5330A)

Analog

Input

Circuits

VA+

AGND

+5V

Analog

AINL

AINR

+0.1

CS5330A

CS5331A

LRCK

MCLK

SCLK

150

Ω

SDATA

47 k

Ω

.01

150

Ω

.01

F1 k

Ω

1 k

Ω

1 k

Ω

1 k

Ω

.47

Required for Master mode only

Optional if analog input circuits biased

to within ± 5% of CS5330A/CS5331A

nominal input bias voltage

Audio Data

Processor

Timing

Logic

Clock

Figure 1. Typica l Connection Diagram

DS138F5 9

CS5330A/31A

3. GENERAL DESCRIPTION

The CS5330A and CS5331A are 18-bit, 2-channel Analog-to-Digital Converters designed for digital audio applica-

tions. Each device u ses two on e-bit delta- sigma modu lators which simulta ne-ously sample the an alog input signals

at 128 times the output sample rate (Fs). The resulting serial b it streams are di gitally filtered, yielding pairs of 18-bit

values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude.

The converters do not require difficult-to-design or expensive anti-alias filters and do not require external sample-

and-hold amplifiers or a voltage reference.

The CS5330A and CS5331A differ only in the output seria l da ta format. The se formats are dis-cusse d in the follow-

ing sections and sh ow n in Figures 2 and 3.

An on-chip voltage reference provides for a single-ended input signal range of 4.0 Vpp. Output data is available in

serial form, coded as 2’s complement 18-bit n umbers. Typical power con-sumption is 150 mW which can be further

reduced to 0.5 mW using the Power-Down mode.

For more information on delta-sigma modulation, see the references at the end of this data sheet.

3.1 System Design

Very few external components are requir ed to support the ADC. Normal power supply de co u- pling compo-

nents and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1.

3.1.1 Master Clock

The master clock (MCLK) runs the digital filter and is used to generate the delta-sigma modula-tor sam-

pling clock. Table 1 shows some common master clock frequencies. The output sample rate is equal to

the frequency of the Left / Right Clock (LRCK). Th e serial nature of the output da ta results in the left and

right data words b eing read at differe nt times. However, the wo rds within an LRCK cycle re present simul-

taneously sampled analog inputs. The serial clock (SCL K) shifts the digi tized audio data from the in ternal

data registers via the SDATA pin.

3.1.2 Serial Data Interface

The CS5330A and CS5331A can be operated in either Master mode, where SCLK and LRCK are outputs,

or SLAVE mode, where SCL K and LRCK are inputs.

3.1.3 Master Mode

In Master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The CS5330A/31A

will divide MCLK by 4 to generate a SCLK which is 64× Fs and by 256 to generate LRCK. The CS5330A

and CS5331A can be placed in the Master mode with a 47 kohm pull-down resistor on the SDATA pin as

shown in Figure 1.

LRCK

(kHz)

MCLK (MHz)

256x 384x 512x

32 8.1920 12.2880 16.3840

44 11.2896 16.9344 22.5792

48 12.2880 18.4320 24.5760

Table 1. Common Clock Frequencies

10 DS138F5

CS5330A/31A

3.1.4 Slave Mode

LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLK and be

equal to Fs. The frequency of SCLK should be equal to 64x LRCK, though other frequencies are possible.

MCLK frequencies of 256x, 384x, and 512x Fs are supported. The ratio of the applied MCLK to LRCK is

automatically detecte d during power-up and intern al dividers are set to ge nerate the ap-propr iate internal

clocks.

3.1.5 CS5330A

The CS5330A data output format is shown in Figure 2. Notice that the MSB is clocked by the transition of

LRCK and the remaining seventeen data bits are clocked by the falling edge of SCLK. The data bits are

valid during the rising edge of SCLK.

3.1.6 CS5331A

The CS5331A data output format is sh own in Figure 3. Notice the one SCLK peri od delay be-twee n the

LRCK transitions and the MSB of the data. The falling edges of SCLK cause the ADC to output the eigh-

teen data bits. The data bits are valid durin g the ri sing edge of SCL K. LRCK is also inver ted compared to

the CS5330A interface. The CS5331A inte rface is compatible with I2S.

18 19 20 21 22

31 0 1

18 19 20 21 22 23

31 0 1

CLK

RCK

Left Audio Data Right Audio Data

17 16

DATA

17 17

Figure 2. Data Output Timing-CS5330A

18 19 20 21 22 31

18 19 20 21 22 23

31 0 1

CLK

RCK

Left Audio Data Right Audio Data

17 16

DATA

3 3

Figure 3. Data Output Timing - CS5331A (I²S Compatible)

DS138F5 11

CS5330A/31A

3.1.7 Analog Connections

Figure 1 shows the analog input connections. The analog inputs are presented to the modula-tors via the

AINR and AINL pins. Each analog input will accept a maximum of 4 Vpp centered at +2.4 V.

The CS5330A/31A samples the analog inputs at 128 × Fs, 6.144 MHz for a 48 kHz sample-rate. The dig-

ital filter rejects all noise above 29 kHz except for frequencies right around 6.144 MHz ±21.7 kHz (and

multiples of 6.144 MHz). Most audio signals do not have significant energy at 6.144 MHz. Nevertheless,

a 150 Ω resistor in series w ith each analog input and a 10 nF capacitor across the inputs will attenuate

any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modula-

tors. The use of capacitors which have a large voltage coefficient must be avoided since thes e will de-

grade signal linearity. It is also important that the self-resonant frequency of the capacitor be well above

the modulator sampling frequency. General purpose ceramics and film capacitors do not meet these re-

quirements. However, NPO and COG capacitors are acceptable. If active circuitry precedes the ADC, it

is recom-mended that the above RC filter is placed between the active circuitry and the AINR and AINL

pins. The above example frequencies scale linearly with Fs.

3.1.8 High-Pass Filter

The operational amplifiers in the input circuitry driving the CS5330A/31A ma y ge nerate a small DC o ffset

into the A/D conv erter. The CS533 0A/31A includes a high pass filter after the decimator to remove any

DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between

de-vices in a multichannel system.

The characteristics of this first-order high pass filter are outlined in the “Digital Filter Characteristics” on

page 6

3.1.9 Initialization and Power-Down

The Initialization and Power-Down sequence is shown in Figure 4. Upon initial power-up, the digital filters

and delta-sigma modulators are reset and the internal voltage reference is powered down. The device will

remain in the Initial Power-Down mode until MCLK is presented. Once MCLK is available, the

CS5330A/31A will make a master/slave mode decision based upon the presence/absence of a 47 kohm

pull-down resistor on SDATA a s shown in Figure 1. The master/slave decision is made during initial pow-

er-up as shown in Figure 4.

In master mode, SCLK and LRCK are outputs where the MCLK/LRCK frequency ratio is 256x. LRCK will

appear as an outpu t 127 MCLK cycles into the initializa tion sequence. At this time, power is applied to the

internal voltage reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static low

during the initialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235

ms at a 48 kHz output sample rate).

In slave mo de , SC LK and LRCK a re in pu ts whe r e t h e MCLK/LRCK frequency ratio must be either 256x,

384x, or 51 2x. Once the MCLK and L RCK are detected, MCLK o ccurr ences are counted over one L RCK

period to determine th e MCLK/LRCK frequency ra tio. At this time, power is applied to the internal voltage

reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static high during the ini-

tialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kHz

sample rate).

12 DS138F5

CS5330A/31A

The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW.

This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the

MCLK pin in Master Mode. The initialization sequence will begin when MCLK, and LRCK for slave mode,

are restored. In slave mode power-down, the CS5330A and CS5331A will adapt to changes in

MCLK/LRCK frequency ratio during the initialization sequence. It is recommended that clocks not be ap-

plied to the device pr ior to powe r supply settling. A reset cir cuit may be implemen ted by gating the MCL K

signal.

3.1.10 Grounding and Power Supply Decoupling

As with any high resolution converter, the ADC requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-

rangements with VA+ connected to a clean +5V supply. Decoupling capacitors should be as near to the

ADC as possible, with the low value ceramic capacitor being the nearest. To minimize digital noise, con-

nect the ADC digital outputs only to CMOS inputs. The printed circuit board layout should have separate

analog and digital regions and ground planes. An evaluation board, CDB5330A or CDB5331A, is avail-

able which demonstrates the optimum layout and power supply arrangements, as well as allowing fast

evaluation of the CS5330A and CS5331A.

USER: Apply Power

Initial Power-Down

USER: Apply MCLK

Master M ode S lave M ode

Master/Slave

Decision

Master Mode

Power Down

MCLK/LRCK Ratio

is 256x onl y

USER: Remove

MCLK

Initialization

- High pas s filter settings

- SDATA mute released

Digital Output

is gene rated

Slave M ode

Power Down

MCLK/LRCK Ratio

Determination

256/384/512

Initialization

- High p

as s filter setting

- SDATA mute released

Digital Output

is G ene rated

USER: Remove

MCLK, LRCK or Bot

USER: Apply MCLK

and LR C K

Figure 4. CS5330A/31A Initializatio n an d Power-Down Sequence

DS138F5 13

CS5330A/31A

3.1.11 Digital Filter

Figures 5 through 8 sh ow the attenuation char acteristics of the digital filter included in the ADC. The filter

response scales linearly with sample rate. The x-axis has been normalized to Fs, and can be scaled by

multiplying the x-axis by the system sample rate, i.e. 48 kHz.

-10

-20

-30

-40

-50

-60

-70

-80

-90

100

110

120

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Normalized Input Frequency

-2

-4

-6

-8

-10

.46 .47 .48 .49 .50 .51 .52 .53 .5

Magnitude (dB)

Normalized Input Frequency

Figure 5. CS5330A/31A Digital Filter Stopband Rejection Figure 6. CS5330A/31A Digital Filte r Transition Band

0.05

0.04

0.03

0.02

0.01

0.00

0.01

0.02

0.03

0.04

0.05 0 0.1 0.2 0.3 0.4 0

Normalized Input Frequency

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

-70.0

-80.0

-90.0

100.00.40 0.45 0.50 0.60 0.65 0.7

Normalized Input Frequency

Figure 7. CS5330A/31A Digital Filter Passband Ripple Figure 8. CS5330A/31A Digital Filter Transition Band

14 DS138F5

CS5330A/31A

4. PARAMETER DEFINITIONS

Resolution

The total number of possible output codes is equal to 2 N, where N = the number of bits in the output word

for each channel.

Dynamic Range

The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is then added to the resultin g measurement to refer the measureme nt to full

scale. This technique ensu res that the distortion components are be low the noise level and do not effect the

measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion+Noise (THD+N)

The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Total Harmonic Distortion

The ratio of the rms sum of all harmonics up to 20 kHz to the rms value of the signal.

Interchannel Phase Deviation

The phase difference between the left and right channel sampling times.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s

output with the input under test AC grounded and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decib els.

Gain Error

The deviation of the measured full-scale amplitude from the ideal full-scale amplitude value.

Gain Drift

The change in gain value with temper ature. Units in ppm/°C.

Bipolar Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in LSBs.

DS138F5 15

CS5330A/31A

5. REFERENCES

1. Area Efficient Decimation Filter for an 18-Bit Delta- Sigma ADC, by K. Lin and J.J. Paulos. Paper pr esented

at the 98th Convention of the Audio Engineering Society, February 1995.

2. An 18-Bit, 8-Pin Stereo Digital -to-Analog Converter, by J.J. Paulos, A.W. Krone, G.D. Kamath and S.T. Du-

puie. Paper presented at the 97th Convention of the Audio Engineering Society, November 1994.

3. An 18-Bit Dual-Channel Oversampling Delta-Sig ma A/D Converter, with 19-Bit Mono App lication Example,

by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.

4. The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversam-

pling Delta Sigma ADC’s, by Steven Harris. Paper presented at the 87th Co nvention of the Audio Engine er-

ing Society, October 1989.

5. A Stereo 16-bit Delta-Sigma A/D Converte r for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swan-

son, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper pr esented at the 85th Convention of the Audio

Engineering Society, November 1988.

6. PACKAGE DESCRIPTIONS

Millimeters Inches

DIM MIN MAX MIN MAX

A 5.15 5.35 0.203 0.210

B 1.27 TYP 0.050 TYP

C 0 0.25 0 0.010

D 1.77 1.88 0.070 0.074

E 0.33 0.51 0.013 0.020

F .15 0.25 0.006 0.010

G0°8°0°8°

H 5.18 5.4 0.204 0.213

I 0.48 0.76 0.019 0.030

J 7.67 8.1 0.302 0.319

Note: The EIAJ Package is not a standard JEDEC package size.

8-Pin

SOIC

16 DS138F5

CS5330A/31A

7. ORDERING INFORMATION

8. REVISION HISTORY

Product Description Package Pb-Free Grade Temp Range Container Order #

CS5330A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC NO Commercial -10° to +70° C Bulk CS5330A-KS

Tape & Reel CS53 30A-KSR

CS5331A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC NO Commercial -10° to +70° C Bulk CS5331A-KS

Tape & Reel CS53 31A-KSR

CS5330A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC YES Commercial -10° to +70° C Bulk CS5330A-KSZ

Tape & Reel CS5330A-KSZR

CS5331A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC YES Commercial -10° to +70° C Bulk CS5331A-KSZ

Tape & Reel CS5331A-KSZR

CS5330A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC NO Automotive -40° to +85° C Bulk CS5330A-BS

Tape & Reel CS53 30A-BSR

CS5331A 8-pin, Stereo A/D Con-

verter for Digital Audio 8-SOIC YES Automotive -40° to +85° C Bulk CS5331A-DSZ

Tape & Reel CS5331A-DSZR

Release Changes

F5 Updated Ordering Information

Contacting Cirrus Logic Support

For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.

To find the one nearest to you, go to www.cirrus.com.

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