AD9172 Data Sheet
Rev. B | Page 48 of 145
Transport Layer Testing
The JESD204B receiver in the AD9172 supports the short
transport layer (STPL) test as described in the JESD204B
standard. Use this test to verify the data mapping between the
JESD204B transmitter and receiver. To perform this test, this
function must be implemented and enabled in the logic device.
Before running the test on the receiver side, the link must be
established and running without errors.
The STPL test ensures that each sample from each converter is
mapped appropriately according to the number of converters
(M) and the number of samples per converter (S). As specified
in the JESD204B standard, the converter manufacturer specifies
the test samples that are transmitted. Each sample must have a
unique value. For example, if M = 2 and S = 2, four unique
samples are transmitted repeatedly until the test is stopped. The
expected sample must be programmed into the device and the
expected sample is compared to the received sample one sample
at a time until all are tested. The process for performing this test
on the AD9172 is described as follows:
1. Synchronize the JESD204B link.
2. Enable the STPL test at the JESD204B Tx.
3. Depending on JESD204B case, there may be up to six
complex subchannels (M = 6), and each frame may contain
up to eight samples (S = 8). Configure the SHORT_TPL_
REF_SP_MSB bits (Register 0x32E) and the SHORT_TPL_
REF_SP_LSB bits (Register 0x32D) to match one of the
samples for one converter within one frame. For N = 12
modes, the expected sample value is multiplied by 16.
4. Set SHORT_TPL_M_SEL (Register 0x32C, Bits[3:2]) to
select the channel.
5. Set SHORT_TPL_IQ_SAMPLE_SEL (Register 0x32F,
Bit 6) to select the I or Q subchannel.
6. Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to
select the sample within one frame for the selected .
7. Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1.
8. Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to
1, then back to 0.
9. Wait for the desired time. The desired time is calculated as
1/(sample rate × BER). For example, given a bit error rate
of BER = 1 × 10−10 and a sample rate = 1 GSPS, the desired
time = 10 sec. Then, set SHORT_TPL_TEST_EN to 0.
10. Read the test result at SHORT_TPL_FAIL (Register 0x32F,
Bit 0).
11. Choose another sample for the same or another M to
continue with the test, until all samples for both converters
from one frame are verified.
Internal Loop Back Test
The AD9172 integrates one internal PRBS generator that can be
used to test the JESD204B PHYs without an external SERDES
signal input. The process for performing internal loopback
testing on the AD9172 is as follows:
1. Set the EQ_BOOST_PHYx bits (Register 0x240, Bits[7:0]
and Register 0x241, Bit[7:0]) to 0.
2. Set SEL_IF_PARDATAINV_DES_RC_CH bits
(Register 0x234, Bits[7:0]) to 0 to make sure lanes not
inverted.
3. Enable the loop back test for all lanes being tested by
writing to EN_LBT_DES_RC_CH (Register 0x250). Each
bit of Register 0x250 enables the loop back test for the
corresponding lane. For example, writing a 1 to Bit 0 enables
the test for Physical Lane 0.
4. For halfrate, set EN_LBT_HALFRATE_DES_RC
(Register 0x251, Bit 1) to 1; otherwise, set it to 0.
5. Toggle INIT_LBT_SYNC_DES_RC (Register 0x251, Bit 0)
from 0 to 1 then back to 0.
6. Refer to the PHY PRBS Testing section for information on
how to run a PRBS7 check.
Repeated CGS and ILAS Test
As per Section 5.3.3.8.2 of the JESD204B specification, the
AD9172 can check that a constant stream of /K28.5/ characters
is being received, or that CGS followed by a constant stream of
ILAS is being received.
To run a repeated CGS test, send a constant stream of /K28.5/
characters to the AD9172 SERDES inputs. Next, set up the
device and enable the links. Ensure that the /K28.5/ characters are
being received by verifying that SYNCOUT± is deasserted and
that CGS has passed for all enabled link lanes by reading
Register 0x470.
To run the CGS followed by a repeated ILAS sequence test,
follow the procedure to set up the links, but before performing
the last write (enabling the links), enable the ILAS test mode by
writing a 1 to Register 0x477, Bit 7. Then, enable the links. When
the device recognizes four CGS characters on each lane, it
deasserts the SYNCOUTx±. At this point, the transmitter starts
sending a repeated ILAS sequence.
Read Register 0x473 to verify that the initial lane synchronization
has passed for all enabled link lanes.
JESD204B ERROR MONITORING
Disparity, Not in Table, and Unexpected Control (K)
Character Errors
As per Section 7.6 of the JESD204B specification, the AD9172 can
detect disparity errors, not in table (NIT) errors, and unexpected
control character errors, and can optionally issue a sync request
and reinitialize the link when errors occur.
Several other interpretations of the JESD204B specification are
noted in this section. When three NIT errors are injected to one
lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback
values of the bad disparity error (BDE) count register is 1.
Reporting of disparity errors that occur at the same character
position of an NIT error is disabled. No such disabling is per-
formed for the disparity errors in the characters after an NIT
error. Therefore, it is expected behavior that an NIT error may
result in a BDE error.