| <> <> <> <> <> <> <> <> > GCLKBUF1 f L GCLKBUFO GCLKPAD1 GCLKPADO Figure 9: Global Clock Distribution Network gclkbu_2.eps 10 November 9, 1998 (Version 1.1 - ADVANCE)3 XILINX Boundary Scan Virtex devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that imple- ment the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP also supports two USERCODE instructions and internal scan chains Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including unbonded ones, are treated as independent 3- state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. Table 7 lists the boundary-scan instructions supported in Virtex FPGAs. Internal signals can be captured during EXTEST by connecting them to unbonded or unused IOBs. They may also be connected to the unused outputs of IOBs defined as unidirectional input pins. This technique partially compensates for the absence of INTEST support. Table 7: Boundary-Scan Instructions Boundary-Scan| Binary aa Command Code(4:0) Description EXTEST 00000 _ =s| Enables boundary-scan EXTEST operation SAMPLE 00001 Enables boundary-scan SAMPLE operation USRI 00010 |Access user-defined regis- ter 1 USR2 00011 Access user-defined reg- ister 2 CFG_OUT 00100 = |Access the configuration bus for Readback CFG_IN 00101 {Access the configuration bus for Configuration INTEST 00111 |Enables boundary-scan in- test operation USRCODE 01000 = |Enables shifting out USER code IDCODE 01001 Enables shifting out of ID Code HIZ 01010 = | Tri-states output pins while enabling the Bypass Reg- ister BUS_RST 01011 |Reset the Configuration Bus ; JSTART 01100 |Clock the startup se- quence when StartupClk is TCK BYPASS 11111 |Enables BYPASS RESERVED All other |Xilinx reserved instructions codes The public boundary-scan instructions are available prior to configuration. After configuration, the public instructions remain available together with any USERCODE instruc- tions installed during the configuration. While the SAMPLE and BYPASS instructions are available during configura- tion, it is recommended that boundary-scan operations not be performed during this transitional period. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. To facilitate internal scan chains, the User Register pro- vides three outputs (Reset, Update, and Shift) that repre- sent the corresponding states in the boundary-scan internal state machine. Development System Virtex FPGAs are supported by the Xilinx Foundation and Alliance CAE tools. The basic methodology for Virtex design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Syn- opsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xil- inx Design Manager (XDM) software, providing design- ers with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing (PAR) can be accessed through the XDM software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Virtex design. RPMs, for example, are schematic-based macros with rela- tive location constraints to guide their placement. They help ensure optimal implementation of common functions. For HDL design entry, the Xilinx FPGA Foundation devel- opment system provides interfaces to the following synthe- sis design environments. * Synopsys (FPGA Compiler, FPGA Express) * Exemplar (Spectrum) Synplicity (Synplify) For schematic design entry, the Xilinx FPGA Foundation and alliance development system provides interfaces to the following schematic-capture design environments. Mentor Graphics V8 (Design Architect, QuickSim Il) * Viewlogic Systems (Viewdraw) Third-party vendors support many other environments. November 9, 1998 (Version 1.1 - ADVANCE) 11Virtex 2.5 V Field Programmable Gate Arrays A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Virtex FPGAs supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumu- lators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. The soft macro portion of the library contains detailed descriptions of common logic functions, but does not con- tain any partitioning or placement information. The perfor- mance of these macros depends, therefore, on the partitioning and placement obtained during implementa- tion. RPMs, on the other hand, do contain predetermined parti- tioning and placement information that permits optimal implementation of these functions. Users can create their own library of soft macros or RRMs based on the macros and primitives in the standard library. The design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. These hierarchical design elements are auto- matically combined by the implementation tools. Different design entry tools can be combined within. a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. Design Implementation The place-and-route tools (PAR) automatically provide the implementation flow described in this section. The parti- tioner takes the EDIF netlist for the design and maps the logic into the architectural resources of the FPGA (CLBs and !OBs, for example). The placer then determines the best locations for these blocks based on their interconnec- tions and the desired performance. Finally, the router inter- connects the blocks. The PAR algorithms support fully automatic implementa- tion of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing informa- tion is optionally specified during the design-entry process. The implementation of highly structured designs can bene- fit greatly from basic floorplanning. The implementation software incorporates Timing Wizard timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines in PAR then recognize these user-specified requirements and accommodate them. Timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tai- lored to user-generated specifications. Specific timing infor- mation for individual nets is unnecessary. Design Verification In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. The development system supports both software simula- tion and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the netlist for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the TRACE static timing analyzer. For in-circuit debugging, the development system includes a download and readback cable. This cable connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifica- tions can be downloaded into the system in a matter of min- utes. Configuration Virtex devices are configured by loading configuration data into the internal configuration memory. Some of the pins used for this are dedicated configuration pins, while others may be re-used as general purpose inputs and outputs once configuration is complete. The dedicated pins are the mode pins (M2, M1, MO), the configuration clock pin (CCLK), the PROGRAM pin, the DONE pin and the boundary-scan pins (TDI, TDO, TMS, TCK). Depending on the configuration mode chosen, CCLK may be an output generated by the FPGA, or may be generated externally, and provided to the FPGA as an input. For a more detailed description than that given below, see the Supplementary Description on Configuration and Readback. Configuration Modes Virtex supports the following four configuration modes. Slave-serial mode e Master-serial mode SelectMAP mode Boundary-scan mode 12 November 9, 1998 (Version 1.1 - ADVANCE)$2 XILINX The Configuration mode pins (M2, M1, MO) select these configuration modes. The selection codes are listed in Table 8. Note that unlisted selection codes are reserved. Table 8: Configuration Codes Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. Configuration Mode | M2 | M1 | MO Dreeton wa ie Master-serial mode 0 6) 0 Out 1 Yes Boundary-scan mode 1 0 1 N/A 1 No SelectMAP mode 1 1 0 In 8 No Slave-serial mode 1 1 1 In 1 Yes Slave Serial Mode configuration chains. This change was made to improve In slave serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be setup at the DIN input pin a short time before each rising edge of an externally generated CCLK. Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed to the DOUT pin. The data on the DOUT pin changes on the ris- ing edge of CCLK. The capture of DIN on the rising edge of CCLK differs from previous families, but will not cause a problem for mixed seriai-configuration rates for Virtex only chains. Figure 10 shows a full master/slave system. A Virtex device in slave seria! mode should be connected as shown in the third device from the left Slave-serial mode is selected by applying <111> to the mode pins (M2, M1, MO). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. Figure 11 shows slave-serial configuration timing. Table 9 provides more detail about the characteristics shown in Figure 11. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. tL NC T LL MO Mi San MO M1 M2 NC ] M2 DOUT PP] DIN DouT -__ VIRTEX | coux MASTER XC1701L VIRTEX, SERIAL XC4000XL, CCLK PICK SLAVE DIN fad DATA ;] PROGRAM CE CEO >] PROGRAM DONE int <<> I RESETIOE | DONE INIT = (Low Reset Option Used) PROGRAM X9025_c Figure 10: Master/Slave Serial Mode Circuit Diagram November 9, 1998 (Version 1.1 - ADVANCE) 13Virtex 2.5 V Field Programmable Gate Arrays . a r+ ) Teer Xd CCLK 7 @Tecu t*@) Teco DOUT (Output) Figure 11: Slave Serial Mode Programming Switch Table 9: Slave Serial Mode Programming Switching X5379_a Description Symbol Units DIN setup/hold V/2 = |Tpee/Tecp| 2.0/0.0 | ns, min DOUT 3 Teco 9.0 ns, max CCLK High time 4 Tocu 5.0 ns, min Low time 5 Toc 5.0 ns, min Maximum Frequency Foc 66 MHz, max Master Serial Mode frequency, ensure that the serial PROM and any daisy- In master serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. The preamble is also forwarded to other devices in the daisy-chain. The interface is identical to slave serial except that an inter- nal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always starts at a slow default frequency. Con- figuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Switching to a lower fre- quency is prohibited. The CCLK frequency is set using the ConfigRate option in the bitstream generation software. When selecting a CCLK Table 10: Master Serial Mode Programming Switching chained FPGAs are fast enough to support this rate. Figure 10 shows a full master/slave system. In this system, the leftmost device operates in master-serial mode. The remaining devices operate in slave-serial mode. The SPROM RESET pin is driven by INIT, and CE input is driven by DONE. There is, therefore, the potential for con- tention on the DONE pin, depending on the start-up sequence options chosen. The sequence of operations necessary to configure a Vir- tex FPGA serially appears in Figure 12. Figure 13 shows the timing of master-serial configuration. Master serial mode is selected by a on the mode pins (M2, M1, MO). Tabie 10 shows the timing information for Figure 13 At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PRO- GRAM Low until Vcc is valid. Description Symbol Units CCLK DIN setup/hold 1/2 |Toscx/Tscxp| 2.0/0.0 | ns, min Note: Master serial mode timing is based on testing in slave mode. SelectMAP Mode The SelectMAP mode is the fastest configuration option. Byte-serial data is written into the FPGA with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If WRITE is not asserted, configuration data is read out of the FPGA as part of a readback operation. 14 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX FPGA starts to clear ______ configuration memory. FPGA makes a final ____ clearing pass and releases INIT when finished. Once a Frame, ___> FPGA checks data using CRC and pulls INIT Low on error. If no CRC errors found, _> Apply Power v Set PROGRAM = High v Release INIT Low High If used to delay configuration If used to delay configuration Load a Configuration Bit End of Bitstream? FPGA enters start-up phase causing DONE to go High. Configuration Completed Figure 12: Serial Configuration Flowchart CCLK (Output) @ "Hs X8793_a @) Toscx Serial Data In \ \ _X Serial DOUT x Xx (Output) =X Figure 13: Master Serial Mode Programming Switching Characteristics X3223_a November 9, 1998 (Version 1.1 - ADVANCE) 15Virtex 2.5 V Field Programmable Gate Arrays After configuration, the pins of the SelectMAP port can be used as additional user |/O. Alternatively, the port may be retained to permit high-speed 8-bit readback. Retention of the SelectMAP port is selectable on a design- by-design basis when the bitstream is generated. If reten- tion is selected, PROHIBIT constraints are required to pre- vent the SelectMAP-port pins from being used as user I/O. Multiple Virtex FPGAs can be configured using the Select- MAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. CCLK cs iO WRITE - ! DATAI7:0] = BUSY No Write Figure 14: SelectMAP Write Waveforms Write Write operations send packets of configuration data into the FPGA. The sequence of operations for a multi-cycle write operation is shown below. Note that a configuration packet can be split into many such sequences. The packet does not have to complete within one assertion of CS, illustrated in Figure 14. 1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or deasserted. Otherwise an abort will be initiated, as described below. 2. Drive data onto D[7:0}. Note that to avoid contention, the data source should not be enabled while CS is Low and Table 11: SelectMAP Write Timing Characteristics Write No Write X8796_b WRITE is High. Similarly, while WRITE is High, no more that one CS should be asserted. 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High from a previous write, the data is not be accepted. Acceptance will instead occur on the first clock after BUSY goes Low, and the data must be held until this has happened. 4. Repeat steps 2 and 3 until all the data has been sent. 5. Deassert CS and WRITE. A flowchart for the write operation appears in Figure 15. Note that if CCLK is slower than fecnyp, the FPGA will never assert BUSY, In this case, the above handshake is unnec- essary, and data can simply be entered into the FPGA every CCLK cycle. Description Symbol Units Do.7 Setup/Hold 1/2 Tsmoce/Tsmccp 2.0/0.0 ns, min CS Setup/Hold 34 Tsmescc/Tsmcccs| 2.0/0.0 ns, min CCLK WRITE Setup/Hold 5/6 Tsmocw/Tsmwec 2.0/0.0 ns, min BUSY Propagation Delay 7 TsmcKBY 9.0 ns, max Maximum Frequency fecNH 50 MHz, max with no handshake 16 November 9, 1998 (Version 1.1 - ADVANCE)$2 XILINX Apply Power FPGA starts to clear >- Y configuration memory. if used to delay a u io Set PROGRAM = High configuration FPGA makes 2 final a. p- y clearing pass and releases INIT when finished. Release INIT configuration INIT? >-Low High Set WRITE = Low Enter Data Source 1 Sequence A Set CS = Low On first FPGA Apply Configuration Byte Once a Frame, > FPGA checks data using CRC and pulls INIT Low on error. End of Data? Hf no errors, first FPGAs enter start-up phase releasing DONE. . Set CS = High On first FPGA I Y noe For any other FPGA later FPGAs enter start-up phase Repeat Sequence A y s releasing DONE. y Disable Data Source v Set WRITE = High When all DONE pins _ are released, DONE goes High and start-up sequences complete. Configuration Completed X8795_a Figure 15: SelectMAP Flowchart for Write Operation November 9, 1998 (Version 1.1 - ADVANCE) 17Virtex 2.5 V Field Programmable Gate Arrays Abort During a given assertion of CS, the user cannot switch from a write to a read, or vice-versa. This action causes the cur- rent packet command to be aborted. The device will remain BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word bounda- F Lz Ly aries, and the FPGA requires a new synchronization word prior to accepting any new packets. To initiate an abort during a write operation, deassert WRITE. At the rising edge of CCLK, an abort is initiated, as shown in Figure 16. X FPGA cik \ 7 \_ 5 cc \ wre \ paTA(7:o) [EK BUSY Figure 16: SelectMAP Write Abort Waveforms Boundary-Scan Mode In the boundary-scan mode, no non-dedicated pins are required, configuration being done entirely through the IEEE 1149.1 Test Access Port. Configuration through the TAP uses the special CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. The following steps are required to configure the FPGA through the boundary-scan port. 1. Load the CFG_IN instruction into. the boundary-scan instruction register (IR) . Enter the Shift-DR (SDR) state . Shift a standard configuration bitstream into TDI . Return to Run-Test-Idle (RTI) . Load the JSTART instruction into IR . Enter the SDR state . Clock TCK for the length of the sequence (the length is programmabie) 8. Return to RTI As noted above, configuration and readback is always available. The boundary-scan mode simply locks out the NO oO fF W TD Abort irl lr other modes. The boundary-scan mode is selected by a <101> on the mode pins (M2, M1, MO). Configuration Sequence The configuration of Virtex devices is a three-phase pro- cess. First, the configuration memory is cleared. Next, con- figuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user, as described below. The configu- ration process may also be initiated by asserting PRO- GRAM. The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire pro- cess is signalled by asserting DONE. Delaying Configuration Configuration of the FPGA can be delayed by holding the PROGRAM pin Low until the system is ready for the device to configure. During the memory clearance phase, the con- figuration sequences continuously cycles through the con- figuration memory clearing all addresses. This activity continues until the completion of one full address cycle after the PROGRAM pin goes High. Thus, configuration is delayed by extending the memory clearance phase. 18 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX Alternatively, INIT can be held Low using an open-drain driver. An open-drain is required since INIT is a bidirec- tional open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to act as if the configuration memory is stili being cleared. Thus, configuration is delayed by preventing entry into the phase where data is loaded. Start-Up Sequence The default Start-up sequence is that one CCLK cycle after DONE goes High, the global tri-state signal (GTS) is released. This permits device outputs to turn on as neces- sary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This per- mits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events may be changed. In addition, the GTS, GSR, and GWE events may be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start in synchronism. The sequence may also be paused at any stage until lock has been achieved on any or all DLLs. Data Stream Format Virtex devices are configured by sequentially loading frames of data.that have been concatenated into a bitstream. Table 12 tists the total number of bits required to configure each device. Table 12: Virtex Bit-stream Lengths Device # of Configuration Bits XCV50O 559,232 XCV100 781,248 XCV150 1,041,128 XCV200 1,335,872 XCV300 1,751,840 XCV400 2,546,080 XCV600 3,608,000 XCV800 4,715,584 XCV1000 6,127,772 Readback The configuration data stored in the Virtex configuration memory can be readback for verification. Along with the configuration data it is possible to readback the contents all flip-flops/latches, LUTRAMs, and block RAMs. This capa- bility is used for real-time debugging. For more detailed information contact the factory for a copy of the Supplementary Description on Configuration and Readback. November 9, 1998 (Version 1.1 - ADVANCE) 19Virtex 2.5 V Field Programmable Gate Arrays Pin Definitions Table 13: Special Purpose Pins Pin Name peated Direction Description GCKO, GCK1, Yes Input Clock input pins that connect to Global Clock Buffers. These GCK2, GCK3 pins become user inputs when not needed for clocks. MO, M1, M2 Yes Input Mode are pins used to specify the configuration mode. CCLK Yes Input or The configuration Clock 1/O pin: it is an input for SelectRAM and Output slave-serial modes, and output in master-serial mode PROGRAM Yes Input Initiates a configuration sequence when asserted Low. DONE Yes Output Indicates that configuration loading is complete, and that the start-up sequence is in progress. INI No Bidir When Low, indicates that the configuration memory is being (open-drain) | cleared. The pin becomes a user I/O after configuration. BUSY/ No Output In SelectMAP mode, BUSY controls the rate at which configura- DOUT tion data is loaded. The pin becomes a user I/O after configura- tion unless the SelectMAP port is retained. in bit-serial modes, DOUT provides preamble and configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration. DO/DIN, No Input In SelectMAP mode, DO-7 are configuration data input pins. D1, D2, These pins become user I/Os after configuration unless the Se- D3, D4, lectMAP port is retained. D5, D6, In bit-serial modes, DIN is the single data input. This pin be- D7 comes a user I/O after configuration. WRITE No Input In SelectMAP mode, the active-low Write Enable signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. cs No Input In SelectMAP mode, the active-low Chip Select signal. The pin becomes a user I/O after configuration unless the SelectMAP port is retained. TDI, TDO, Yes Mixed Boundary-scan Test-Access-Port pins, as defined in IEEE TMS, TCK 1149.1. DXN, DXP Yes N/A Temperature-sensing diode pins. (Anode: DXP, Cathode: DXN) Vocint Yes Input Power-supply pins for the internal core logic. Veco Yes Input Power-supply pins for the output drivers (subject to banking rules) VREF No Input Input threshold voltage pins. Become user I/Os when an exter- nal threshold voltage is not needed (subject to banking rules). GND Yes Input Ground 20 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX Virtex DC Characteristics Definition of Terms Data sheets may be designated as Advance or Preliminary. The status of specifications in these data sheets is as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Data sheets not identified as either Advance or Preliminary are to be considered final. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. All specifications are subject to change without notice. Virtex Absolute Maximum Ratings Symbol Description Units Vecint Supply voltage relative to GND -0.5 to 3.0 Vv Veco Supply voltage relative to GND -0.5 to 4.0 Vv VReF Input Reference Voltage -0.5 to 3.6 Vv Vin Input voltage relative to GND, differential inputs -0.5 to 3.6 Vv VIN Input voltage relative to GND, other pins -0.5 to 5.5 Vv Vis Voltage applied to 3-state output -0.5 to 5.5 Vv Vec Longest Supply Voltage Rise Time from 1 V to 3V 50 ms Tst Storage temperature (ambient) -65 to +150 c TsoL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 C r Junction temperature Ceramic packages +125 C Plastic packages 4125 C Notes: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Virtex Recommended Operating Conditions Symbol Description Min Max Units Vociny Supply voltage relative to GND, Ty = 0 C to +85C Commercial 2.5 - 5% 2.5+5% Vv Supply voltage relative to GND, Ty = -40C to +100C industrial 2.5 -5% 2.5+5% Vv Veco Supply voltage relative to GND, Ty = 0 C to +85C Commercial 3.6 Vv Supply voltage relative to GND, T, = -40C to +100C Industrial 3.6 Vv Tin Input signal transition time 250 ns Notes: Correct operation is guaranteed with a minimum Ver of 2.25 V (Nominal Vegiyt -10%). Below the minimum value stated above, all delay parameters increase by 3% for each 50-mV reduction in Vocint below the specified range. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of Voc. November 9, 1998 (Version 1.1 - ADVANCE) 21Virtex 2.5 V Field Programmable Gate Arrays Virtex DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Vorint | Data Retention Vecin7 Voltage (below which configuration data may be lost) 2.0 Vv VorIo Data Retention Vocg Voltage (below which configuration data may be lost) 1.2 v IcciIntq | Quiescent Vocint supply current (Note 1) mA locoa Quiescent Veco supply current (Note 1) mA lRer Vrer Current per Vref pin 20 pA I Input or output leakage current -10 +10 HA Cw Input capacitance (sample tested) | BGA, PQ, HQ, packages 8 pF lnpu Pad pull-up (when selected) @ V,, = 0 V, Veco = 3.3 V (sample tested) Note 2 0.25 mA lapp Pad pull-down (when selected) @ V;, = 3.6 V (sample tested) Note 2 0.15 mA Note 1: With no output current loads, no active input pull-up resistors, all I/O pins Tri-stated and floating. Note 2: Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. Virtex DC Input and Output levels Values for V\_ and Vi are recommended input voltages. Values for Vo, and Voy are guaranteed output voltages over the recommended operating conditions. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at minimum Veco with the respective Io, and Io, currents shown. Other standards are sample tested. Input/Output Vin Vin Voi Vou lo. lon Standard V, min V, max V, min V, max V, Max V, Min mA mA LVTTL (Note 1) 0.0 0.8 2.0 5.5 0.4 2.4 24 - 24 LVCMOS2 0.0 44% Vocint | 60% Vecint 5.5 10% Veco | 90% Veco 15 -0.5 PCI,3.3V -0.5 44% Vocint 60% Vecint Veco +0.5 10% Veco 90% Veco Note 2 Note 2 PCI, 5.0V -0.5 0.8 2.0 5.5 0.55 2.4 Note 2 Note 2 GTL 0.0 Vrer - 0.05 | Vaer + 0.05 3.6 0.4 na 40 n/a GTL+ 0.0 Veer -0.2 | Vag + 0.2 3.6 0.6 n/a 36 n/a HSTL | 0.0 Veer -0.1 | Veer + 0.1 3.6 0.4 Voco - 0.4 8 -8 HSTL Ill 0.0 Vrer- 0.1 | Vrer + 0.1 3.6 0.4 Voco - 0.4 24 -8 HSTL IV 0.0 Vrer -0.1 VReF +0.1 3.6 0.4 Veco - 0.4 48 8 SSTL3 |! 0.0 Vrer - VRer +0.2 3.6 Vrer -0.6 VREF +0.6 8 -8 SSTL3 Il 0.0 Vrer - Vrer +0.2 3.6 Vrer -0.8 VrRer +0.8 16 -16 SSTL2 l 0.0 VReEF - Vrer +0.2 3.6 Vrer - 0.45 Vaer + 0.45 6 -6 SSTL2 ll 0.0 Vrer -0.2 Vrer +0.2 3.6 Veer -0.6 VReF + 0.6 12 -12 CTT 0.0 Vrer-0.2 | Veer + 0.2 3.6 Vrer - 0.4 | Vrer + 0.4 8 -8 AGP 0.0 Veer: 0.2 | Var + 0.2 3.6 10% Veco | 90% Veco Note 2 Note 2 Note1: Voz. and Voy for lower drive currents are sample tested. Note 2: Tested according to the relevant specifications. 22 November 9, 1998 (Version 1.1 - ADVANCE)>: XILINX Virtex Switching Characteristics Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex devices unless otherwise noted. Virtex IOB Input Switching Characteristics Input delays associated with the pad are specified for LVTTL levels. For other standards, these delays typically vary by less than 0.3 ns. Precise values are provided by the timing analyzer. Speed Grade Description Symbol 6 | 5 | -4 Units Propagation Delays Pad to ! output, no delay Tiopi 0.8 0.9 1.0 ns, max Pad to | output, with delay Tiopip 1.4 1.6 1.8 ns, max Pad to output IQ via transparent latch, no delay Tiopul 1.7 1.9 2.2 ns, max Pad to output IQ via transparent latch, with delay Tiopuio 3.3 3.8 4.4 ns, max Sequential Delays Clock CLK to output IQ Tiockia 1.4 12 | 1.4 ns, max Setup and Hold Times with respect to Clock CLK Setup Time/Hold Time Pad, no delay Tiopick/TioicKe 1.9/0.0 2.2/0.0 2.5/0.0 ns, min Pad, with delay (Note 1} Tiopicko/NoicKrp 3.5/<0 4.1/<0 4.7/<0 ns, min ICE input Tioiceck/Tiockice 0.8/0.0 0.9/0.0 1.0/0.0 ns, min SR input (IFF, synchronous) TiosackyTiockisr 0.8/0.0 | 1.0/0.0 | 1.1/0.0 ns, min Set/Reset Delays SR input to !Q (asynchronous) Tiosria 1.2 1.4 1.6 ns, max GSR to output IQ Tasre ns, max Note 1: With delay, the IOB hold time is negative. This reduces or eliminates pad-to-pad hold time. Virtex Pad-to-Pad Switching Characteristics Output delays terminating at the pad are specified for LVTTL levels with 12 mA drive and slow slew rate (the default output standard). For other standards, these delays must be adjusted by adding the values shown in the Virtex |OB Output Switching Characteristics table. Speed Grade Description Symbol 6 5 -4 Units Using a DLL Pad-to-pad input data setup time before the clock ns, min Pad-to-pad input data hold time after the clock ns, min Pad-to-pad delay from clock input to data output ns, max Without a DLL Pad-to-pad input data setup time before the clock All ns, min Pad-to-pad input data hold time after the clock All ns, min Pad-to-pad delay from clock input to data output XCV50 ns, max XCV100 ns, max XCV150 ns, max XCV200 ns, max XCV300 ns, max XCV400 ns, max . XCV600 ns, max XCV800 ns, max XCV1000 ns, max November 9, 1998 (Version 1.1 - ADVANCE) 23Virtex 2.5 V Field Programmable Gate Arrays Virtex 1|OB Output Switching Characteristics Output delays terminating at the pad are specified for LVTTL levels with 12 mA drive and slow slew rate (the default output standard). For other standards, these delays must be adjusted by adding the values shown. Speed Grade Description Symbol 6 {| 5 | 4 Units Propagation Delays O input to Pad Tioop 41 5.3 6.1 ns, max O input to Pad via transparent latch Tioo-p 43 5.5 6.4 ns, max 3-State Delays T input to Pad high-impedance TiotHz 1.4 1.3 1.5 ns, max T input to valid data on Pad TioToN 5.0 5.8 6.6 ns, max T input to Pad high-impedance via transparent latch TIOTLPHZ 17 1.9 2.2 ns, max T input to valid data on Pad via transparent latch TIOTLPON 5.0 5.8 6.6 ns, max GTS to Pad high impedance Tets 5.0 5.8 6.7 ns, max Sequential Delays . . Clock CLK to Pad TiocKe 5.8 6.7 7.7 ns, max Clock CLK to Pad high-impedance (synchronous) TiockHz 2.1 2.4 2.8 ns, max Clock CLK to valid data on Pad (synchronous) TiockoN 5.8 6.7 7.7 ns, max Setup Times before Clock CLK O input Tioock 0.5 0.5 0.6 ns, min OCE input Tiooceck 0.8 0.9 1.0 ns, min SR input (OFF) Tiosracko 0.8 1.0 1.4 ns, min 3-State SetupTimes TCE input TiotcEcK 0.8 0.9 1.0 ns, min T input TiotcK 0.2 0.2 0.3 ns, min SR input (TFF) TiosRcCKT 0.8 1.0 11 ns, min Hold Times after Clock CLK Ley All Hold Times 0.0 0.0 0.0 ns, min Set/Reset Delays SR input to Pad (asynchronous) Tiosrp 5.0 5.8 6.6 ns, max SR input to Pad high-impedance (asynchronous) TiosRHz 2.3 2.6 3.0 ns, max SR input to valid data on Pad (asynchronous) TIoSRON 6.0 6.8 7.9 ns, max GSR to Pad Tesro ns, max Output Delay Adjustments Standard-specific increments for delays terminating at pads LVTTL, Slow, 2mA 13.3 15.2 17.5 ns 4mA 5.8 6.6 7.6 ns 6 mA 3.0 3.5 4.0 ns 8mA 1.2 1.4 1.6 ns 12mA 0.0 0.0 0.0 ns 16mA -0.2 -0.2 -0.3 ns 24mA - 0.6 -0.7 - 0.8 ns LVTTL, Fast, 2mA 11.5 13.3 15.3 ns 4mA 3.5 41 4.7 ns 6 mA 13 15 1.7 ns 8mA -0.9 -1.0 - 1.2 ns 12mA -1.9 -2.2 -25 ns 16 mA -2.0 -2.3 -2.7 ns 24 mA -2.3 -26 -3.0 ns LVCMOS2 -2.0 2.3 -2.7 ns PCI, 33 MHz, 3.3 V 0.3 0.4 0.4 ns PCI, 33 MHz, 5.0 V -0.9 1.41 -1.2 ns PCI, 66 MHz, 3.3 V -2.7 -3.1 -3.6 ns GTL -2.6 -3.0 -3.5 ns GTL+ - 1.9 -2.2 - 2.5 ns HSTL | -2.8, -3.2 -3.7 ns HSTL Ili -2.8 -3.3 -3.7 ns HSTL IV -3.0 - 3.4 -3.9 ns SSTL3 | -2.5 - 2.8 -3.3 ns SSTL3 II -3.0 -3.4 -3.9 ns SSTL2 | -2.4 -2.7 -3.2 ns SSTL2 II -2.8 -3.2 -3.7 ns CTT -2.5 -2.9 -3.4 ns AGP -2.8 -3.3 -3.8 ns 24 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX Virtex CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise values are provided by the timing analyzer. Speed Grade Description Symbol 6 | 5 | -4 Units Combinatorial Delays 4-input function: F/G inputs to X/Y outputs Tito 0.6 0.7 0.8 ns, max 5-input function: F/G inputs to F5 output Ties 1.0 11 1.2 ns, max 5-input function: F/G inputs to X output Tirsx 1.0 1.2 1.3 ns, max 6-input function: F/G inputs to Y output via F6 MUX Tirey 1.2 1.4 1.6 ns, max 6-input function: FSIN input to Y output TESINY 0.4 0.5 0.6 ns, max Incremental delay routing through transparent latch to XQ/YQ out- TIENCTL 0.4 0.5 0.6 ns, max puts BY input to YB output Tsyyp 0.5 0.6 0.7 ns, max Sequential Delays . . FF Clock CLK to XQ/YQ outputs Toxo 1.1 1.3 1.4 ns, max Latch Clock CLK to XQ/YQ outputs Texto 0.7 0.7 0.9 ns, max Setup Times before Clock CLK 4-input function: F/G Inputs Tick 1.0 1.4 1.2 ns, min -input function: F/G inputs Tirsck 1.4 1.6 1.8 ns, min 6-input function: FSIN input TrsiIncK 0.8 0.9 1.0 ns, min 6-input function: F/G inputs via F6 MUX Tireck 1.6 1.8 2.0 ns, min BX/BY inputs Toick 1.6 1.8 2.0 ns, min CE input Toeck 0.8 0.9 1.0 ns, min SR/BY inputs (synchronous) Trex 1.3 1.5 1.7 ns, min Hold Times after Clock CLK All Hold Times 0.0 | 0.0 0.0 | ns,min Clock CLK Minimum Pulse Width, High Tou 2.0 2.3 2.6 ns, min Minimum Pulse Width, Low : Tet 2.0 2.3 2.6 ns, min Set/Reset Minimum Pulse Width, SR/BY inputs Trew 2.9 3.4 3.9 ns, min Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) Tra 1.6 1.9 2.2 ns, max Delay from GSR to XQ/YQ outputs Teasra ns, max November 9, 1998 (Version 1.1 - ADVANCE) . 26Virtex 2.5 V Field Programmable Gate Arrays Virtex CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Speed Grade Description Symbol 6 | 5 | 4 Units Combinatorial Delays : F operand inputs to X via XOR Topx 0.8 0.9 1.0 ns, max F operand input to XB output Topxe 1.2 1.4 1.6 ns, max F operand input to Y via XOR Topy 1.6 1.9 2.2 ns, max F operand input to YB output Topys 1.3 15 1.7 ns, max F operand input to COUT output Topcyr 1.3 1.5 1.7 ns, max G operand inputs to Y via XOR Topey 1.0 1.41 1.3 ns, max G operand input to YB output Topays 1.4 1.6 1.9 ns, max G operand input to COUT output Topcye 1.4 1.6 1.8 ns, max BX initialization input to COUT Texcy 0.8 0.9 1.0 ns, max CIN input to X output via XOR . Toinx 0.5 0.5 0.6 ns, max CIN input to XB Toinxs 0.1 0.1 0.1 ns, max CIN input to Y via XOR Tony 0.5 0.6 0.7 ns, max CIN input to YB Tonys 0.2 0.2 0.2 ns, max CIN input to COUT output Tayp 0.1 0.2 0.2 ns, max Multiplier Operation , F1/2 operand inputs to XB output via AND TEANDXB 0.4 0.5 0.6 ns, max F1/2 operand inputs to YB output via AND TEANDYB 0.5 0.6 0.6 ns, max F1/2 operand inputs to COUT output via AND TEANDCY 0.5 0.5 0.6 ns, max G1/2 operand inputs to YB output via AND ToanbyB 0.4 0.4 0.5 ns, max Gi/2 operand inputs to COUT output via AND Toeanpcy 0.4 0.4 0.5 ns, max Setup Times before Clock CLK CIN input to FFX Tock 0.8 0.9 1.4 ns, min CIN input to FFY Tecxy 0.9 1.0 1.4 ns, min Setup Time Adjustment ns Hold Times after Clock CLK : All Hold Times 0.0 0.0 0.0 ns, min Virtex CLB SelectRAM Switching Characteristics Speed Grade Description Symbol 6 | 5 | -4 Units Sequential Delays : : Clock CLK to X/Y outputs (WE active) ns, max Shift-Register Mode Clock CLK to X/Y outputs TsycKo ns, max Setup Times before Clock CLK F/G address inputs Tas/TaH 0.6 0.7 0.8 ns, min BX/BY data inputs (DIN) Tos/Tou 1.0 1.2 1.3 ns, min CE input (WE) Tws/Twu 0.6 0.6 0.7 ns, min Shift-Register Mode BX/BY data inputs (DIN) Tsypick ns, min CE input (WS) TsHceck ns, min Hold Times after Clock CLK All Hold Times } 00 | 00 0.0 ns, min Clock CLK Minimum Pulse Width, High Tweu 2.9 3.4 3.9 ns, min Minimum Pulse Width, Low Twe 2.9 3.4 3.9 ns, min Minimum clock period to meet address write cycle time Twe 5.8 6.7 7.7 ns, min 26 November 9, 1998 (Version 1.1 - ADVANCE)22 XILINX Virtex BLOCKRAM Switching Characteristics Speed Grade Description Symbol 6 | 5 | -4 Units Sequential Delays Clock CLK to DOUT output Tacxo 33 | 38 | 44 ns, max Setup Times before Clock CLK ADDR inputs Teack 1.2 1.4 1.6 ns, min DIN inputs Tepck 1.2 1.4 1.6 ns, min EN input Tpeck 2.7 3.1 3.6 ns, min RST input Terck 2.5 2.9 3.3 ns, min WEN input Tewek 2.4 2.8 3.2 ns, min Hold Times after Clock CLK All Hold Times 0.0 0.0 0.0 ns, min Clock CLK Minimum-Pulse Width, High TeewH 2.0 2.3 2.6 ns, min Minimum Pulse Width, Low TapwL 2.0 2.3 2.6 ns, min CLKA -> CLKB setup time for different ports Teccs ns, min Virtex TBUF Switching Characteristics Speed Grade . Description Symbol 6 | 5 | -4 Units Combinatorial Delays IN input to OUT output Tio 0.2 0.2 0.2 ns, max TRI input to OUT output high-impedance Torr 0.2 0.2 0.2 ns, max Tri input to valid data on OUT output Ton 0.2 0.2 0.2 ns, max Virtex Clock Distribution Switching Characteristics Speed Grade Description Symbol 6 | 5 | -4 Units GCLK 1OB and Buffer Global Clock PAD to output. Tepip 1.0 1.4 1.3 ns, max IN input to OUT output Teio 0.9 1.0 1.2 ns, max Virtex Clock Distribution Guidelines Speed Grade Description Symbol 6 | 5 | -~4 Units GCLK Distribution From GCLK pad to any flip-flop XCV50 ns, max XCV100 ns, max Note: These ciock-distribution delays are pro- XCV150 ns, max vided for guidance only. They reflect the de- XCV200 ns, max lays encountered in a typical design under XCV300 ns, max worst-case conditions. Precise values for a XCV400 ns, max particular design are provided by the timing XCV600 ns, max analyzer. XCV800 ns, max XCV1000 ns, max Virtex Test Access Port Switching Characteristics Speed Grade Description Symbol 6 5 -4 Units TMS and TDI Setup times before TCK ns, min TMS and TDI Hold times after TCK ns, min Output delay from clock TCK to output TDO ns, max Maximum TCK clock frequency MHz, max 27 November 9, 1998 (Version 1.1 - ADVANCE)Virtex 2.5 V Field Programmabie Gate Arrays Virtex Pin Outs Pin-Out Tables Contact the factory for full pin-out listings of Virtex devices. For convenience, Table 14 and Table 15 list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os. Table 14: Virtex Pin-out Tables (Non-BGA) Pin Name Device PQ/HQ240 GCKO All 92 GCK1 . All 89 GCK2 All 210 GCK3 All 213 Mo All 60 M1 All 58 M2 All 62 CCLK All 179 PROGRAM Alt 122 DONE All 120 INIT All 123 BUSY/DOUT All 178 DO/DIN All 177 D1 All 167 D2 All 163 D3 All 156 D4 All 145 D5 All 138 D6 All 134 D7 All 124 WRITE All 185 cs All 184 TDI All 183 TDO All 181 Table 14: Virtex Pin-out Tables (Non-BGA) (Continued) Pin Name Device PQ/HQ240 TMS All 2 TCK All 239 Vecint All 16, 32, 43, 77, 88, 104, 137, 148, 164, 198, 214, 225 Veco . All 15, 30, 44, 61, 76, 90, 105, 121, 136, 150, 165, 180, 197, 212, 226, 240 Vrer, Bank 0 XCV50 218, 232 (VREF pins are listed in- XCV100/150 w+ 229 crementally. Connectall pins listed for both the XCV200/300 ... + 236 required device and all smaller devices listed in xcv400 +215 the same package.) XCV600 +230 | XCV800 .. + 222 Vrer, Bank 1 XCV50 191, 205 (Vrer Pins are listed in- XCV100/150 .. + 194 crementally. Connect all pins listed for both the XCV200/300 ve + 187 required device and all smaller devices listed in XCV400 + 208 the same package.) XCV600 we $198 XCV800 we +201 Vrer, Bank 2 XCV50 157, 171 (Vrer pins are listed in- XCV100/150 ... + 168 crementally. Connectall pins listed for both the XCV200/300 .. +175 required device and all smaller devices listed in XCV400 +154 the same package.) XCV600 . + 169 XCV800 .. + 161 28 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX Table 14: Virtex Pin-out Tables (Non-BGA) (Continued) Table 14: Virtex Pin-out Tables (Non-BGA) (Continued) Pin Name Device PQ/HQ240 VReF; Bank 7 (Veer Pins are listed in- crementally. Connectall pins listed for both the required device and alt smaller devices listed in the same package.) XCV50 9, 23 XCV100/150 +12 XCV200/300 +5 XCV400 .. +26 XCV600 +11 XCV800 w #19 GND All * 1, 8, 14, 22, 29, 37, 45, 51, 59, 69, 75, 83, 91, 98, 106, 112, 119, 129, 135, 143, 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233 Pin Name Device PQ/HQ240 Vrer, Bank 3 XCV50 130, 144 (Veer pins are listed in- XCV100/150 +133 crementally. Connectall pins listed for both the XCV200/300 + 126 required device and all smaller devices listed in XCV400 + 147 the same package.) XCV600 .. + 182 XCV800 . + 140 Vrer, Bank 4 XCV50 * 97,111 (Vrer pins are listed in- | XCV100/150 . + 108 crementally. Connectall pins listed for both the XCV200/300 we #115 required device and all smalier devices listed in XCV400 +94 the same package.) ~ XCV600 + 109 XCV800 .. +101 Vrer; Bank 5 XCV50 70, 84 (Vrer Pins are listed ine XCV100/150 +73 crementally. Connectall pins listed for both the XCV200/300 .. + 66 required device and all smaller devices listed in xCV400 +87 the same package.) XCV600 +72 XCV800 .. +80 Vrer, Bank 6 XCV50 36, 50 (Vper pins are listed in- XCV100/150 +47 crementally. Connect all pins listed for both the XCV200/300 .. + 54 required device and all smaller devices listed in xCV400 + 33 the same package.) ~ XCV600 . +48 XCV800 .. + 40 November 9, 1998 (Version 1.1 - ADVANCE) 29Virtex 2.5 V Field Programmable Gate Arrays Table 15: Virtex Pin-out Tables (BGA) Pin Name Device BG256 BG352 BG432 BGS560 GCKO All Y11 AE13 AL16 AL17 GCK1 All Y10 AF14 AK16 AJ17 GCK2 All A10 B14 A16 D17 GCK3 All B10 D14 D17 A17 Mo All Y1 AD24 AH28 AJ29 M1 All U3 AB23 AH29 AK30 M2 All we AC23 AJ28 AN32 CCLK All B19 C3 D4 C4 PROGRAM All Y20 AC4 AH3 AM1 DONE All wig AD3 AH4 AJ5 INIT All U18 AD2 AJ2 AH5 BUSY/DOUT All D18 E4 D3 D4 DO/DIN All C19 D3 C2 E4 D1 All E20 G1 K4 K3 D2 All G19 J3 K2 L4 D3 All J19 M3 P4 P3 D4 All Mi9 R3 V4 W4 D5 All P19 U4 AB1 AB5 D6 All T20 V3 AB3 AC4 D7 All v19 AC3 AG4 AJ4 WRITE All A19 D5 B4 D6 cs All B18 C4 D5 A2 TDI All C17 B3 B3 D5 TDO All A20 D4 C4 E6 TMS All D3 D23 D29 B33 TCK All Al C24 D28 E29 DXN All W3 AD23 AH27 | AK29 DXP All V4 AE24 AK29 AJ28 30 November 9, 1998 (Version 1.1 - ADVANCE)$< XILINX Table 15: Virtex Pin-out Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 Vecint XCV50/100/150/ C10, D6, A20, C14, 200 D15, F4, D10, J24, Incomentaly. Connect Fq7,L3, | Ka, Pe, all pins listed for both L18, Rd, P25, V24, the required device and R17, U6, We, AC10, allsmatiler devices listed U15, V10 AE14, AE19 in the same package.) XCV300 .. + B16, D12, A10, A17, Li, L25, B23, C14, . R23,T1, , C19, K3, AF1i1, AF16 K29, N2, N29, T1, T29, We, W31, AB2, AB30, AJ10, AJ16, AK13, AK19, AK22 XCV400/600 ... + B26, C7, A21, B14, F1, F30, B18, B28, AE29, AF1, C24, EQ, AH8, AH24 E12, F2, H30, J1, K32, N41, N33, U5, U30, Y2, Y31, AD2, AD32, AG3, AG31, AK8, AK11, AK17, AK20, AL14, AL27, AN25 XCV800/1000 ... + B12, C22, M3, N29, AB2, AB32, AJ13, AL22, Voco: Bank 0 All D7, D8 A17, B25, A21, C29, A22, A26, D19 D21 A30, B19, B32 Voco, Bank 1 Alt D13, D14 A10, D7, Al, A114, A10, A16, D13 D11 B13, C3, E5 Voco;: Bank 2 All G17, H17 B2, H4, C3, L1, B2, D1, Ki L4 H1, M1, R2 November 9, 1998 (Version 1.1 - ADVANCE) 31Virtex 2.5 V Field Programmable Gate Arrays Table 15: Virtex Pin-out Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 Veco, Bank 3 All N17, P17 P4, U1, AA1, AA4, V1, AA2, Y4 AJ3 AD1, AK1, AL2 Veco: Bank 4 All U13, U14 AC8, AE2, AH11, AL1, AN2, AM15, AF10 AL11 AN4, AN8, AN12 Veco; Bank 5 All U7, U8 AC14, AC20, AH21, AJ29, AL31, AM21, AF17 AL21 AN18, AN24, . AN3O Veco, Bank 6 All N4, P4 U26, W23, AA28, AA31, W832, AB33, AE25 AL31 AF33, AK33, AM32 Veco, Bank 7 Al G4, H4 G23, K26, A31, L28, C32, D33, N23 L31 K33, N32, T33 Vrer, Bank 0 XCV50 A8, B4 (Vrer pins are listed in- XCV100/150 + A4 A16,C19, crementally. Connect all C241 pins listed for both the required device and ail smaller devices listed in XCV200/300 .. +D21 B19, D22, the same package.) D24, D26 XCV400 .. + B15 . + C18 A19, D20, D26, E23, E27 XCV600 . + C24 . + E24 XCV800 .. + B21 .. + E21 XCV1000 . + D29 32 November 9, 1998 (Version 1.1 - ADVANCE)Table 15: Virtex Pin-out Tables (BGA) (Continued) 22 XILINX Pin Name Device BG256 BG352 BG432 BG560 Vrer, Bank 1 XCV50 A17, B12 (Vrer pins are listed in- XCV100/150 . + B15 B6, C9, crementally. Connect all C12 pins listed for both the required device and all XCV200/300 ... + DE A13, B7 smaller devices listed in C6 C1 0 the same package.) ; XCV400 $+ C13 .. + B15 A6, D7, D11, D16, E15 XCV600 ..+D10 .. +D10 XCV800 .. + B12 .. +D13 XCV1000 .. + E7 Vrer, Bank 2 XCV50 C20, J18 (VREF pins are listed in- XCV100/150 .. + F19 E2, H2, crementally. Connect all M4 pins listed for both the required device and all XCV200/300 + D2 E2, G3 smaller devices listed in J2. Nt the same package.) XCV400 + M1 .. +R3 G5, H4, L5, P4, Rt XCV600 . +H wt KS XCV800 .. + M3 a. + N5 XCV1000 .. + BS Veer, Bank 3 XCV50 M18, V20 (Vper pins are listed in- XCV100/150 .. + R19 R4, V4, crementally. Connect all Y3 Pins listed for both the required device and all XCV200/300 .. #AC2 V2, AB4 smaller devices listed in AD4 AF3 the same package.) XCV400 .+R1 . +U2 V4, W5, AD3, AE5, AK2 XCV600 . + AC3 + AFI XCV800 . +3 ... + AA4 XCV1000 .. + AH4 November 9, 1998 (Version 1.1 - ADVANCE) 33Virtex 2.5 V Field Programmable Gate Arrays Table 15: Virtex Pin-out Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 Vrer, Bank 4 XCV50 V12, Y18 (Vrer pins are listed in- XCV100/150 we + W185 AC12, AE5, crementally. Connectall AE8, pins listed for both the required device and all XCV200/300 w+ AES AJ7, AL4, smaller devices listed in AL8. AL13 the same package.) , XCV400 .. + AF12 .. + AKI5 AL7, AL10, AL16, AM4, AM14 XCV600 ... + AK8 .. + ALY XCV800 . AJ12 .. + AK13 XCV1000 .. + ANS Vrer, Bank 5 XCV50 v9, Y3 (Vrer Pins are listed in- XCV100/150 + WE AC15, AC18, crementally. Connectalt AD20 pins listed for both the required device and all XCV200/300 ... + AE23 AJ18, AJ25, smaller devices listed in AK23. AK27 the same package.) , XCV400 .. + AFI5 ... + AJI7 AJ18, AJ25, AL20, AL24, AL29 XCV600 .. + AL24 ... + AM26 XCV800 .. + AH19 .. + AN23 XCV1000 ... + AK28 Vrer, Bank 6 XCV50 M2, R3 (Veer pins are listed in- XCV100/150 +T1 R24, Y26, crementally. Connect all AA25, pins listed for both the ater once ae ain XCV200/300 ... + AD26 V28, AB28, the same package.) AESO, AF28 XCV400 .. + P24 ... + U28 V29, Y32, AD31, AE29, AK32 XCV600 ... + AC28 .. + AES1 XCV800 .. + 30 .. + AA30 XCV1000 ... + AH30 34 November 9, 1998 (Version 1.1 - ADVANCE)22 XILINX Table 15: Virtex Pin-out Tables (BGA) (Continued) Pin Name Device BG256 BG352 BG432 BG560 Vref, Bank 7 XCV50 G3, H1 (Vaer pins are listed in- XCV100/150 . +D1 D26, G26, crementally. Connect all L26 pins listed for both the required device and all XCV200/300 + E24 F28, F31, smaller devices listed in J30. N30 the same package.) , XCV400 wa & M25 .. + R31 E31, G31, . K31, P31, T31 XCV600 .. + J28 .. + H32 XCV800 ... + M28 .. +L33 XCV1000 .. +D31 GND All C3, C18, Al, A2, A2, A3, Al, A7, D4, D5, AS, A8, A7, AY, A12, A14, D9, D10, A14, A19, A14, A18, A18, A20, D1i1, D12, A22, A25, A23, A25, A24, A29, D16, D17. A26, Bt, A29, A30, A382, A33, E4, E17, B26, E1, B1, B2, B1, B6, J4, J9, E26, H1, B30, B31, BO, B15, J10, J11, H26, N1, Ci, C31, B23, B27, J12, J17, P26, W1, D16, G1, B31, C2, K4, KQ, W26, AB1, G31, Jt, E1, F382, K10, K14, AB26, AE1, J31, P1, G2, G33, K12, K17, AE26, AF1, P31, T4, J32, K1, L4, L9, AF2, AF5, T28, V1, L2, M33, L10,L11, AF8, AF 13, V31, AC1, P1, P33, L12, L17, AF 19, AF22, AC31, AE1, R32, T1, M4, M9, AF25, AF26 AE31, AH16, V33, W2, M10, M11, AJ1, AJ31, Y1, 33, M12, M17, AK1, AK2, AB1, AC32, T4, T17, AK30, AK31, AD33, AE2, U4, U5, AL2, ALS, AG1, AG32, U9, U10, AL7, AL9 AH2, AJ33, U11, U12, AL14, AL18 AL32, AM3, U16, U17, AL23, AL25, AM7, AM11, V3, V18 AL29, AL30 AM19, AM25, AM28, AM33, AN1, AN2, ANS, AN10, AN14, AN16, AN20, AN22, AN27, AN33 No Connect C31, AC2, AK4, AL3 November 9, 1998 (Version 1.1 - ADVANCE) 35Virtex 2.5 V Field Programmable Gate Arrays Pin-Out Diagrams The following diagrams, pages 37 through 41, illustrate the locations of special-purpose pins on Virtex FPGAs. Table 16: Pin-out Diagram Symbols Symbol Pin Function General I/O Vocint Device-dependent Vecint, n/c on smaller devices Veco VRer Device-dependent Vref, remains I/O on smaller devices @|~}| Dl) O| <| <| x Ground + Global Clocks e|8 wo Mo, M1, M2 8 9 eo DO/DIN, D1, D2, D3, D4, D5, D6, D7 DOUT/BUSY DONE PROGRAM INIT Boundary-scan Test Access Port Temperature diode, anode Temperature diode, cathode at +|4]0]8|~|-| >] 0] 0] 2 No connect Table 16 lists the symbols used in these diagrams. The dia- grams aiso show I/O-bank boundaries. 36 November 9, 1998 (Version 1.1 - ADVANCE)22 XILINX PQ240/HQ240 Pin-out Diagram Onwmnmrre ODnwonnrrnonrewuMondrireoonrewnnrnredrnrewnomoraonnrewnono- REKRRRANNARAASAHSKRRRTRESSSSS SRLS Tx * GeerGv*x* Gx** - NG ** Rr *O%*% fr RX PFW TT Nr *Rerex*O%x* r * RVON2 fr * GR*KVGr*G*#* SG 1 G, Bank 0 Bank 1 179 3 x B 5 ,* x2 177 7 * r 175 nc *. 173 9 R G * R 171 1+ * r r 169 13 x . lo 167 G 15 o, Bank 7 Bank 2 8, 165 17 2K Vv * @ 163 19 r * * r 161 21 * * 23 G x* 159 3 Ry PQ240/HQ240 Ge 487 * @ 27 x (Top view) r* 155 29 ** 188 31 Pins are shown staggered ae 151 Vv for readability x 149 33 r Vv * r 147 35 x * R @ 145 37 G R 3 G 143 39 * r * 1441 41 x r 43 y* Bank 6 Bank 3 o* 139 45 Go oY 137 * G@ 135 47 Of r r 133 49 *, r 431 51 G RG 129 53 y* * 55 x 127 * *% 125 57 * @ 59 o Bank 5 Bank 4 p j 123 o \/A 121 * r*#Rer * Ox r **R*VOGOrxGxe*VGrx Ge* *oD Oo **G*rGv* * G* fr 17G%* * R** rf *O* fr R fr *#G SDESSBSRRRRRESSSZSHSRSESSSSSSSLL LES 37 November 9, 1998 (Version 1.1 - ADVANCE)Virtex 2.5 V Field Programmable Gate Arrays BG256 Pin-out Diagram OTFNOAFTWO OR ODO rrrrrrrrr eH AN ~ANOTW OR OOD qmoogwnuOoOrTrXTYAszacro>s> FIKCKOKKKKKKKKKXOXKOHO S|IXOx*X*+O@OXOXXO*X OX * OIOX KAOOKKKKOKX>O*KK* YORE Cx FOO>OOODOOOO>[O x x x Ox x* x Ox * * ~CTXOO>FPOOODOOOO> OO +x * KKOrRKKOKKKHOKKK*OCHKOIO IL KK KKK KKKK KK OK KKK K KIO xX FIK KS KKK OK KKKKKKSKKKO qmogqguuor mItszoarrd>=s> N Oo > x x Mw S S Oe x x co ca + _ XOX KX OOOO F Soarxx O0O00 Ox xd OOOO 2 O>*- SOOG EF p~OrK h o *OKKX z SS he an an Or NOTWO OR ODO rrrrrrr rere TN ANMOTMO ORM OD November 9, 1998 (Version 1.1 - ADVANCE) 38$2 XILINX BG352 Pin-out Diagram OrnNaonsT MOOR WOH OrTA YO TW O rrrr rrr rrr NnNtnAaa&Nn aN a rN OT OR OD <4 mogagwwW qmoogwudgr> eazomrororsregoowr GQHOKLOKLOKOHOKKOKKOKOLDKOK OO OOP KK KK KKK >K KD KKKKKKOK KK OVO KKK SK KK > KKK KK OK KS KKK KK Ol + KKK K KOK KK KX OK RFK KKOK KX O@ 1 + * x**O N Yo) KK KK >**x* x = Om x* x Ox LO oO oO K*>O ***EKX 0 in KK Ox** ~ ***O c>** _ o ***> **** Nz cee xX Oalao > Ox>- ***O Os ** QOS * KO > Or cxx* KKK = +t ***> O*xx*> = = >**O K*OK nN o Oo ****x* Ox * x = x O* nO **XO a a *** * * OK SN OxeKS KX OL[O* *OX*>* OKO KOLKXO* *Ol*K KHL SKKKKOKKOKKOKKOXL* * Slo * CGOx OK KOKKKKKD>KKKKSD KKK LOO GSOHOKKOKOOKOR>*KOKKSOKOKX OK OO S>"go0 OrFNYOYTMO OR DWOOKTA YO TW O wrrererrrrrrr rT NNN N NN ANOTIO OR, O 39 November 9, 1998 (Version 1.1 - ADVANCE)Or-NnNOTFMH OR OODOOrA OTN OR WDDOr rrr r rT eTrTrTeTrTTAninINnNINn&NNNNND OO rTNOSTW OF, OO Virtex 2.5 V Field Programmable Gate Arrays BG432 Pin-out Diagram O* * * KAS O O> x* * ** KO O+x* oO KK KK *Oo> x Ox + * Bank 7 Bank 6 oro OoOrn~nwoonoor ANNAN NNN OO N N November 9, 1998 (Version 1.1 - ADVANCE) Bank 0 Bank 5 oor rN AN _ > *K*O N*K*KO KM KK Ox > * cx KX * SKK O* *O >* Oo. O* * * KK KK Oa >x x _ BG432 (Top View) Srveree Bank 1 Bank 4 Bank 2 Bank 3 rKNOMTWO OR OOD 40$2 XILINX OF NOYNTMN OR DHDOKNANUNTMNOORDWDRAOrKA YM FTerrnTrrrrwrTrT nana a4nrdanN NO OM OM tMoOWLOTeWASzomgroa>s>snoow OK KX SHKKKKKKKDAKKKKOKRKKKKKOHKX KOI OX * Lot qticqacqtqcc * OrH~NYNTW OR DDOrAMTNONOORWDWDDOrT ANY rere TTT TTT NNNANNN NN NN ON OD Om OD OO) 41 rNOTFTW OR OD BG560 Pin-out Diagram x > KK N +k OX *O* KO x x **>*KO Ox * ax a oO xX * KX KK O mn CX*XO> Ok >x* ~ ** CxO *OxX XO SG Oo ***KX*S Ox >* x ** > KO > KKK x**x OX Ox * ax K>O*O CO*Kx*k*X oF KX OX O>x* * x coxx xO ok 0x 3 o - ax x Ox * x * mT *KCKO XOK XO ~ * kK * OX O>x* *x **>aO *OX > Lk ** O>x**> ****O KKK OK e +t *>* OX Oxx*.x* ~ KKEKOS XOKX> n o Oo ** kX **XKX*KX < *>x**O a oO K*KX COX * KK KX KOKKLOKCKKH>SKOKKOKKCKKAOKKKO K*SMOXKKXCKXOKKOKHXKXCOK.KOKXKX .Olo* LO KKEKKKKOK>KOKKXKKKKKKOCOKX>**KXSCOS OOX*K>ORKKKOKKXKXOHKKOS>O> o> OX*KOKEDAOG ANODTIO ORM O OD November 9, 1998 (Version 1.1 - ADVANCE)Virtex 2.5 V Fieid Programmable Gate Arrays Device/Package Combinations and Maximum I/O Package Maximum User /O XCV50 XCV100 | XCV150 | XCV200 | XCV300 | XCV400 | XCV600 | XCV800 | XCV1000 CS144 94 94 TQ144 94 94 PQ240 164 164 164 164 164 HQ240 164 164 164 BG256 180 180 BG352 260 260 260 BG432 316 316 316 316 BG560 404 404 404 404 FG256 176 176 176 176 P FG456 260 284 312 FG600 404 404 404 FG680 500 514 514 Ordering Information Example: XCV300-6PQ240C Device Type |___ Temperature Range C = Commercial (Ty = 0 to +85C) | = Industrial (Ty = -40 to +100C) Speed Grade -4 5 L__ Number of Pins 8 Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale Package 42 November 9, 1998 (Version 1.1 - ADVANCE)22 XILINX Revision Table Date Revision 11/98 Initial document release. November 9, 1998 (Version 1.1 - ADVANCE) 43 |