Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 LM5030 100-V Push-Pull Current Mode PWM Controller 1 Features 3 Description * * * * * * * * * * * The LM5030 high-voltage PWM controller contains all of the features needed to implement push-pull and bridge topologies, using current-mode control in a small 10-pin package. This device provides two alternating gate driver outputs. The LM5030 includes a high-voltage start-up regulator that operates over a wide input range of 14 V to 100 V. Additional features include: error amplifier, precision reference, dual mode current limit, slope compensation, softstart, sync capability, and thermal shutdown. This high speed IC has total propagation delays less than 100 ns and a 1-MHz capable single-resistor adjustable oscillator. 1 Internal High-Voltage Start-Up Regulator Single Resistor Oscillator Setting Synchronizable Error Amplifier Precision Reference Adjustable Softstart Dual Mode Overcurrent Protection Slope Compensation Direct Optocoupler Interface 1.5-A Peak Gate Drivers Thermal Shutdown Device Information(1) 2 Applications * * * PART NUMBER Telecommunication Power Converters Industrial Power Converters +42-V Automotive Systems LM5030 PACKAGE BODY SIZE (NOM) VSSOP (10) 3.00 mm x 3.00 mm WSON (10) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Diagram VIN VOUT VIN LM5030 OUT1 VCC OUT2 CS COMP RT SS VFB ISOLATED FEEDBACK GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application ................................................. 14 9 Power Supply Recommendations...................... 20 10 Layout................................................................... 20 10.1 Layout Guidelines ................................................. 20 10.2 Layout Example .................................................... 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D * Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1 Changes from Revision B (March 2013) to Revision C * 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 16 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 5 Pin Configuration and Functions DGS, DPR Package 10-Pin VSSOP, WSON Top View 1 10 2 9 3 8 4 7 5 6 VIN SS VFB RT CS COMP VCC GND OUT2 OUT1 Pin Functions PIN NAME NO. COMP 3 I/O O DESCRIPTION APPLICATION INFORMATION Output to the error amplifier There is an internal 5-k pullup resistor on this pin. The error amplifier provides an active sink. Current sense input Current sense input for current mode control and current limit sensing. Using separate dedicated comparators, if CS exceeds 0.5 V, the outputs will go into cycle-by-cycle current limit. If CS exceeds 0.625 V the outputs will be disabled and a softstart commenced. CS 8 I GND 7 -- Return Ground OUT1 5 O Output of the PWM controller Alternating PWM output gate driver OUT2 6 O Output of the PWM controller Alternating PWM output gate driver RT 9 I Oscillator timing resistor pin and synchronization input An external resistor sets the oscillator frequency. This pin will also accept synchronization pulses from an external oscillator. SS 10 I Dual purpose soft start and shutdown pin A 10-A current source and an external capacitor set the softstart timing length. The controller will enter a low power state if the SS pin is pulled below the typical shutdown threshold of 0.45 V. VIN 1 I Source input voltage Input to start-up regulator. Input range 14 to 100 V. VFB 2 I Inverting input to the error amplifier The non-inverting input is internally connected to a 1.25-V reference. VCC 4 I/O Output from the internal high-voltage series pass regulator. The regulation setpoint is 7.7 V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal series pass regulator will shutdown, reducing the IC power dissipation. Die substrate The exposed die attach pad on the WSON package should be connected to a PCB thermal pad at ground potential. For additional information on using TI's No Pull Back WSON package, refer to WSON Application Note AN-1187 (SNOA401). WSON DAP SUB -- Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 3 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN to GND (Survival) -0.3 100 V VCC to GND (Survival) -0.3 16 V RT to GND (Survival) -0.3 5.5 V All other pins to GND (Survival) -0.3 7 V Power dissipation Lead temperature Internally Limited (soldering 4 seconds) Operating junction temperature Storage temperature, Tstg (1) -55 260 C 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 Electrostatic discharge (1) 2000 Machine model (MM) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN TJ Operating junction temperature NOM MAX UNIT 14 90 V -40 105 C 6.4 Thermal Information LM5030 THERMAL METRIC (1) DGS (VSSOP) DPR (WSON) 10 PINS 10 PINS UNIT RJA Junction-to-ambient thermal resistance 158.8 38.1 C/W RJC(top) Junction-to-case (top) thermal resistance 53.6 137.1 C/W RJB Junction-to-board thermal resistance 74.8 15.2 C/W JT Junction-to-top characterization parameter 5.3 0.4 C/W JB Junction-to-board characterization parameter 77.6 15.4 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- 4.6 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 6.5 Electrical Characteristics Specifications are for TJ = 25C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 k PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT START-UP REGULATOR TJ = 25C VCCReg VCC Regulation Open ckt full operating junction temperature range 7.7 7.4 TJ = 25C VCC Current limit See Figure 2 I-VIN Start-up regulator leakage (external VCC supply) VIN = 90 V IIN Shutdown current SS = 0 V, VCC = open full operating junction temperature range 8.0 V 17 mA 10 TJ = 25C 150 full operating junction temperature range 500 TJ = 25C A 250 full operating junction temperature range 350 A VCC SUPPLY VCC Undervoltage lockout voltage Undervoltage hysteresis VCCReg - 100 mV TJ = 25C full operating junction temperature range TJ = 25C 1.6 full operating junction temperature range 1.2 TJ = 25C ICC Supply current V VCCReg - 300 mV Cload = 0 2.1 V 2 full operating junction temperature range 3 mA ERROR AMPLIFIER GBW Gain bandwidth DC gain TJ = 25C Input voltage VFB = COMP COMP sink capability VFB = 1.5 V COMP =1V full operating junction temperature range MHz 75 dB 1.245 1.220 TJ = 25C full operating junction temperature range 4 1.270 V 13 mA 5 CURRENT LIMIT TJ = 25C 0.5 CS1 Cycle-by-cyble CS threshold voltage CS2 Restart CS threshold voltage Resets SS capacitor; auto restart ILIM delay to output CS step from 0-V to 0.6-V time-to-onset of OUT transition (90%) Cload = 0 CS sink current (clocked) CS = 0.3 V full operating junction temperature range 0.45 TJ = 25C full operating junction temperature range (1) (2) V 0.625 0.575 0.675 30 TJ = 25C full operating junction temperature range 0.55 V ns 6 3 mA Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers represent the most likely parametric norm for 25C operation. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 5 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics (continued) Specifications are for TJ = 25C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 k PARAMETER MIN (1) TEST CONDITIONS TYP (2) MAX (1) UNIT SOFT START AND SHUTDOWN Softstart current source Softstart to COMP offset Shutdown threshold TJ = 25C 10 full operating junction temperature range 7 TJ = 25C 13 0.5 full operating junction temperature range 0.25 TJ = 25C 0.75 0.45 full operating junction temperature range 0.2 0.7 A V V OSCILLATOR Frequency1 (RT = 26.7K) Frequency2 (RT = 8.2K) Sync threshold TJ = 25C 200 full operating junction temperature range 175 TJ = 25C 225 600 full operating junction temperature range 510 TJ = 25C 690 3.2 full operating junction temperature range 3.8 kHz kHz V PWM COMPARATOR Delay to output COMP set to 2-V CS stepped 0 to 0.4 V, time-toonset of OUT transition low Max duty cycle Inferred from deadtime Min duty cycle COMP = 0 V 30 TJ = 25C full operating junction temperature range ns 49% 47.5% 50% full operating junction temperature range 0% COMP to PWM comparator gain 0.34 TJ = 25C COMP open circuit voltage VFB = 0 V COMP short circuit current VFB = 0 V, COMP = 0V full operating junction temperature range 5.2 4.3 TJ = 25C full operating junction temperature range V/V 6.1 V 1.1 0.6 1.5 mA SLOPE COMPENSATION Slope comp amplitude TJ = 25C Delta increase at PWM Comparator to full operating junction CS temperature range 105 80 130 mV OUTPUT SECTION TJ = 25C Cload = 0, 10% to 10% Output high saturation Iout = 50 mA, VCC - VOUT Output low saturation IOUT = 100 mA Rise time Cload = 1 nF 16 ns Fall time Cload = 1 nF 16 ns full operating junction temperature range TJ = 25C 85 185 0.75 V 0.25 full operating junction temperature range Submit Documentation Feedback ns 0.25 full operating junction temperature range TJ = 25C 6 135 Deadtime 0.75 V Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 Electrical Characteristics (continued) Specifications are for TJ = 25C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, and RT = 26.7 k PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT THERMAL SHUTDOWN Tsd Thermal shutdown temperature Thermal shutdown hysteresis 165 C 15 C Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 7 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com 6.6 Typical Characteristics at TJ = 25C (unless otherwise noted) 16 10 14 9 8 12 7 6 VCC (V) VCC (V) 10 8 5 4 6 3 4 2 2 1 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 VIN (V) 8 10 12 14 16 18 20 ICC (mA) Figure 1. VCC vs VIN Figure 2. VCC vs ICC (VIN = 48 V) 1000 OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) 203.0 100 202.5 202.0 201.5 201.0 200.5 200.0 199.5 199.0 1 10 100 -50 0 RT (K:) 50 100 150 o Figure 3. Oscillator Frequency vs RT TEMPERATURE ( C) Figure 4. Oscillator Frequency vs Temperature RT = 26.7 k 160 10.7 10.6 155 10.5 DEADTIME (ns) ISS (PA) 10.4 10.3 10.2 10.1 10.0 9.9 150 145 140 135 9.8 9.7 130 -50 0 100 50 150 o 0 100 50 150 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 5. Softstart Current vs Temperature 8 -50 Submit Documentation Feedback Figure 6. Deadtime vs Temperature Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 Typical Characteristics (continued) at TJ = 25C (unless otherwise noted) Figure 7. Feedback Amplifier Gainphase Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 9 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LM5030 high-voltage PWM controller contains all of the features needed to implement push-pull and bridge topologies, using current-mode control in a small 10-pin package. Features included are, start-up regulator, dual mode current limit, dual alternating gate drivers, thermal shutdown, softstart, and slope compensation. This high speed IC has total propagation delays < 100 ns. The functional block diagram of the LM5030 is shown in Functional Block Diagram. The LM5030 is designed for current-mode control converters that require alternating outputs, such as push-pull and half- and full-bridge topologies. The features included in the LM5030 enable all of the advantages of currentmode control, line feed-forward, cycle-by-cycle current limit, and simplified loop compensation. The oscillator ramp is internally buffered and added to the PWM comparator input to provide the necessary slope compensation for current-mode control at higher duty cycles. 7.2 Functional Block Diagram 7.7V SERIES REGULATOR VCC VIN GENERATOR REFERENCE ENABLE 5V 1.25V LOGIC CLK OSC Rt / SYNC SLOPECOMP RAMP GENERATOR J 45PA K 0 5V 5k 100k SET Q VCC Q OUT1 Q R Q CLR PWM DRIVER + - VFB 1.4V CLR S COMP 1.25V SET LOGIC 50k SS VCC OUT2 CS 2k 0.5V + - 0.625V + - DRIVER GND CLK ERROR AMP SOFT START 10PA SS SHUTDOWN COMPARATOR + - ENABLE 0.45V 10 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 7.3 Feature Description 7.3.1 High-Voltage Start-Up Regulator The LM5030 contains an internal high-voltage start-up regulator. The input pin (VIN) can be connected directly to line voltages as high as 100 V. The regulator output is internally current limited to 10 mA. Upon power up, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended capacitance range for the VCC regulator is 0.1 F to 50 F. When the voltage on the VCC pin reaches the regulation point of 7.7 V, the controller outputs are enabled. The outputs will remain enabled unless, VCC falls below 6.1 V or if the SS/SHUTDOWN pin is pulled to ground or an over temperature condition occurs. In typical applications, an auxiliary transformer winding is diode connected to the VCC pin. This winding raises the VCC voltage greater than 8 V, effectively shutting off the internal start-up regulator and saving power while reducing the controller dissipation. The external VCC capacitor must be sized such that the self-bias will maintain a VCC voltage greater than 6.1 V during the initial start-up. During a fault mode when the converter self bias winding is inactive, external current draw on the VCC line should be limited as to not exceed the maximum power dissipation of the controller. An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the Vin pins and feeding the external bias voltage (8 V to 15 V) to that node. 7.3.2 Error Amplifier An internal high gain error amplifier is provided within the LM5030. The noninverting reference of the amplifier is tied to 1.25 V. In nonisolated applications the power converter output is connected to the VFB pin via the voltage setting resistors and loop compensation is connected between the COMP and VFB pins. For most isolated applications the error amplifier function is implemented on the secondary side ground. Because the internal error amplifier is configured as an open drain output it can be disabled by connecting VFB to ground. The internal 5-k pullup resistor, connected between the 5-V reference and COMP, can be used as the pullup for an optocoupler or other isolation device. 7.3.3 PWM Comparator The PWM comparator compares the compensated current ramp signal to the loop error voltage from the internal error amplifier (COMP pin). This comparator is optimized for speed in order to achieve minimum discernable duty cycles. The comparator polarity is such that 0 V on the COMP pin will cause a zero duty cycle. 7.3.4 Current Limit and Current Sense The LM5030 contains two levels of over-current protection. If the voltage on the current sense comparator exceeds 0.5 V the present cycle is terminated (cycle-by-cycle current limit). If the voltage on the current sense comparator exceeds 0.625 V, the controller will terminate the present cycle and discharge the softstart capacitor. A small RC filter, located near the controller, is recommended for the CS pin. An internal MOSFET discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. The LM5030 CS and PWM comparators are very fast, and as such will respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and RTN). Also if a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the IC. If a current sense resistor located in the drive transistor sources is used, for current sense, a low inductance resistor should be chosen. In this case all of the noise sensitive low power grounds should be commoned together around the IC and then a single connection should be made to the power ground (sense resistor ground point). The second level threshold is intended to protect the power converter by initiating a low duty cycle hiccup mode when abnormally high, fast rising currents occur. During excessive loading, the first level threshold will always be reached and the output characteristic of the converter will be that of a current source but this sustained current level can cause excessive temperatures in the power train especially the output rectifiers. If the second level threshold is reached, the softstart capacitor will be fully discharged, a retry will commence following the discharge detection. The second level threshold will only be reached when a high dV/dt is present at the current sense pin. The signal must be fast enough to reach the second level threshold before the first threshold detector turns off the driver. This can usually happen for a saturated power inductor or shorted load. Excessive filtering on the CS pin, extremely low value current sense resistor or an inductor that does not saturate with excessive loading may prevent the second level threshold from ever being reached. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 11 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) 7.3.5 Oscillator, Shutdown and Sync Capability The LM5030 oscillator is set by a single external resistor connected between the RT pin and return. To set a desired oscillator frequency, the necessary RT resistor can be calculated in Equation 1: RT = (1/F) - 172 x 10-9 182 x 10-12 (1) Each output switches at half the oscillator frequency in a push-pull configuration. The LM5030 can also be synchronized to an external clock. The external clock must be of higher frequency than the free running frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT pin with a 100-pF capacitor. A peak voltage level greater than 3 V with respect to ground is required for detection of the sync pulse. The sync pulse width should be set in the 15- to 150-ns range by the external components. The RT resistor is always required, whether the oscillator is free running or externally synchronized. The voltage at the RT pin is internally regulated to a nominal 2 V. Locate the RT resistor close to the device and connected directly to the pins of the IC (RT and GND). 7.3.6 Slope Compensation The PWM comparator compares the current sense signal to the voltage derived from the COMP pin. The COMP voltage is set by either the internal error amplifier or an external error amplifier through an optocoupler. At duty cycles greater than 50% (composite of alternating outputs) current mode control circuits are prone to subharmonic oscillation. By adding an additional ramp signal to the current sense ramp signal this condition can be avoided. The LM5030 integrates this slope compensation by buffering the internal oscillator ramp and summing it internally to the current sense (CS) signal. Additional slope compensation may be added by increasing the source impedance of the current sense signal. 7.3.7 Soft Start and Shutdown The soft-start feature allows the converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. An internal 10-A current source and an external capacitor generate a ramping voltage signal that limits the error amplifier output during start-up. In the event of a second level current limit fault, the soft-start capacitor will be fully discharged which disables the output drivers. When the fault condition is no longer present, the soft-start capacitor is released to ramp and gradually restart the converter. The SS pin can also be used to disable the controller. If the SS pin voltage is pulled down below 0.45 V (nominal) the controller will disable the outputs and enter a low power state. 7.3.8 OUT1, OUT2, and Time Delay The LM5030 provides two alternating outputs, OUT1 and OUT2. The internal gate drivers can each sink 1.5-A peak each. The maximum duty cycle for each output is inherently limited to less than 50%. The typical deadtime between the falling edge of one gate driver output and the rising edge of the other gate driver output is 135 ns. 7.3.9 Thermal Protection Internal thermal-shutdown circuitry is provided to protect the integrated circuit in the event the excessive junction temperature. When activated, typically at 165C, the controller is forced into a low-power reset state, disabling the output drivers and the bias regulator. This feature is provided to prevent catastrophic failures from accidental device overheating. 12 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 7.4 Device Functional Modes The LM5030 is a versatile PWM controller that can be used in the following functional modes: * The LM5030 provides a complete push-pull current mode current mode controller. * The LM5030 driver outputs can be configured to drive high side MOSFETs through a gate driver chip to implement half and full bridge topologies. * The LM5030 can be configured in single ended outputs such as a flyback converter or boost. * The LM5030 can also operate in conjunction with a high side driver chip to implement a synchronous buck converter. Details of these circuits can be found in Versatility of the LM5030 PWM Push-Pull Controller, SNVA548. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 13 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5030 is a highly integrated PWM controller that contains all of the features necessary for implementing push-pull topology power converters. The device targets DC-DC converter applications with input voltages of up to 100 VDC and output power in the range 15 W to 150 W. 8.2 Typical Application The schematic in Figure 8 shows an example of a 33-W push-pull converter controlled by a LM5030. The operating input range is 36 V to 75 V, and the output voltage is 3.3 V. The output current capability is 10 A. The converter is configured for input current protection with cycle-by-cycle current limit. An auxiliary winding is used to raise the VCC voltage to reduce the controller power dissipation. Figure 8. Typical Application Circuit, 36-V to 75-V IN and 3.3-V, 10-A OUT 14 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 Typical Application (continued) 8.2.1 Design Requirements For this design example, use the input parameters listed in Table 1. Table 1. Design Parameters PARAMETER MIN Input Voltage NOM 36 Output Voltage MAX 75 3.3 Output Current 0 82.5% Efficiency (Half Load) 84.5% Load Regulation V V 10 Efficiency (Full Load) UNIT A 1% Line Regulation 0.15% Output Current Limit 11 A 8.2.2 Detailed Design Procedure 8.2.2.1 VCC While the LM5030 internally generates a voltage at VCC (7.7 V), the internal regulator is used mainly during the start-up sequence. Once the load current begins flowing through L2, which is both an inductor for the output filter and a transformer, a voltage is generated at the secondary of L2, which powers the VCC pin. When the externally applied voltage exceeds the internal value (7.7 V), the internal regulator shuts off, thereby reducing internal power dissipation in the LM5030. L2 is constructed such that the voltage supplied to VCC ranges from approximately 10.6 V to approximately 11.3 V, depending on the load current (see Figure 9). 11.3 11.2 11.1 VCC (V) 11.0 10.9 10.8 10.7 10.6 10.5 0.0 2.0 4.0 6.0 8.0 10.0 LOAD CURRENT (A) Figure 9. VCC Voltage vs Load Current 8.2.2.2 Current Sense Monitoring the input current provides a good indication of the operation of the circuit. If an overload condition should exist at the output (a partial overload or a short circuit), the input current would rise above the nominal value shown in Figure 12. Transformer T2, in conjunction with D3, R9, R12 and C10, provides a voltage to pin 8 on the LM5030 (CS) which is representative of the input current flowing through its primary. The average voltage seen at pin 8 is plotted in Figure 10. If the voltage at the first current sense comparator exceeds 0.5 V, the LM5030 disables its outputs, and the circuit enters a cycle-by-cycle current limit mode. If the second level threshold (0.625 V) is exceeded due to a severe overload and transformer saturation, the LM5030 will disable its outputs and initiate a softstart sequence. However, the very short propagation delay of the cycle-by-cycle current limiter (CS1), the design of the CS filter (R9, R12, and C10), and the conservative design of the output inductor (L2), may prevent the second level current threshold from being realized on this evaluation board. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 15 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com AVERAGE VOLTAGE @ CS (V) 0.25 0.20 0.15 0.10 0.05 0.00 0.0 0.2 0.4 0.6 0.8 1.0 INPUT CURRENT (A) Figure 10. Average Voltage at the CS Pin vs Input Current 8.2.2.3 Shutdown The Shutdown pad (SD) on the board connects to the SoftStart pin on the LM5030 (pin 10), and permits on/off control of the converter by an external switch. SD should be pulled below 0.45 V, with an open collector or open drain device, to shut down the LM5030 outputs and the VCC regulator. If the voltage at the SD pad is between 1.0 and 1.5 V, a partial-on condition results, which could be disruptive to the system. Therefore, the voltage at the SD pad should transition quickly between its open circuit voltage (4.9 V) and ground. 8.2.2.4 External Sync Although the LM5030 includes an internal oscillator, its operating frequency can be synchronized to an external signal if desired. The external source frequency must be higher than the internal frequency set with the RT resistor (262 kHz with RT = 20 k). The sync input pulse width must be between 15 and 150 ns, and have an amplitude of 1.5 to 3.0 V at the Sync pad on the board. The pulses are coupled to the LM5030 through a 100-pF capacitor (C16) as specified in the data sheet. Table 2. Bill of Materials ITEM 16 PART NUMBER DESCRIPTION VALUE C 1 C0805C472K5RAC Capacitor, CER, KEMET 4700 p, 50 V C 2 C0805C103K5RAC Capacitor, CER, KEMET 0.01 , 50 V C 3 C4532X7S0G686M Capacitor, CER, TDK 68 , 4 V C 4 T520D337M006AS4350 Capacitor, TANT, KEMET 330 , 6.3 V C 5 T520D337M006AS4350 Capacitor, TANT, KEMET 330 , 6.3 V C 6 C4532X7R3A103K Capacitor, CER, TDK 0.01 , 1000 V C 7 C3216X7R2A104K Capacitor, CER, TDK 0.1 , 100 V C 8 C4532X7R2A105M Capacitor, CER, TDK 1 , 100 V C 9 C4532X7R2A105M Capacitor, CER, TDK 1 , 100 V C 10 C0805C102K1RAC Capacitor, CER, KEMET 1000 p, 100 V C 11 C1206C223K5RAC Capacitor, CER, KEMET 0.022 , 50 V C 12 C3216X7R1E105M Capacitor, CER, TDK 1 , 25 V C 13 C3216COG2J221J Capacitor, CER, TDK 220 p, 630 V C 14 C3216COG2J221J Capacitor, CER, TDK 220 p, 630 V C 15 C1206C104K5RAC Capacitor, CER, KEMET 0.1 , 50 V C 16 C0805C101J1GAC Capacitor, CER, KEMET 100 p, 100 V C 17 C0805C101J1GAC Capacitor, CER, KEMET 100 p, 100 V C 18 C3216X7R1H334K Capacitor, CER, TDK 0.33 , 50 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 Table 2. Bill of Materials (continued) ITEM PART NUMBER DESCRIPTION VALUE D 1 MBRB3030CTL Diode, Schottky, ON D 2 CMPD2838-NSA Diode, Signal, Central D 3 CMPD2838-NSA Diode, Signal, Central D 4 CMPD2838-NSA Diode, Signal, Central D 5 CMPD2838-NSA Diode, Signal, Central L 1 MSS6132-103 Input Choke, Coilcraft 10 H, 1.5 A L 2 A9785-B Output Choke, Coilcraft 7 H R 1 CRCW12061R00F Resistor 1 R 2 CRCW12064990F Resistor 499 R 3 CRCW2512101J Resistor 100, 1 W R 4 CRCW2512101J Resistor 100, 1 W R 5 CRCW12064022F Resistor 40.2K R 6 CRCW120610R0F Resistor 10 R 7 CRCW120610R0F Resistor 10 R 8 CRCW12061002F Resistor 10K R 9 CRCW120623R7F Resistor 23.7 R 10 CRCW12062002F Resistor 20K R 11 CRCW120610R0F Resistor 10 R 12 CRCW12063010F Resistor 301 R 13 CRCW120610R0F Resistor 10 R 14 CRCW12061001F Resistor 1K TX 1 A9784-B POWER XFR, COILCRAFT TX 2 P8208T CURRENT XFR, Pulse U1 1 LM5030 REGULATOR, TI U2 2 MOCD207M OPTO-COUPLER, QT OPTOELECTRONICS U3 3 LM3411AM5-3.3 REFERENCE, TI 651-1727010 DUAL TERMINALS, MOUSER X 1 SUD19N20-90 FET, N, 200 V, SILICONIX X 2 SUD19N20-90 FET, N, 200 V, SILICONIX 100:1 3 per ASSY Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 17 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com V1 Q2 Gate 0V t1 t2 V1 Q1 Gate 0V V4 V3 V2 Q2 Drain tR = 150 ns 0V V5 V6 T1 (Pin 4) 0V V8 V7 V9 V10 D1 Output 0V L2 Output 3.3V 100 mVp-p Figure 11. Representative Waveforms Table 3. Test Data VIN IOUT t1 t2 Fs V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 36 V 1.0 A 2.2 S 5.3 S 266.7 10.5 V 36 V 72 V 90 V 10 V 6V -10 V -6 V 10 V 6V 48 V 10 A 1.9 S 5.5 S 270.3 11.5 V 48 V 96 V 130 V 18 V 8V -18 V -8 V 13 V 8V 75 V 1.0 A 1.2 S 6.2 S 270.3 10.5 V 75 V 150 V 200 V 20 V 13 V -20 V -13 V 20 V 13 V 18 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 8.2.3 Application Curves 100 1.2 80 VIN = 36 V 0.8 EFFICIENCY (%) INPUT CURRENT (A) VIN = 36 V 90 1.0 VIN = 75 V 0.6 0.4 VIN = 75 V 70 60 50 40 0.2 30 20 0.0 0 5 0 10 2 4 6 8 10 LOAD CURRENT (A) LOAD CURRENT (A) Figure 12. Input Current vs Load Current and VIN Figure 13. Efficiency vs Load Current and VIN Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 19 LM5030 SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 www.ti.com 9 Power Supply Recommendations The LM5030 can be used as a controller for push-pull, full bridge or half bridge power supplies. Typical applications are for input voltages up to 100 V and output power around 30 W with switching frequency up to 1 MHz. Care should be taken that components with the correct current rating are chosen. This includes magnetic components, power MOSFETs and diodes, connectors and wire sizes. Input and output capacitors should have the correct ripple current rating. The VCC pin requires a local decoupling capacitor that is connected to GND. This capacitor ensures stability of the internal regulator from the VIN pin. The decoupling capacitor also provides the current pulses to drive the gates of the external MOSFETs through the driver output pins. Place the decoupling capacitor close to the VCC and GND pins and track it directly to these pins. 10 Layout 10.1 Layout Guidelines As in all high frequency switching power supplies, it is important to separate the high current return trace from the low level GND signal of the controller. These signals should be connected together at a single point, usually the negative side of the DC input filter capacitor. Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the device pins. If the current sense circuit employs a sense resistor in the power MOSFET source, a low inductance resistor should be used and all the low current traces should be connected in common near the device with a single connection made to the GND pin. The gate drive outputs of the device should have short, direct paths to the power MOSFETs in order to minimize inductance in the gate path. If the internal dissipation of the device produces a high junction temperature during normal operation, the use of multiple vias under the device to a ground plane can help conduct heat away from the device. 10.2 Layout Example VIN SS VFB RT COMP CS From VIN VCC OUT1 To Current Sense Resistor GND To Gate Drive 2 OUT2 To Isolated Feedback To Gate Drive 1 Figure 14. LM5030 Board Layout 20 Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 LM5030 www.ti.com SNVS215D - APRIL 2003 - REVISED NOVEMBER 2015 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Documentation Support 11.2.1 Related Documentation SNOA401: AN-1187 Leadless Leadframe Package (LLP) SNVA548: Versatility of the LM5030 PWM Push-Pull Controller 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2003-2015, Texas Instruments Incorporated Product Folder Links: LM5030 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM5030MM NRND VSSOP DGS 10 1000 Non-RoHS & Non-Green Call TI Call TI -40 to 125 S73B LM5030MM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S73B LM5030MMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S73B LM5030SD/NOPB ACTIVE WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 5030SD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5030MM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5030MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5030MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5030SD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5030MM VSSOP DGS 10 1000 210.0 185.0 35.0 LM5030MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5030MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5030SD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DGS0010A VSSOP - 1.1 mm max height SCALE 3.200 SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 SEATING PLANE PIN 1 ID AREA A 0.1 C 10 1 3.1 2.9 NOTE 3 8X 0.5 2X 2 5 6 B 10X 3.1 2.9 NOTE 4 SEE DETAIL A 0.27 0.17 0.1 C A 1.1 MAX B 0.23 TYP 0.13 0.25 GAGE PLANE 0 -8 0.15 0.05 0.7 0.4 DETAIL A TYPICAL 4221984/A 05/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA. www.ti.com EXAMPLE BOARD LAYOUT DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (0.3) 10X (1.45) (R0.05) TYP SYMM 1 10 SYMM 8X (0.5) 6 5 (4.4) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221984/A 05/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGS0010A VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM 1 (R0.05) TYP 10 SYMM 8X (0.5) 6 5 (4.4) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221984/A 05/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. 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