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Standard Products
UT54ACS245S
Schmitt Octal Bus Transceiver with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Three-state outputs drive bus line directly
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS245S - SMD 5962-96572
DESCRIPTION
The UT54ACS245S is a non-inverting octal bus transceiver with
Schmitt Trigger input levels. The circuit is designed for asyn-
chronous two- w ay communication between data buses. The
control function implem entation minimizes external tim ing re-
quirements.
The device allows data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level
at the direction control (DIR) input. The enable input (G) dis-
ables the device so that the buses are ef fectively isolated.
The device is characterized over full military temperature range
of -55°C to +125°C.
FUNCTION TABLE
PINOUTS 20-Pin DIP
Top View
20-Lead Flatpa ck
Top View
LOGIC SYMBOL
ENABLE
GDIRECTION
CONTROL DIR OPERATION
L L B Data To A Bus
L H A Data To B Bus
H X Isolation
1
2
3
4
5
7
6
20
19
18
17
16
14
15
DIR
A1
A2
A3
A4
A5
A6
VDD
G
B1
B2
B3
B5
813
A7 B6
B4
912
A8 B7
10 11
VSS B8
1
2
3
4
5
7
6
20
19
18
17
16
14
15
DIR
A1
A2
A3
A4
A5
A6
VDD
G
B1
B2
B3
B5
813
A7 B6
B4
912
A8 B7
10 11
VSS B8
(19)
GG3
(2)
A1
(3)
A2 (4)
(18) B1
(16)
(17) B2
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
A3 (5)
A4 (6)
A5 (7)
A6
B3
(13) B6
(14) B5
(15) B4
(8)
A7 (9)
A8 (11) B8
(12) B7
(1)
DIR 3 EN1 (BA)
3 EN2 (AB)
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2
LOGIC DIAGRAM
A1
A2
A3
A4
A5
A6
A7
A8
DIR (1)
(2)
(19)
(18)
(3)
(17)
(4)
(16)
(5)
(15)
(6)
(14)
(7)
(13)
(8)
(12)
(9)
(11)
B1
B2
B3
B6
B5
B4
B8
B7
G
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OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyo nd limits indicated in the opera tional sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 3120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VT+Schmitt Trigger, positive goin g threshold1
ACS .7VDD V
VT-Schmitt Trigger, negative going threshold1
ACS .3VDD V
VHSchmitt Trigger, typical range of hysteresis
2ACS 0.6 1.5 V
IIN Input leakage current
ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACS IOL = 100μA0.25 V
VOH High-level output voltage 3
ACS IOH = -100μAVDD - 0.25 V
IOL Output current (Sink)10 VIN=VDD or VSS
VOL=0.4V
12 mA
IOH Output current (Source)10 VIN=VDD or VSS
VOH=VDD - 0.4
-12 mA
IOZ Three-state output leakage current VO = VDD and VSS -30 30 μA
IOS Short-circuit output current 2, 4
ACS VO = VDD and VSS -300 300 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 2.0 mW/
MHz
IDDQ Quiescent Supply Current VDD = 5.5V 10 μA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5ƒ = 1MHz @ 0V 15 pF
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Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit, but not guaranteed or tested.
3. Per MIL-PRF-385 35, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4.Not more than one output may be shorted at a time for maxim um duration of one second.
5.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal ampl itude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10.Guaranteed based on characterization data, but not tested.
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AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si)
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPLH Data to bus 2 15 ns
tPHL Data to bus 2 15 ns
tPZL G low to bus active 2 12 ns
tPZH G low to bus active 2 12 ns
tPLZ G high to bus three-state 2 15 ns
tPHZ G high to bus three-state 2 15 ns
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PACKAGING Side-Brazed Packages
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FLATPACK PACKAGES
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UT54ACS245S: SM D
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 20-lead ceramic bottom-brazed dual-in-line Flatpack
C = 20-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96572 = UT54ACS245S
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
