IRFR/U9024N
PRELIMINARY HEXFET® Power MOSFET
6/26/97
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.3
RθJA Junction-to-Ambient (PCB mount)** ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110
Thermal Resistance
D - Pa k
TO-252AA I-Pa k
TO-251AA
lUltra Low On-Resistance
lP-Channel
lSurface Mount (IRFR9024N)
lStraight Lead (IRFU9024N)
lAdvanced Process Technology
lFast Switching
lFully Avalanche Rated
Description
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -1 1
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V - 8 A
IDM Pulsed Drain Current -44
PD @TC = 25°C Power Dissipation 38 W
Linear Derating Factor 0.30 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy 62 mJ
IAR Avalanche Current-6.6 A
EAR Repetitive Avalanche Energy3.8 mJ
dv / dt Peak Diode Recovery dv/dt -10 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The D-Pak is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
PD - 9.1506
VDSS = -55V
RDS(on) = 0.175 Ω
ID = -11A
S
D
G
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IRFR/U9024N
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)
––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– -1.6 V TJ = 25°C, I S = -7.2A, VGS = 0V
trr Reverse Recovery Time ––– 47 71 n s TJ = 25°C, IF = -7.2A
Qrr Reverse Recovery Charge ––– 84 130 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
-11
-44 A
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
Starting TJ = 25°C, L = 2.8mH
RG = 25Ω, IAS = -6.6A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ -6.6A, di/dt ≤ 240A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -55 ––– ––– V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– -0.05 ––– V/°C Reference to 25°C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.175 ΩVGS = -10V, ID = -6.6A
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
gfs Forward Transconductance 2.5 ––– ––– S VDS = -25V, ID = -7.2A
––– ––– -25 µA VDS = -55V, V GS = 0V
––– ––– -250 VDS = -44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge ––– ––– 19 ID = -7.2A
Qgs Gate-to-Source Charge ––– ––– 5.1 nC VDS = -44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 10 VGS = -10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 13 ––– V DD = -28V
trRise Time ––– 55 ––– ID = -7.2A
td(off) Turn-Off Delay Time ––– 23 ––– RG = 24Ω
tfFall Time ––– 37 ––– RD = 3.7Ω, See Fig. 10
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance – –– 350 ––– VGS = 0V
Coss Output Capacitance ––– 170 ––– pF VDS = -25V
Crss Reverse Transfer Capacitance ––– 92 ––– ƒ = 1.0MHz, See Fig. 5
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
S
D
G
Uses IRF9Z24N data and test conditions.
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IRFR/U9024N
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-Source Voltage (V)
-I , Drain-to-Source Current (A)
DS
D
-4.5V
0.1
1
10
100
0.1 1 10 100
20µs PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-Source Voltage (V)
-I , Drain-to-Source Current (A)
DS
D
-4.5V
-60 -40 -20 0 20 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
-10V
-11A
0.1
1
10
100
45678910
V = -25V
20µs PULSE WIDTH
DS
-V , Gate-to-Source Voltage (V)
-I , Drain-to-Source Current (A)
GS
D
T = 150 C
J°
T = 25 C
J°
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IRFR/U9024N
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0.1
1
10
100
0.2 0.6 0.9 1.3 1.6
-V ,Source-to-Drain Voltage (V)
-I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
1000
1 10 100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 150 C
= 25 C
°°
J
C
-V , Drain-to-Source Voltage (V)
-I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
0
100
200
300
400
500
600
700
1 10 100
C, Capacitance (pF)
DS
V , Dr ai n-to - So ur c e V oltage (V )
A
V = 0 V, f = 1 MHz
C = C + C , C SHO RT ED
C = C
C = C + C
GS
iss gs g d ds
rs s g d
oss ds gd
C
iss
C
oss
C
rss
0
4
8
12
16
20
0 5 10 15 20 25
G
GS
A
-V , Ga te-to-S ource Voltage (V )
Q , To tal Gate C ha rg e (n C )
FOR TE ST CIRCUIT
SEE FIG U RE 1 3
I = -7.2 A
V = - 4 4V
V = - 2 8V
D
DS
DS
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IRFR/U9024N
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
VDS
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RGD.U.T.
+
-
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
25 50 75 100 125 150
0.0
3.0
6.0
9.0
12.0
T , Case Temperature ( C)
-I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. Duty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
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IRFR/U9024N
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Q
G
Q
GS
Q
GD
V
G
Charge
-10V
D.U.T. V
DS
I
D
I
G
-3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tpV
(BR)DSS
I
AS
R
G
IAS
0.01
Ω
t
p
D.U.T
L
VDS
VDD
DRIVER A
15V
-20V
-
+VDD
25 50 75 100 125 150
0
20
40
60
80
100
120
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
-3.0A
-4.2A
-6.6A
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IRFR/U9024N
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 14. For P-Channel HEXFETS
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IRFR/U9024N
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
TO-252AA (D-Pak)
Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
4.57 (.180)
2.28 ( .090)
2X 1.14 (.045)
0.76 (.030)
1.52 (.060)
1.15 (.045)
1.02 (.040)
1.64 (.025)
5.46 (.215)
5.21 (.205) 1.27 ( .050)
0.88 ( .035)
2.38 (.094)
2.19 (.086) 1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0.58 (.023)
0.46 (.018)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
INTERNATIONAL
REC TIFIE R
L OGO
ASSEMBLY
LO T CO D E
EXAM PLE : THIS IS AN IRFR120
WITH ASSEMBL Y
L O T CO D E 9 U1 P FIR ST PO RTION
OF PAR T N UMBER
SECO ND POR TION
OF PART NU MBER
120
IRFR
9U 1 P
A
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IRFR/U9024N
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
TO-251AA (I-Pak)
Part Marking Information
INTERNATIONAL
RE CT IF IE R
L OG O
ASSEM BLY
L OT CODE
FIRST PORTION
OF PART N UM BER
SECO ND POR TION
OF PART NU MBER
120
9 U 1P
EXAM PLE : THIS IS AN IRFU1 20
WITH ASSEM BLY
L OT CODE 9 U1 P
IRFU
6.73 (.265)
6.35 (.250)
- A -
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.28 (.090)
1.14 (.045)
0.76 (.030)
5.46 (.215)
5.21 (.205) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018) LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSIO N : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
9.65 (.380)
8.89 (.350)
2X
3X
2.28 (.090)
1.91 (.075)
1.52 (.060)
1.15 (.045)
4
1 2 3
6.45 ( .245)
5.68 ( .224)
0.58 (.023)
0.46 (.018)
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IRFR/U9024N
Tape & Reel Information
TO-252AA
TR
16 .3 ( .64 1 )
15 .7 ( .61 9 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIREC TIO N FEED DIREC TIO N
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NO T ES :
1. CONT RO LLING DIM ENSION : M ILLIM ETER.
2. ALL DIME NSIO NS ARE S HOWN IN M ILLIM ETERS ( IN CHES ).
3. O UT LINE CO N FO R MS TO E IA -481 & E IA-541.
NOT ES :
1. O UTLINE CO NFO RM S TO EIA-481.
16 m m
13 INC H
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
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IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
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http://www.irf.com/ Data and specifications subject to change without notice. 6/97
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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