FEATURES FUNCTIONAL BLOCK DIAGRAM Dual, independent, digitally controlled gain amplifier (DGA) -9 dB to +26 dB gain range 1 dB step size, 0.2 dB accuracy at 200 MHz 100 differential input resistance 10 differential output resistance 1.2 dB change in noise figure for first 12 dB of gain reduction Output third-order intercept (OIP3): 48.5 dBm at 200 MHz, 5 V, high performance mode -3 dB bandwidth: 1700 MHz typical in high performance mode Multiple control interface options Parallel 6-bit control interface with latch Serial peripheral interface (SPI) with fast attack Gain step up/down interface Wide input dynamic range Low power mode Power-down control Single 3.3 V or 5 V supply operation 40-lead, 6 mm x 6 mm LFCSP package SIDE A SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN PWUPA LOGIC VINA+ 100 0dB TO 23dB VINA- Differential analog-to-digital converter (ADC) drivers High intermediate frequency (IF) sampling receivers High output power IF amplification Instrumentation VOUTA- 14dB TO 26dB 10 14dB TO 26dB 10 VOUTA+ MODE0 CONTROL CIRCUITRY MODE1 PM VINB+ 100 0dB TO 23dB VINB- LOGIC SIDE B VOUTB- VOUTB+ ADL5205 PWUPB SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN APPLICATIONS VPOS GND 13488-001 Data Sheet Dual, 35 dB Range, 1 dB Step Size DGA ADL5205 Figure 1. GENERAL DESCRIPTION The ADL5205 is a digitally controlled, wide bandwidth, variable gain dual amplifier (DGA) that provides precise gain control, high output third-order intercept (OIP3) and a near constant noise figure for the first 12 dB of attenuation. The excellent OIP3 performance of 48.5 dBm (at 200 MHz, 5 V, high performance mode, and maximum gain) makes the ADL5205 an excellent gain control device for a variety of receiver applications. For wide input dynamic range applications, the ADL5205 provides a broad 35 dB gain range with a 1 dB step size. The gain is adjustable through multiple gain control and interface options: parallel, SPI, or gain step up/down control. The two channels of the ADL5205 can be powered up independently by applying the appropriate logic level to the PWUPA and PWUPB pins. The quiescent current of the ADL5205 is typically 175 mA for high performance mode and 135 mA for Rev. A low power mode. When disabled, the ADL5205 consumes only 14 mA and offers excellent input to output isolation. The gain setting is preserved when the device is disabled. Fabricated on the Analog Devices, Inc., high speed, silicon germanium (SiGe) complementary BiCMOS process, the ADL5205 provides precise gain adjustment capabilities with good distortion performance. The ADL5205 amplifier comes in a compact, thermally enhanced, 6 mm x 6 mm, 40-lead LFCSP package and operates over the temperature range of -40C to +85C. Note that throughout this data sheet, multifunction pins, such as CSA/A3, are referred to by the entire pin name or by a single function of the pin, for example, CSA, when only that function is relevant. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5205 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Read ....................................................................................... 20 Applications ....................................................................................... 1 ADC Interfacing ......................................................................... 21 Functional Block Diagram .............................................................. 1 Noise Figure vs. Gain Setting .................................................... 21 General Description ......................................................................... 1 Evaluation Board ............................................................................ 22 Revision History ............................................................................... 2 Overview ..................................................................................... 22 Specifications..................................................................................... 3 Power Supply Interface .............................................................. 22 Timing Specifications .................................................................. 5 Signal Inputs and Outputs......................................................... 23 Absolute Maximum Ratings............................................................ 6 Manual Controls ......................................................................... 23 Thermal Resistance ...................................................................... 6 Parallel Interface ......................................................................... 24 Junction to Board Thermal Impedance..................................... 6 Serial Interface ............................................................................ 24 ESD Caution .................................................................................. 6 Standard Development Platform (SDP) Interface ................. 25 Pin Configuration and Function Descriptions ............................. 7 Evaluation Board Control Software ......................................... 25 Typical Performance Characteristics ............................................. 9 Command Line Control Program............................................ 25 Theory of Operation ...................................................................... 17 Graphical User Interface (GUI) Program ............................... 25 Basic Structure ............................................................................ 17 Evaluation Board Schematics and Layout ................................... 27 Control/Logic Circuitry............................................................. 17 Bill of Materials ........................................................................... 30 Common-Mode Voltage ............................................................ 17 Outline Dimensions ....................................................................... 31 Applications Information .............................................................. 18 Ordering Guide .......................................................................... 31 Basic Connections ...................................................................... 18 Digital Interface Overview ........................................................ 19 REVISION HISTORY 5/2019--Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 4/2016--Revision 0: Initial Version Rev. A | Page 2 of 31 Data Sheet ADL5205 SPECIFICATIONS Supply voltage (VPOS) = 3.3 V or 5 V, TA = 25C, ZLOAD = 200 , maximum gain (Gain code = 000000), frequency = 200 MHz, PM = 0 V, 2 V p-p differential output, unless otherwise noted. Table 1. Parameter1 DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT STAGE Maximum Input Swing2 Differential Input Resistance Input Common-Mode Voltage Common-Mode Rejection Ratio (CMRR) GAIN Voltage Gain Range Maximum Gain Minimum Gain Gain Step Size Gain Step Accuracy Gain Flatness Gain Temperature Sensitivity Fast Attack Step Response Delay COMMON-MODE INPUTS VCMA and VCMB Input Resistance OUTPUT STAGE Output Voltage Swing Common-Mode Voltage Reference Output Common-Mode Offset Differential Output Resistance Short-Circuit Current NOISE/HARMONIC PERFORMANCE 10 MHz Noise Figure Second Harmonic Third Harmonic Output Third-Order Intercept (OIP3) Output 1 dB Compression Point (P1dB) 100 MHz Noise Figure Second Harmonic Third Harmonic OIP3 Output P1dB Test Conditions/Comments 3.3 V Supply Min Typ Max High performance mode Low power mode VINx+ and VINx- pins Gain code = 111111 Differential Gain code = 000000 Gain code = 000000 Gain code = 100011 to 111111 From 30 MHz to 200 MHz Gain code = 000000 For VIN = 0.1 V, FA_A or FA_B changing from 0 to 1 with 16 dB step VOUTx+ and VOUTx- pins At P1dB, gain code = 000000 VCMA, VCMB ((VOUTx+) + (VOUTx-))/2 - VCMx/2 Differential High performance mode Low power mode Gain code = 000000, high performance mode Min 5 V Supply Typ Max Unit 1700 1500 5 1700 1500 5 MHz MHz V/ns 8 100 1.65 48 8 100 2.5 48 V p-p V dB 35 26 -9 1 0.2 0.2 2.4 15 35 26 -9 1 0.2 0.2 4 80 dB dB dB dB dB dB p-p mdB/C ns 2.6 2.6 k 10 22 17 10 22 17 V p-p V mV mA mA VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite 6.3 -103 -101 48.5 13.7 6.5 -103 -100 47 17.5 dB dBc dBc dBm dBm VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite 6.3 -86 -87 45 13.2 6.6 -90 -94 46 17.4 dB dBc dBc dBm dBm Rev. A | Page 3 of 31 1.2 -10 4.5 1.65 1.8 +10 1.4 -10 5.4 2.5 2.7 +10 ADL5205 Parameter1 200 MHz Noise Figure Increase for First 12 dB of Gain Reduction Noise Figure Second Harmonic Third Harmonic OIP3 Output P1dB 300 MHz Noise Figure Second Harmonic Third Harmonic OIP3 Output P1dB 500 MHz Noise Figure Second Harmonic Third Harmonic OIP3 Output P1dB DIGITAL INTERFACE Input Pins VIH VIL Input Leakage Current Output Pins Logic High (VOH) Logic Low (VOL) POWER-INTERFACE Supply Voltage (VPOS) Quiescent Current High Performance Mode Low Power Mode Power-Down Current Data Sheet Test Conditions/Comments 3.3 V Supply Min Typ Max Min 5 V Supply Typ Max Unit Gain code = 000000 to 001100 1.2 1.2 dB VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite 6.6 -75.5 -77 44 13 6.6 -75 -87.5 48.5 17 dB dBc dBc dBm dBm VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite 6.6 -63 -68 43 12.8 6.9 -64 -78 43.5 17.3 dB dBc dBc dBm dBm VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite 7.8 -58 -57.5 37 13.1 8.2 -61.5 -67.5 36 17.7 dB dBc dBc dBm dBm A0 to A5, B0 to B5, MODE1, MODE0, PWUPA, PWUPB, PM, LATCHA, LATCHB, SDIO Logic high Logic low Digital input voltage = 0 V to 3.3 V SDIO IOH = -2 mA IOL =2 mA VPOS 2 0 1 2 0 3 3.3 1.0 3 2.4 2.4 0.5 3.15 PM = low PM = high PWUPA and PWUPB = low VPOS 1.0 3.3 175 135 14 3.45 4.75 5 175 135 14 V V A 0.5 V V 5.25 V mA mA mA When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. 2 The maximum input swing of 8 V p-p is for the lowest gain setting of -9 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly to maintain the same maximum output swing. Rev. A | Page 4 of 31 Data Sheet ADL5205 TIMING SPECIFICATIONS Table 2. SPI Timing Parameters Parameter CSA or CSB to SCLK Setup Time Symbol tCS Min 20 SDIO to SCLK Setup Time SCLK to SDIO Hold Time SCLK Pulse Width SCLK Cycle Time SCLK to CSA or CSB Setup Time SCLK to SDIO Output Valid Delay tDS tDH tPW tSCLK tCH tDV 10 10 25 50 10 Typ Max Unit ns Test Conditions/Comments ns ns ns ns ns ns 20 During readback Timing Diagrams tPW tSCLK SCLK tCH tCS tDV ___ ___ CSA, CSB DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 Figure 2. SPI Interface Read/Write Mode Timing Diagram tDS tDS UPDN_DAT_x tPW UPDN_CLK_x UP RESET DOWN tDS tDH 13488-003 DNC tDH Figure 3. Up/Down Gain Control Timing Diagram LATCHA, LATCHB A5 TO A0 B5 TO B0 tDH Figure 4. Parallel Mode Timing Diagram Rev. A | Page 5 of 31 13488-004 SDIO D0 13488-002 tDS tDH ADL5205 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Differential Output Voltage Swing x Bandwidth Product Supply Voltage, VPOS PWUPA, PWUPB, A0 to A5, B0 to B5, MODE0, MODE1, PM, LATCH A, LATCH B Input Voltage (VINx+ ,VINx-) Differential Input Voltage ((VINx+) - (VINx-))1 Internal Power Dissipation Maximum Junction Temperature Operating Temperature Range Storage Temperature Range 1 Table 4 shows the thermal resistance from the die to ambient (JA), die to board (JB), and die to lead (JC), respectively. Rating 3 V-GHz 5.4 V -0.5 V to +3.6 V -0.5 V to +3.1 V 1 V 1000 mW 135C -40C to +85C -65C to +150C The differential input voltage limit is significantly lower than the maximum input swing of 8 V p-p. The maximum input swing is for the lowest gain setting of -9 dB. As the gain setting is increased, the maximum input swing must be reduced correspondingly to maintain the same maximum output swing. The differential input voltage limit takes effect at greater than ~14 dB, at which point there is no more resistive attenuation on the input and the signal presented on the pins goes directly on an input ESD protection circuit. Therefore, the input signal swing must be limited to a low value. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Thermal Resistance Package Type 40-Lead LFCSP JA 47.7 JB 24.4 JC 15.4 Unit C/W JUNCTION TO BOARD THERMAL IMPEDANCE The junction to board thermal impedance (JB) is the thermal impedance from the die to the leads of the ADL5205. The value given in Table 4 is based on the standard printed circuit board (PCB) described in the JESD51-7 standard for thermal testing of surface-mount components. PCB size and complexity (number of layers) affect JB; more layers tend to reduce thermal impedance slightly. If the PCB temperature is known, use the junction to board thermal impedance to calculate the die temperature (also known as the junction temperature) to ensure that the die temperature does not exceed the specified limit of 135C. For example, if the PCB temperature is 85C, the die temperature is given by TJ = TB + (PDISS x JB) The worst case power dissipation for the ADL5205 is 919 mW (5.25 V x 175 mA, see Table 1). Therefore, TJ is TJ = 85C + (0.919 W x 24.4C/W) = 107.4C ESD CAUTION Rev. A | Page 6 of 31 Data Sheet ADL5205 ADL5205 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 VOUTA- VOUTA+ DNC VPOS DNC DNC VPOS DNC VOUTB+ VOUTB- NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE. THIS IS THE GROUND (0V) REFERENCE FOR ALL THE VOLTAGES IN TABLE 1. 13488-005 GS0/FA_B/B2 UPDN_CLK_B/B1 UPDN_DAT_B/B0 LATCHB VINB- VINB+ PWUPB VCMB DNC DNC 11 12 13 14 15 16 17 18 19 20 CSA/A3 1 A4 2 A5 3 MODE1 4 MODE0 5 PM 6 DNC 7 SDIO/B5 8 SCLK/B4 9 GS1/CSB/B3 10 40 39 38 37 36 35 34 33 32 31 PIN 1 INDICATOR FA_A/A2 UPDN_CLK_A/A1 UPDN_DAT_A/A0 LATCHA VINA- VINA+ PWUPA VCMA DNC DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic CSA/A3 2 3 4 A4 A5 MODE1 5 MODE0 6 PM 7, 19, 20, 23, 25, 26, 28, 31, 32 8 DNC SDIO/B5 9 SCLK/B4 10 GS1/CSB/B3 11 GS0/FA_B/B2 12 UPDN_CLK_B/B1 13 UPDN_DAT_B/B0 Description Channel A Select in Serial Mode (CSA). When serial mode is enabled, a logic low selects Channel A. Bit 3 for Channel A in Parallel Gain Control Interface Mode (A3). Bit 4 for Channel A in Parallel Gain Control Interface Mode (A4). Bit 5 for Channel A in Parallel Gain Control Interface Mode (A5). MSB for Mode Control. Use both the MODE0 and MODE1 pins to select parallel, SPI, or up/down interface mode. LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or up/down interface mode. Power Mode. Set this pin to logic low to enable high performance mode, or logic high to enable low power mode. Do Not Connect. Do not connect to these pins. Serial Data Input and Output in SPI Mode (SDIO). Bit 5 for Channel B in Parallel Gain Control Interface Mode (B5). Serial Clock Input in SPI Mode (SCLK). Bit 4 for Channel B in Parallel Gain Control Interface (B4). MSB for the Gain Step Size Control in Up/Down Mode (GS1). Channel B Select in Serial Mode (CSB). When serial mode is enabled, a logic low selects Channel B. Bit 3 for Channel B in Parallel Gain Control Mode (B3). LSB for the Gain Step Size Control in Up/Down Mode (GS0). Fast Attack for Channel B (FA_B). In serial mode, a logic high on this pin attenuates Channel B according to the FA bit values in the control register. Bit 2 for Channel B in Parallel Gain Control Interface (B2). Clock Interface for the Channel B Up/Down Function (UPDN_CLK_B). Bit 1 for Channel B in Parallel Gain Control Interface Mode (B1). Data Pin for the Channel B Up/Down Function (UPDN_DAT_B). Bit 0 for Channel B in Parallel Gain Control Interface Mode (B0). Rev. A | Page 7 of 31 ADL5205 Data Sheet Pin No. 14 Mnemonic LATCHB 15 16 17 VINB- VINB+ PWUPB 18 21 22 24, 27 29 30 33 34 VCMB VOUTB- VOUTB+ VPOS VOUTA+ VOUTA- VCMA PWUPA 35 36 37 VINA+ VINA- LATCHA 38 UPDN_DAT_A/A0 39 UPDN_CLK_A/A1 40 FA_A/A2 EP GND Description Latch B. A logic low on this pin allows the gain to change on Channel B in parallel gain control interface mode. A logic high on this pin prevents gain changes. Channel B Negative Analog Input. Channel B Positive Analog Input. Channel B Power-Up. A logic high on this pin powers up Channel B, and a logic low on this pin disables it. Channel B Common-Mode Output. Channel B Negative Analog Output. Channel B Positive Analog Output. Positive Power Supply. Channel A Negative Analog Output. Channel A Positive Output. Channel A Common-Mode Output. Channel A Power-Up. A logic high on this pin powers up Channel A, and a logic low on this pin disables it. Channel A Positive Analog Input. Channel A Negative Analog Input. Latch A. A logic low on this pin allows the gain to change on Channel A in the parallel gain control interface mode. A logic high on this pin prevents gain changes. Data Pin for the Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A in Parallel Gain Control Interface Mode (A0). Clock Interface for the Channel A Up/Down Function (UPD_CLK_A). Bit 1 for Channel A in Parallel Gain Control Interface Mode (A1). Fast Attack for Channel A (FA_A). In serial mode, a logic high on this pin attenuates Channel A according to an FA SPI word. Bit 2 for Channel A in Parallel Gain Control Interface (A2). Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane. This is the ground (0 V) reference for all the voltages in Table 1. Rev. A | Page 8 of 31 Data Sheet ADL5205 TYPICAL PERFORMANCE CHARACTERISTICS 60 3.45V 3.3V 3.15V 5.25V 5.0V 4.75V 50 40 OIP3 (dBm) 20 25 85 TEMPERATURE (C) 141 139 0 100 200 300 400 500 FREQUENCY (MHz) Figure 9. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS at Three Gain Codes, High Performance Mode 60 50 40 137 OIP3 (dBm) 135 133 30 20 131 129 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C 10 127 25 85 TEMPERATURE (C) Figure 7. Supply Current vs. Temperature, PM = 1 30 0 13488-007 125 -40 100 200 300 400 500 FREQUENCY (MHz) Figure 10. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS for Three Temperatures at Maximum Gain, High Performance Mode 60 -40C +25C +85C 25 0 13488-010 SUPPLY CURRENT (mA) 0 3.45V 3.3V 3.15V 5.25V 5.0V 4.75V 143 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB 10 Figure 6. Supply Current vs. Temperature, PM = 0 145 30 13488-009 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 -40 13488-006 SUPPLY CURRENT (mA) Supply voltage (VPOS) = 3.3 V or 5 V, TA = 25C, ZLOAD = 200 , maximum gain (gain code = 000000), 2 V p-p composite differential output for intermodulation distortion (IMD) and OIP3, 2 V p-p differential output for second harmonic distortion (HD2) and third harmonic distortion (HD3), VCMA = VCMB = VPOS/2, unless otherwise noted. 50 20 40 OIP3 (dBm) 10 5 30 20 -5 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB 10 -10 -15 0 5 10 15 20 25 30 35 40 GAIN CODE Figure 8. Gain vs. Gain Code over Temperature at 200 MHz 0 0 100 200 300 FREQUENCY (MHz) 400 500 13488-011 0 13488-008 GAIN (dB) 15 Figure 11. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS at Three Gain Codes, Low Power Mode Rev. A | Page 9 of 31 Data Sheet 60 -20 50 -40 40 -60 IMD3 (dBc) 30 20 200 300 400 500 Figure 12. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS for Three Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode 0 50 -20 40 -40 20 200 300 400 500 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB -60 -80 5.25V 5V 4.75V 3.45V 3.3V 3.15V 0 100 -100 200 300 400 500 FREQUENCY (MHz) Figure 13. Output Third-Order Intercept (OIP3) vs. Frequency and VPOS Variance (5%), Maximum Gain, High Performance Mode -20 -120 13488-013 10 0 100 Figure 15. Two-Tone Output IMD3 vs. Frequency over VPOS for Three Gain Codes at 2 V p-p, High Performance Mode 60 30 0 FREQUENCY (MHz) HD2 (dBc) OIP3 (dBm) -140 13488-015 100 13488-012 0 -120 FREQUENCY (MHz) -40 0 100 200 300 400 500 FREQUENCY (MHz) Figure 16. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three Gain Codes, High Performance Mode 0 5V 26dB 5V 14dB 5V 6dB 3.3V 26dB 3.3V 14dB 3.3V 6dB -30 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C -20 -50 -40 -60 HD2 (dBc) IMD3 (dBc) -80 -100 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C 10 0 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB 13488-016 OIP3 (dBm) ADL5205 -70 -80 -60 -80 -90 -100 -100 0 100 200 300 FREQUENCY (MHz) 400 500 -120 13488-014 -120 Figure 14. Two-Tone Output IMD3 vs. Frequency over VPOS for Three Gain Codes at 2 V p-p Composite, Low Power Mode 0 100 200 300 FREQUENCY (MHz) 400 500 13488-017 -110 Figure 17. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three Temperatures at Maximum Gain, 2 V p-p, High Performance Mode Rev. A | Page 10 of 31 Data Sheet 0 ADL5205 0 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB -20 -20 -40 -80 -80 -100 -100 -120 0 100 200 300 400 500 FREQUENCY (MHz) Figure 18. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three Gain Codes at 2 V p-p Composite, Low Power Mode 0 -120 0 100 200 300 400 500 FREQUENCY (MHz) Figure 21. Third Harmonic Distortion (HD3) vs. Frequency vs. VPOS for Three Temperatures at Maximum Gain, 2 V p-p Composite, High Performance Mode 0 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C -20 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB -20 -40 -60 -60 -80 -80 -100 -100 0 100 200 300 400 500 FREQUENCY (MHz) Figure 19. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode 0 -120 13488-019 -120 0 200 300 400 500 FREQUENCY (MHz) Figure 22. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three Gain Codes at 2 V p-p Composite, Low Power Mode 0 5V, 26dB 5V, 14dB 5V, 6dB 3.3V, 26dB 3.3V, 14dB 3.3V, 6dB -20 100 13488-022 HD3 (dBc) -40 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C -20 -40 HD3 (dBc) -40 -60 -60 -80 -80 -100 -100 0 100 200 300 FREQUENCY (MHz) 400 500 -120 13488-020 -120 Figure 20. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three Gain Codes at 2 V p-p Composite, High Performance Mode 0 100 200 300 FREQUENCY (MHz) 400 500 13488-023 HD2 (dBc) -60 13488-021 HD3 (dBc) -60 13488-018 HD2 (dBc) -40 HD3 (dBc) 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C Figure 23. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode Rev. A | Page 11 of 31 ADL5205 Data Sheet 40 40 35 35 13dB TO -9dB NOISE FIGURE (dB) 25 20 15 25 20 15 10 10 5 5 GAIN = 26dB TO 14dB GAIN = 26dB TO 14dB 0 100 200 300 400 500 FREQUENCY (MHz) 0 13488-024 0 0 100 200 300 400 500 FREQUENCY (MHz) Figure 24. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 5 V, High Performance Mode 13488-027 NOISE FIGURE (dB) 13dB TO -9dB 30 30 Figure 27. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 3.3 V, Low Power Mode 20 40 19 35 13dB TO -9dB 18 17 OP1dB (dBm) NOISE FIGURE (dB) 30 25 20 15 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C 16 15 14 13 10 12 5 11 0 100 200 300 400 500 FREQUENCY (MHz) 10 13488-025 0 Figure 25. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 3.3 V, High Performance Mode 0 100 200 300 400 500 FREQUENCY (MHz) 13488-028 GAIN = 26dB TO 14dB Figure 28. Output 1 dB Compression Point (OP1dB) vs. Frequency at Maximum Gain, High Performance Mode 20 40 19 35 13dB TO -9dB 18 17 25 20 15 16 15 14 13 10 5V, +85C 5V, +25C 5V, -40C 3.3V, +85C 3.3V, +25C 3.3V, -40C 12 5 11 GAIN = 26dB TO 14dB 0 100 200 300 FREQUENCY (MHz) 400 500 10 13488-026 0 Figure 26. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 5 V, Low Power Mode 0 100 200 300 FREQUENCY (MHz) 400 500 13488-029 OP1dB (dBm) NOISE FIGURE (dB) 30 Figure 29. Output 1 dB Compression Point (OP1dB) vs. Frequency at Maximum Gain, Low Power Mode Rev. A | Page 12 of 31 Data Sheet ADL5205 40 30 20 VOLTAGE GAIN (dB) 0 -20 -40 -60 50 5000 500 FREQUENCY (MHz) 0 -10 -30 10M Figure 30. Differential S-Parameters (SDD21, SDD12, SDD11, SDD22) vs. Frequency 100M 1G FREQUENCY (Hz) 13488-133 -100 10 -20 SDD11 SDD12 SDD21 SDD22 -80 13488-030 S-PARAMETERS (dB) 20 Figure 33. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 5 V, High Performance Mode 30 VOLTAGE GAIN (dB) MAXIMUM VOLTAGE GAIN (dB) 20 10 0 -10 100M 1G FREQUENCY (Hz) -30 10M 13488-032 Figure 34. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 3.3 V, High Performance Mode 30 30 20 20 VOLTAGE GAIN (dB) VOLTAGE GAIN (dB) 1G FREQUENCY (Hz) Figure 31. Maximum Voltage Gain vs. Frequency over Temperature at VPOS = 3.3 V 10 0 -10 -20 10 0 -10 -20 100M FREQUENCY (Hz) 1G -30 10M 13488-132 -30 10M 100M 100M FREQUENCY (Hz) Figure 32. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 3.3 V, Low Power Mode 1G 13488-135 10M 13488-134 -20 -40C +25C +85C Figure 35. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 5 V, Low Power Mode Rev. A | Page 13 of 31 ADL5205 150 100 -20 50 -25 0 -30 -50 -35 -100 -40 -150 -45 -200 100 1k 2 -250 FREQUENCY (MHz) CH2 500mV/div 50 BW:8.0G 20.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 12.5GS/s 80.0ps/pt Figure 39. Enable Time Domain Response at VPOS = 5 V 250 -0.5 200 -1.0 150 -1.5 100 -2.0 50 -2.5 0 -3.0 -50 -3.5 -100 -4.0 -4.5 -5.0 SDD22 PHASE (Degrees) T -150 +26dB GAIN MAGNITUDE -9dB GAIN MAGNITUDE +26dB PHASE -9dB PHASE 3 2 -200 1000 -250 13488-138 SDD22 MAGNITUDE (dB) Figure 36. Differential Input Reflection (SDD11) Magnitude and Phase vs. Frequency 0 FREQUENCY (MHz) CH2 500mV/div 50 BW:8.0G 20.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 12.5GS/s 80.0ps/pt 10 0.8 8 0.4 6 0 4 -0.4 2 -0.8 -6 -3 0 3 6 9 12 15 PROGRAMMED GAIN (dB) 18 21 24 26 -1.2 T CUMULATIVE GAIN STEP ERROR (dB) 1.2 3 2 13488-036 PHASEVARIATION(Degrees) 12 1.56V Figure 40. Enable Time Domain Response at VPOS = 3.3 V Figure 37. Differential Output Reflection (SDD22) Magnitude and Phase vs. Frequency 0 -9 1.57V 13488-038 -50 10 3 13488-037 -15 Figure 38. Phase Variation and Cumulative Gain Step Error vs. Programmed Gain, Frequency = 200 MHz, VPOS = 3.3 V, 2 V p-p Composite Rev. A | Page 14 of 31 CH2 500mV/div 50 BW:8.0G 20.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 6.25GS/s 160ps/pt 1.57V Figure 41. Disable Time Domain Response at VPOS = 5 V 13488-039 -10 T 200 SDD11 PHASE (Degrees) -5 SDD11 MAGNITUDE (dB) 250 +26dB GAIN MAGNITUDE -9dB GAIN MAGNITUDE +26dB GAIN PHASE -9dB GAIN PHASE 13488-034 0 Data Sheet Data Sheet ADL5205 70 T 60 CMRR (dB) 50 3 40 CMRR 5V CMRR 3.3V 30 20 2 1.57V 0 10 13488-040 CH2 500mV/div 50 BW:8.0G 20.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 6.25GS/s 160ps/pt 100 1k FREQUENCY (MHz) Figure 42. Enable Time Domain Response at VPOS = 3.3 V 13488-043 10 Figure 45. CMRR vs. Frequency at Maximum Gain 250 T SETTLING TO WITHIN 1 dB, FOR GAIN STEP FROM -9dB TO 26dB SETTLING TIME (ns) 200 3 150 100 5V 3.3V 1.53V 0 1.0 13488-041 CH2 500mV/div 50 BW:8.0G 40.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 25.0GS/s 40.0ps/pt Figure 43. Fast Attack Step Time Domain Response at VPOS = 5 V 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 VCMA OR VCMB (V) 13488-147 50 2 Figure 46. Maximum Gain Transition Settling Time vs. Output CommonMode Voltage (VCMA or VCMB) 1000 T GROUP DELAY (ps) 950 3 900 850 1.53V 800 10 13488-042 CH2 500mV/div 50 BW:8.0G 20.0ns/div A CH2 CH3 300mV/div 50 BW:5.0G 25.0GS/s 40.0ps/pt Figure 44. Fast Attack Step Time Domain Response at VPOS = 3.3 V 3.3V, PM = 0 3.3V, PM = 1 5V, PM = 0 5V, PM = 1 100 FREQUENCY (MHz) 1000 13488-148 2 Figure 47. Group Delay at Maximum Gain vs. Frequency over VPOS and Power Modes Rev. A | Page 15 of 31 ADL5205 Data Sheet 0 3.3V DISABLED STATE 5V DISABLED STATE 3.3V ENABLED 5V ENABLED CH A TO CH B CH B TO CH A REVERSE ISOLATION (dB) CHANNEL ISOLATION (dB) -20 -40 -60 -80 Figure 48. Reverse Isolation vs. Frequency 13488-149 FREQUENCY (Hz) -120 10 100 FREQUENCY (MHz) 1000 13488-150 -100 Figure 49. Channel Isolation vs. Frequency for Channel A and Channel B Rev. A | Page 16 of 31 Data Sheet ADL5205 BASIC STRUCTURE The ADL5205 is a dual differential, digitally controlled variable gain amplifier (DGA). Each DGA consists of a 100 differential input, digitally controlled passive attenuator followed by a digitally controlled gain amplifier. The input, digitally controlled, binary weighted attenuator has a range of 0 dB to 23 dB with 1 dB steps, and the amplifier has a range of 14 dB to 26 dB, also with 1 dB steps. On-chip logic circuitry maps the gain codes such that the first 12 dB of gain reduction from the maximum gain are accomplished using the digitally controlled gain amplifier, only. This topology allows the first 12 dB of gain reduction to be accompanied by typically 1.2 dB of total noise figure degradation (at 200 MHz). The OIP3 also remains nearly constant over the first 12 dB of gain range. The noise figure for the DGA increases by 1 dB for each decibel of attenuation within the remaining 23 dB attenuation range. The differential output impedance of the amplifier is 10 . The output common-mode voltages of the ADL5205 are controlled by the voltages on the VCMA and VCMB pins. Each of these pins is connected internally through 5 k resistors to the VPOS pin as well as to the exposed pad (EP). As a result, the commonmode output voltage at each channel is preset internally to half of the supply voltage at VPOS. Alternatively, the VCMA and VCMB pins can be connected to the common-mode voltage reference output from an ADC, and thus the common-mode levels between the two devices can be matched without requiring any external components. SIDE A SPI WITH FA, PARALLEL WITH LATCH, UP/DOWN LOGIC 100 0dB TO 23dB VINA- The ADL5205 features three different gain control interfaces: serial, parallel, or up/down control, determined by the combination of the MODE1 and MODE0 pins. For details on controlling the gain in each of these modes, see the Digital Interface Overview section. In general, the gain step size is 1 dB; however, larger step sizes can be programmed as described in the Digital Interface Overview section. Each amplifier has a maximum gain of +26 dB (Gain Code 000000) to -9 dB (Gain Code 100011 to Gain Code 111111). Using the performance mode (PM) pin, users can lower the power consumption of the device with a slight degradation in linearity performance. COMMON-MODE VOLTAGE The ADL5205 is flexible in terms of input/output coupling. It can be ac-coupled or dc-coupled at the inputs and/or outputs within the specified output common-mode levels of 1.2 V to 2.7 V, depending on the supply voltage. If no external output common-mode voltage is applied, the input and output commonmode voltages are set internally to half of the supply voltage. Rev. A | Page 17 of 31 VPOS ADL5205 CHANNEL A VINA+ CONTROL/LOGIC CIRCUITRY PWUPA MODE0 MODE1 PM 14dB TO 26dB VOUTA- 10 VOUTA+ CONTROL CIRCUITRY CIRCUITRY DUPLICATED FOR CHANNEL B GND Figure 50. Basic Structure 13488-054 THEORY OF OPERATION ADL5205 Data Sheet APPLICATIONS INFORMATION To enable each channel of the ADL5205, pull the PWUPA pin or the PWUPB pin high (2.0 V PWUPA/PWUPB 3.3 V). A logic low on the PWUPA pin or the PWUPB pin sets the channel to sleep mode, reducing the current consumption to approximately 7 mA per channel. The VCMA and the VCMB pins are the reference inputs for the output common-mode voltage of each channel, and they must be decoupled with 0.1 F capacitors. BASIC CONNECTIONS Figure 51 shows the basic connections for operating the ADL5205. Apply a voltage of 3.3 V or 5 V to the VPOS pins. Decouple each supply pin with at least one low inductance, surface-mount ceramic capacitor of 0.1 F placed as close to the device as possible. The differential outputs have a dc common-mode voltage that is approximately half of the supply; therefore, decouple these outputs using 0.1 F capacitors to the balanced load. The balanced differential inputs have the same dc common-mode voltage as the outputs; the inputs are decoupled using 0.1 F capacitors as well. The digital pins, mode control pins, associated SPI pins, and parallel gain control pins, (PM, PWUPA, and PWUPB) operatefrom a 3.3 V voltage. BALANCED SOURCE AC 0.1F CHANNEL B PARALLEL INTERFACE 0.1F 3.3V EXPOSED PAD ADL5205 VOUTA- VOUTA+ DNC VPOS DNC DNC VPOS DNC VOUTB+ VOUTB- 30 29 28 27 26 25 24 23 22 21 0.1F 0.1F BALANCED LOAD 0.1F 0.1F VPOS 10F 0.1F BALANCED LOAD 0.1F 11 12 13 14 15 16 17 18 19 20 3.3V CSA/A3 A4 A5 MODE1 MODE0 PM DNC SDIO/B5 SCLK/B4 GS1/CSB/B3 GS0/FA_B/B2 UPDN_CLK_B/B1 UPDN_DAT_B/B0 LATCHB VINB- VINB+ PWUPB VCMB DNC DNC 3.3V 1 2 3 4 5 6 7 8 9 10 FA_A/A2 UPDN_CLK_A/A1 UPDN_DAT_A/A0 LATCHA VINA- VINA+ PWUPA VCMA DNC DNC 40 39 38 37 36 35 34 3.3V 33 32 31 0.1F 0.1F CHANNEL B PARALLEL INTERFACE 3.3V 0.1F 0.1F NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE. THIS IS THE GROUND (0V) REFERENCE FOR ALL THE VOLTAGES IN TABLE 1. Figure 51. Basic Connections Rev. A | Page 18 of 31 13488-053 BALANCED SOURCE AC Data Sheet ADL5205 DIGITAL INTERFACE OVERVIEW or CSB low. By simultaneously pulling the CSA and CSB pins low, the same data can be written to both SPI registers. The three digital control interface options of the ADL5205 DGA are, respectively, Parallel control interface Serial peripheral interface Gain step up/down interface SPI fast attack mode is controlled by the FA_A or FA_B pins. A logic high on the FA_A pin or FA_B pin results in an attenuation selected by the FA1 and the FA0 bits in the SPI register. The digital control interface selection is made via two digital pins, MODE1 and MODE0, as shown in Table 6. Additionally, there are three power mode control pins, PM, PWUPA, and PWUPB. PM selects between the high performance and low power modes, whereas PWUPA and PWUPB enable (powerup) the corresponding channel. The gain in each channel is controlled by a 6-bit binary code (A5 to A0 and B5 to B0). Table 7. SPI 2-Bit Attenuation Step Size Truth Table FA1 0 0 1 1 The same physical pins are shared between three interfaces, resulting in as many as three different functions per digital pin (see Table 5). The up/down interface uses two digital pins to control the gain. When the UPDN_DAT_x pin is low, the gain for the corresponding channel is increased by a clock pulse on the UPDN_CLK_x pin (rising and falling edges). When the UPDN_DAT_x pin is high, the corresponding gain is decreased by a clock pulse on the UPDN_CLK_x pin. Reset is detected when the rising edge of UPDN_CLK_x latches one polarity on UPDN_DAT_x, and the falling edge latches the opposite polarity. Reset results in the minimum gain code of 111111. Interface Parallel Serial (SPI) Up/down Up/down Parallel Digital Interface The parallel digital interface uses six gain control bits and a latch pin per amplifier. The latch pin controls whether the input data latch is transparent (logic low) or latched (logic high). In transparent mode, the gain changes as the input gain control bits change. In latched mode, the gain is determined by the latched gain setting and is not changed by changing the input gain control bits. UPDN_DAT_x UPDN_CLK_x UP RESET Figure 52. Up/Down Gain Control Timing The step size is selectable by the GS1 and GS0 pins. The default step size is 1 dB. The gain code count rails at the top and bottom of the control range. Serial Peripheral Interface (SPI) The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The SPI data register consists of two bytes: six gain control bits (D0 to D5), two attenuation step size address bits (FA0 and FA1), one read/write bit (R/W), and seven don't care bits (X), as shown in Figure 53. Table 8. Step Size Control Truth Table GS1 0 0 1 1 The SPI uses a bidirectional pin (SDIO) for writing to the SPI register and for reading from the SPI register. To write to the SPI register, pull the CSA or the CSB pin low and apply 16 clock pulses to shift the 16 bits into the corresponding SPI register, MSB first. Individual channel SPI registers can be selected by pulling CSA LSB DN 13488-055 MODE0 0 1 0 1 Step Size (dB) 2 4 8 16 Up/Down Interface Table 6. Digital Control Interface Selection Truth Table MODE1 0 0 1 1 FA0 0 1 0 1 GS0 0 1 0 1 Step Size (dB) 1 2 4 8 MSB LSB MSB DATA D0 D1 D2 D3 D4 D5 FA0 FA1 R/W X X X X X X X DON'T CARE (7 BITS) READ/WRITE FAST ATTACK ATTENUATION STEP SIZE ADDRESS GAIN CONTROL Figure 53. 16-Bit SPI Register Rev. A | Page 19 of 31 13488-056 * * * SPI register read back operation is described in the SPI Read section. Because there is only one SDIO line, the control register of each channel must be read back individually. ADL5205 Data Sheet Table 9. Gain Code vs. Voltage Gain CSA, CSB SCLK SDIO (IN) SDIO (OUT) 13488-047 WRITE VALUE WRITE 0x0054 R/W BIT LOW ON SDIO_IN DATA WRITTEN ON RISING CLOCK EDGE Figure 54. Write Gain Control Word CSA, CSB SCLK SDIO (IN) SDIO (OUT) 13488-048 Voltage Gain (dB) +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 SET UP READ WRITE 0x0100 R/W BIT LOW ON SDIO_OUT Figure 55. Write Logic 1 into R/W Bit CSA, CSB SCLK SDIO (IN) SDIO OUTPUT ENABLED SDIO (OUT) PERFORM READ READ 0x0154 R/W BIT HIGH DATA READ ON FALLING CLOCK EDGE 13488-049 6-Bit Binary Gain Code, D5 to D0 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 to 111111 Figure 56. Perform Read SCLK SPI READ Rev. A | Page 20 of 31 1 3 SDIO CSA OR CSB 2 CH1 1V/DIV CH3 1V/DIV CH2 1V/DIV A CH2 Figure 57. Write Gain Control Value, 0x0054 1.6V 13488-050 The ADL5205 can be read back only in the serial mode, during a read cycle (from CSA/CSB low to CSA/CSB high) after the R/W bit is set high in the previous cycle. During the read cycle, data changes at each rising edge of SCLK, and can be latched using the falling edge of SCLK. There is no continual read operation. A logic high (1) must be written into the R/W bit to enable the subsequent read cycle. The sequence for reading back is shown in Figure 54 to Figure 57, showing the operation of the input and output functions of the SDIO pin. The actual waveforms during the readback process are shown in Figure 57 to Figure 59. SDIO is enabled as an output only during the read cycle in Figure 57. Data Sheet ADL5205 FILTER L3A R1A C4 AMP L1B C2B ADC R1B L3B 13488-161 C2A L1A SCLK VCM 1 SDIO Table 10. Component Values for a 500 MHz Acquisition System CSA OR CSB CH1 1V CH3 1V CH2 1V A CH2 1.6V 13488-051 2 Figure 58. Write Read Setup Value, 0x0100 SCLK Value 1/2 ADL5205 22 nH 6.8 pF L3A, L3B C4 22 nH 1.5 pF R1A, R1B ADC 10 1/2 AD9680 Description/Comments One channel Q 50 at 500 MHz Final value depends on PCB parasitics Q 50 at 500 MHz Final value depends on PCB parasitics Not applicable One channel, input impedance set to 100 NOISE FIGURE vs. GAIN SETTING 1 3 Component Amplifier L1A, L1B C2A, C2B Because of the architecture of the ADL5205, the noise figure does not degrade significantly for the first 12 dB of gain reduction from the maximum gain setting. The noise figure increases by 2 dB only during the first 12 dB of gain reduction, after which it resumes the 1 dB degradation for each dB of gain reduction. SDIO CSA OR CSB 2 CH2 1V A CH2 760mV 45 13488-052 CH1 1V CH3 1V 40 Figure 59. Read Back Value, 0x0154 ADC INTERFACING A typical data acquisition system using the ADL5205 together with an antialiasing filter and an ADC is shown in Figure 60. The main role of the filter after the amplifier is for attenuating the broadband noise and out-of-band harmonics generated by the amplifier. Component values for a 500 MHz acquisition bandwidth are listed in Table 10. Without this filter, the out-ofband noise and distortion components alias back into the Nyquist band, resulting in a reduction of signal-to-noise ratio. The design of the filter preceding the ADL5205 amplifier is more specific to the system rejection requirements for the acquisition system, NOISE FIGURE (dB) 35 Rev. A | Page 21 of 31 30 REGULAR ATTENUATORAMPLIFIER CASCADE 25 20 15 ADL5205 AT 200 MHz 5V HP 11dB IMPROVEMENT 10 1.2dB INCREASE 5 0 -10 -5 0 5 10 15 20 GAIN (dB) Figure 61. Noise Figure vs. Gain 25 30 13488-162 3 Figure 60. ADC Interface (One of Two Channels Shown) ADL5205 Data Sheet EVALUATION BOARD OVERVIEW The ADL5205-EVALZ evaluation board allows the manual control of the ADL5205 device through the serial and the parallel interface ports, as well as the control of the device through the USB port on a Microsoft(R) Windows(R) PC via the system demonstration platform (SDP) interface board. A 3.3 V low dropout (LDO) voltage regulator supplies the logic circuits when the device is running on a 5 V supply. On-board baluns convert single-ended input signals to differential form for input to the device and convert the differential output signals of the device to single-ended form for output. To bypass these baluns, rearrange the 0 resistors on the board as described in the Signal Inputs and Outputs section. CHANNEL B INPUTS The ADL5205-EVALZ provides all of the support circuitry required to operate the ADL5205 in its various modes and configurations. Figure 62 shows the typical bench setup used to evaluate the performance of the ADL5205. POWER SUPPLY INTERFACE The ADL5205-EVALZ evaluation board requires either a 3.3 V or 5 V power supply, and an optional negative supply to pull down the output common-mode dc level to match the ADCs that require a lower common-mode level. If an external 3.3 V supply is used, connect it to the test point labeled 3P3V. If a 5 V supply is used, connect it to the test point labeled 5V. Similarly, if an external negative supply is used, connect it to the VNEG test point shown in Figure 62. CHANNEL B MODE CONTROLS SWITCHES PARALLEL INTERFACE ADL5205 CHANNEL B OUTPUTS VNEG SDP INTERFACE 3.3V SUPPLY CLUSTER 5V CHANNEL A INPUTS CHANNEL A CONTROLS Figure 62. ADL5205-EVALZ Evaluation Board Rev. A | Page 22 of 31 SERIAL INTERFACE 13488-058 CHANNEL A OUTPUTS Data Sheet ADL5205 The power supply jumper configurations (S1 to S3) required for selecting the evaluation board analog supply (VCC) and digital supply (VDD) from the external 3.3 V or 5 V power supply are shown in Table 11. When using a 5 V supply, enable the on-board 3.3 V voltage regulator and select it using the S3 and S2 jumpers, respectively, to provide digital supply (VDD) to the pull-up resistors for logic signals. Table 11. Power Supply Selection Jumpers Jumper S1 S2 S3 Function VCC selection VDD selection VDD LDO enable Supply Selection VCC = 3.3 V VCC = 5 V 3P3V 5V 3P3V VREG AGND 5V SIGNAL INPUTS AND OUTPUTS Signal inputs and outputs for each channel come through a pair of SMA connectors. In the default configuration, on-board baluns convert single-ended signals from VINA- and VINB- into differential signals to the device. Similarly, differential output signals from the device are converted through the on-board baluns into single-ended form to the VOUTA+ and VOUTB+ connectors. MANUAL CONTROLS Three sets of switches provide the manual control of the states of the device. Their functions are listed in Table 12. When the individual switch is in the up position, the signal controlled by the switch is set to logic high. Table 12. Switch Block Functions Switch Block SW1 Position 1 Position 2 Position 3 Position 4 Position 5 Position 6 Position 7 Position 8 SW2 Position 1 Position 2 Position 3 SW3 Position 1 Position 2 Position 3 Position 4 Position 5 Position 6 Position 7 Position 8 Function Channel B control (eight positions) PWUPB LATCHB B0 B1 B2 B3 B4 B5 Mode control (three positions) Power mode (PM) MODE0 (M0) MODE1 (M1) Channel A control (eight positions) A5 A4 A3 A2 A1 A0 LATCHA PWUPA Device Pin No. 17 14 13 12 11 10 9 8 6 5 4 3 2 1 40 39 38 37 34 Mode Switches When the power mode (PM) switch is up (logic high or Logic 1), the device is in low power mode. When the switch is down (logic low or Logic 0), the device is in high performance mode. MODE1 and MODE0 (labeled M1 and M0 on the PCB) select one of three interface modes for the device (parallel, serial/SPI, or up/down mode), as shown in Table 13. There is no functional difference between the mode switch settings of 10 and 11. Table 13. Mode Switch Settings MODE1, MODE0 00 01 10 11 Interface Parallel Serial (SPI) Up/down Up/down Channel Control Switches The channel control switches include PWUPA, LATCHA, and A5 to A0 for Channel A and PWUPB, LATCHB, and B5 to B0 for Channel B. PWUPA and PWUPB are the up positions (logic high) that turn on their respective channels. When PM is set to logic low (high performance mode), the total current consumption increases by approximately 81 mA (that is, one half of the difference between the enabled current of 175 mA and the disabled current of 14 mA) when each channel is enabled. When the PM is set to logic high (low power mode), the total current consumption increases by approximately 61 mA (that is, one half of the difference between the enabled current of 135 mA and the disabled current of 14 mA) when each channel is enabled. The LATCHA and LATCHB switches are used with the gain control input bits (A5 to A0 and B5 to B0) to control the corresponding channel voltage gain. When these switches are in the down (logic low) position, the gain changes with the position of the gain control switches. When these switches are in the up position, the last gain setting is latched into the corresponding channel of the ADL5205, and the gain stops changing. For Bits[A5:A0] and Bits[B5:B0], the following equation determines the voltage gain of each channel of the ADL5205: Gain = 26 - [A5:A0] dB where [A5:A0] is the value representing the binary string formed by Bits[A5:A0] from 0 to 35. When this value exceeds 35, the gain is set to minimum (-9 dB). The voltage gain for Channel B is changed by Bits[B5:B0] in the same manner. Rev. A | Page 23 of 31 ADL5205 Data Sheet PARALLEL INTERFACE SERIAL INTERFACE The functions of Parallel Interface Connector P3 are identical to those of the switches in the switch block. The pinout of the Parallel Interface Connector P3 is listed in Table 14. Logic levels on the P3 pins override the corresponding switch setting. As a result, the switches for PWUPA and PWUPB must be in the up position when using the parallel interface to control the device. When the mode switches are in the 01 position, the ADL5205 operates in the serial/SPI mode. The pins that are relevant in the serial/SPI mode are brought out to Serial Interface Connector P2. The pinout for Serial Interface Connector P2 is listed in Table 15. Note that only four pins (plus AGND) are used for the SPI, and they include the following: Table 14. Parallel Interface Pinout (P3) * Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function PWUPB AGND LATCHB AGND B0 AGND B1 AGND B2 AGND B3 AGND B4 AGND B5 AGND VDD AGND Power mode (PM) AGND MODE0 AGND MODE1 AGND A5 AGND A4 AGND A3 AGND A2 AGND A1 AGND A0 AGND LATCHA AGND PWUPA AGND * * CSA and CSB are the active low serial port enable pins for Channel A and Channel B, respectively. SDIO is the serial data input and output line. SDIO is a bidirectional pin. SCLK is the serial clock pin. For detailed operations and timing diagrams of the serial port interface, see the Serial Peripheral Interface (SPI) section. These signals operate at 3.3 V logic levels. The CSA and CSB lines can be tied together to program both channels at the same time. Table 15. Serial Interface Connector (P2) Pinout Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Rev. A | Page 24 of 31 Function PWUPA Not applicable FA_A Not applicable CSA Not applicable PM Not applicable SDIO Not applicable SCLK Not applicable CSB Not applicable FA_B Not applicable PWUPB Not applicable AGND Not applicable Data Sheet ADL5205 STANDARD DEVELOPMENT PLATFORM (SDP) INTERFACE The ADL5205-EVALZ connects to the universal serial bus (USB) port on a Windows-based PC through an SDP board. The SDP interface board plugs into the P1 connector on the ADL5205-EVALZ evaluation board and provides all the digital handshaking to communicate with the USB. Use the SDP with the ADL5205 control software on the PC. To control the ADL5205 through the USB to SDP interface, nine jumpers must be inserted from the odd numbered pins (Pin 1, Pin 3, Pin 5, Pin 7, Pin 9, Pin 11, Pin 13, Pin 15, and Pin 17) to the even numbered pins (Pin 2, Pin 4, Pin 6, Pin 8, Pin 10, Pin 12, Pin 14, Pin 16, and Pin 18 on the P2 connector, as shown in Figure 63. No jumper is needed for Pin 19 and Pin 20. SDP INTERFACE BOARD A dynamically loadable library (DLL), sdpApi1.dll, provides the software interface to the actual hardware. The control program, using the USB interface, can communicate with the hardware through interface functions in this DLL. EVALUATION BOARD CONTROL SOFTWARE Two separate programs are available for use with a Windowsbased PC to control the ADL5205 through the USB to SDP interface: a command line control program and a program with a graphical user interface. COMMAND LINE CONTROL PROGRAM The adl5205_regw_x_x.exe, where x_x represents the revision of the program, is a command line program that takes the 8-bit value represented by the command line argument and writes into the control register of the ADL5205. The syntax for the program is shown in Figure 64, which contains a sample run of the command line control program, showing the help listing. GRAPHICAL USER INTERFACE (GUI) PROGRAM SDP JUMPERS USB 13488-059 The adl5205_ctrlsw_y_y.exe, where y_y represents the revision of the program, is a GUI program that allows the control of the ADL5205 functions through an on-screen display. The ADL5205 gain and modes of operation can be controlled interactively using icons on the computer screen. A typical display from the GUI control is shown in Figure 65, and the corresponding control functions are listed in Table 16. 13488-165 Figure 63. SDP Interface Board Figure 64. Sample Listing Showing Usage of the Command Line Program Rev. A | Page 25 of 31 ADL5205 Data Sheet A B E C F G 13488-060 D Figure 65. Main Screen of the ADL5205 Control Software Table 16. Features on the Control Software Main Screen Feature A B C D E F G Description SDP and evaluation board connection status Gain setting displays Gain control for Channel A and Channel B Gain setting readback Power mode (high performance (HP) or low power (LP)) Channel A Fast attack step size Channel B fast attack step size Rev. A | Page 26 of 31 Rev. A | Page 27 of 31 1 AGND 2 3 4 5 1 VINB+ AGND 2 3 45 VINB- AGND 2 3 4 5 VINA1 AGND 2 3 4 5 INPUTB+ INPUTB- INPUTA- AGND AGND R2 0 R1 0 0 DNI R18 0 R29 0 0 DNI C6 0.1UF AGND R15 R19 0 TC2-1T+ 0 R24 0 R14 R21 0 DNI T3 0 R20 C1 0.1UF AGND R16 0 R8 R17 0 TC2-1T+ T1 0 DNI R7 AGND R101 AGND R102 VINA+ INPUTA+ 1 3 2 1 3 2 1 S2 S3 3 2 1 S1 C2 C3 0.1UF C8 0.1UF C7 0.1UF Figure 66. ADL5205-EVALZ Evaluation Board Schematic, Page 1 AGND GND1 1 BLK PWUPB MODE0 MODE1 LATCHA LATCHB PM VINB_POS VINB_NEG VINA_NEG VINA_POS GND2 1 BLK AGND SAMTECTSW10608GS3PIN 0.1UF 0 DNI 0 DNI VCC GND3 1 BLK SD_N 5V 3P3V VDD VREG 3P3V C15 0.1UF 35 VINA+ 36 VINA15 VINB16 VINB+ 37 LATCH_A 14 LATCH_B 6 PM 5 MODE0 4 MODE1 PWUPA REGULATOR VCC 6 ERR_N SD_N GND 4 5 AGND A1 ADP3303ARZ-3.3 3 NR 1 7 IN OUT 8 IN1 OUT1 2 AGND C21 1UF 1 RED 3P3V RED 5V 34 23 24 25 26 27 28 EOUT ADL5205 U1 AGND C14 100PF C13 10UF VCC 1 RED VCC C11 0.1UF AGND AGND VCMB C19 0.1UF C12 0.1UF VCMA AGND C18 100PF YEL VCMB 1 YEL 1 VCMA 30 29 31 32 20 19 22 21 38 39 40 1 2 3 13 12 11 10 9 8 AGND R51 330K C23 10UF 1 RED VREG C26 0.01UF VOUTAVOUTA+ NC NC NC NC VOUTB+ VOUTBUPDN_DAT/A0 UPDN_CLK/A1 FA/A2 CSA_N/A3 A4 A5 UPDN_DAT/B0 UPDN_CLK/B1 GS0/FA/B2 GS1/CSB/B3 SCLK/B4 SDIO/B5 PWUPA NC VPOS NC NC VPOS NC 17 PWUPB 7 NC 18 GND VCMB 33 VCMA PAD PAD 0 DNI R103 0 DNI R104 1 C20 10UF VDD 1 RED VDD 0.1UF C9 0.1UF C5 0.1UF SDIO_B5 SCLK_B4 GS0_FA_B_B2 GS1_CSB_N_B3 UPDN_CLK_B_B1 UPDN_DAT_B_B0 A5 A4 CSA_N_A3 FA_A_A2 UPDN_CLK_A_A1 UPDN_DAT_A_A0 0.1UF VOUTB_NEG C10 VOUTB_POS VOUTA_POS VOUTA_NEG C4 R3 R10 84.5 R35 0 AGND 0 DNI R38 0.1UF AGND C17 84.5 R9 0 R98 50 R42 R12 34.8 R11 34.8 R99 T4 AGND 0 DNI E1 2 0 R45 0 R44 1 0 DNI VNEG BLK C24 2.2UF VOUTA+ VOUTA- AGND VOUTB- AGND 5 4 3 2 1 AGND 5 4 3 2 VOUTB+ 5 4 3 2 VOUTB+ 1 R46 VOUTB- AGND VNEG 95OHM AT 100MHZ 1 2 4 3 PRI SEC 1 6 TC1-1-13M+ 0 DNI 0 R34 0 DNI 50 R47 0 R48 DNI 0 VOUTA+ 1 AGND 5 4 3 2 VOUTA- 1 0 AGND R49 R43 50 R41 NC T2 NC 2 4 3 SEC PRI 1 6 TC1-1-13M+ 0 DNI R50 R40 84.5 R6 34.8 R5 34.8 50 R39 0 R37 R4 0.1UF C16 84.5 NEG_VOLTAGE 0 R36 DNI R32 AGND 0 R31 R30 0 DNI 13488-061 5V Data Sheet ADL5205 EVALUATION BOARD SCHEMATICS AND LAYOUT AGND SW1 SW2 1B 2B 3B 1B 1A 2B 2A 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B 5435802-9 SW3 5435802-2 1A 2A 3A 1B 1A 2B 2A 3B 3A 4B 4A 5B 5A 6B 6A 7B 7A 8B 8A 5435802-9 33K R90 33K R91 33K R92 33K R93 33K R94 33K R95 33K R96 33K R97 33K 1K R72 1K R73 1K R74 1K R75 1K R76 1K R77 1K 33K 1K 1K R71 33K R85 1K R65 1K R70 33K R84 1K R64 33K R89 33K R83 1K R63 1K R69 33K R82 1K R62 33K R88 33K R81 1K R61 R87 33K R80 1K R60 1K R68 33K R79 1K R59 R67 R78 R58 VDD PWUPB Rev. A | Page 28 of 31 FA_A_A2 CSA_N_A3 A4 A5 MODE1 MODE0 PM PWUPA LATCHA UPDN_DAT_A_A0 UPDN_CLK_A_A1 VDD SDIO_B5 SCLK_B4 GS1_CSB_N_B3 GS0_FA_B_B2 UPDN_CLK_B_B1 UPDN_DAT_B_B0 LATCHB AGND Figure 67. ADL5205-EVALZ Evaluation Board Schematic, Page 2 TSW-120-08-G-D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P3 TSW-120-08-G-D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 P3 (P:45) (P:47) 5V 0 R100 0 AGND R33 GPIO4_SDP GPIO2_SDP GPIO0_SDP GPIO6_SDP TWI_A0 P1 DGND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FX8-120S-SV(21) (P:74) (P:76) 3.3V GPIO5_SDP GPIO3_SDP GPIO1_SDP SCL_SDP SDA_SDP GPIO7_SDP P1 DGND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 FX8-120S-SV(21) PWUPA GPIO7_SDP R28 GPIO3_SDP R27 100K R26 TBD0402 DNI DGND DGND 8 U2 VDD C22 0.1UF 3.3V (P:116) 200 AGND R57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P2 (P:79) SCL_SDP (P:56) TWI_A0 TSW-110-08-G-D A0 VCC DGND A1 SDA_SDP A2 SDA 5 (P:80) SCL WP VSS 4 24LC32A-I/MS E014160 JEDEC_TYPE=MSOP8 DGND 1 2 3 SCL_SDP 6 7 R25 100K 200 R56 GPIO5_SDP 200 200 R55 GS0_FA_B2 GPIO4_SDP R54 200 R53 200 R52 PWUPB GPIO6_SDP GS1_CSB_N_B3 SCLK_B4 GPIO1_SDP GPIO2_SDP 200 200 SDIO_B5 R23 GPIO0_SDP 200 200 R22 R13 PM CSA_N_A3 FA_A_A2 GPIO4_SDP ADL5205 Data Sheet 13488-062 ADL5205 13488-063 Data Sheet 13488-064 Figure 68. ADL5205-EVALZ Evaluation Board Side A Figure 69. ADL5205-EVALZ Evaluation Board Side B Rev. A | Page 29 of 31 ADL5205 Data Sheet BILL OF MATERIALS Table 17. Bill of Materials Qty. 1 5 Description PCB Connectors, PCB test points, red, CNLOOPTP Reference Designator Not applicable 5V, VCC, VDD, 3P3V, VREG 1 IC, high accuracy, 200 mA, low dropout linear regulator, SO8 Capacitors, ceramic, X7R 0402, 0.1 F, C0402, 10%, 16 V A1 17 2 2 1 1 1 1 1 4 1 Capacitors, ceramic, X5R 0603, 10 F, C0603, 20%, 6.3 V Capacitors, ceramic, monolithic chip, C0G, 100 pF, C0402, 5%, 50 V Capacitors, ceramic, 0805 X7R, 1 F, C0805H53, 10%, 50 V Capacitor, ceramic, X5R, 10 F, C0805H60, 10%, 10V Capacitor, ceramic, monolithic X7R, 2.2 F, C1206H71, 10%, 50 V Capacitor, ceramic, C0G 0805, 0.01 F, C0805, 5%, 50 V Inductor chip ferrite bead, 0.3 , maximum dc resistance, 0.5 A, 95 at 100 MHz, L1206-3 Connectors, PCB test point black, CNLOOPTP 21 Connectors, PCB vertical type receptacle SMD, FX8-120S-SV(21), CNHRSFX8-120S-SV Connectors, PCB BERG header ST male 20P, TSW-110-08-G-D, CNBERG2X10H330LD36 Connectors, PCB header 40P male, TSW-120-08-G-D, CNSAMTECTSW-120-08-T-D Resistors, chip SMD jumper, 0 , R0402, 5% 4 8 4 10 Resistors, chip SMD ,0402, 84.5 , R0402, 1% Resistors, high frequency chip, 0402, 50 , R0402, 1% Resistors, precision thick film chip, 34.5 , R0402, 1% Resistors, film SMD 1206, 200 , R1206, 2% 2 Resistors, precision thick film chip, R0402, 100 k, R0402, 1% Resistors, film SMD 0805, 330 k, R0805, 5% Resistors, thick film chip, 1 k, R0603, 1% Resistors, chip SMD 0603, 33 k, R0603, 0.5% Connectors, PCB BERG header ST male 3P, SAMTECTSW10608GS3PIN, CNBERG1X3H205LD36 Switches, DIP SPST, side actuated, 5435802-9, SWL880W380H310 Switch, SPST DIP, three position AU (ALCOSWITCH-7000), 5435802-2, SWSQ380H310 XFMR RF 1:1, TC1-1-13M+, AT224-1 XFMR RF 2:1, TC2-1T+, AT224-1 IC, 35 dB step size programmable DGA, ADL5205, QFN40_6X6 IC, 32 kb serial EEPROM, 24LC32A-I/MS, MSOP8 Connectors, PCB test point yellow, CNLOOPTP 1 1 1 19 19 3 2 1 2 2 1 1 2 8 Connectors, PCB coaxial SMA end launch, JOHNSON142-0701-801, CNJOHNSON142-0701-801 Manufacturer Analog Devices Components Corporation Analog Devices Part No. 08_039771B TP-104-01-02 C1 to C12, C15 to C17, C19, C22 C13, C20 C14, C18 Murata GRM155R71C104KA88D Murata Murata GRM188R60J106ME47D GRM1555C1H101JA01D C21 C23 C24 Murata KEMET Murata GRM21BR71H105KA12L C0805C106K8PACTU GRM31CR71H225KA88L C26 E1 Murata Laird Technologies, Inc. GCM2195C1H103JA16D LF1206E152R-10 GND1to GND3, VNEG TP-104-01-00 P1 Components Corporation Hirose FX8-120S-SV(21) P2 Samtec TSW-110-08-G-D P3 Samtec TSW-120-08-G-D R1, R2, R16 to R21, R24, R29, R31 to R35, R43 to R45, R49, R98, R100 R3, R4, R9, R10 R39 to R42, R101 to R104 R5, R6, R11, R12 R13, R22, R23, R28, R52 to R57 R25, R27 Panasonic ERJ-2GE0R00X Panasonic Vishay Panasonic Welwyn ERJ-2RKF84R5X FC0402E50R0FST1 ERJ-2RKF34R5X 200R WCR 1206 Panasonic ERJ-2RKF1003X R51 R58 to R65, R67 to R77 R78 to R85, R87 to R97 S1 to S3 Panasonic Vishay SUSUMU Samtec ERJ-6GEYJ334V CRCW06031K00FKEAHP RR0816P-333-D TSW-103-08-G-S SW1, SW3 TE Connectivity 5435802-9 SW2 TE Connectivity 5435802-2 T2, T4 T1, T3 U1 Mini-Circuits Mini-Circuits Analog Devices TC1-1-13M+ TC2-1T+ ADL5205 U2 VCMA, VCMB Microchip Technology Components Corporation Johnson 24LC32A-I/MS TP-104-01-04 VINA+, VINA-, VINB+, VINB-, VOUTA+, VOUTA-, VOUTB+, VOUTB- Rev. A | Page 30 of 31 ADP3303ARZ-3.3 142-0701-801 Data Sheet ADL5205 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 PIN 1 INDICATOR 0.30 0.23 0.18 40 31 30 0.50 BSC 1 PIN 1 INDICATOR 3.05 2.90 SQ 2.75 EXPOSED PAD 21 0.80 0.75 0.70 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-004333 SEATING PLANE 11 20 BOTTOM VIEW 4.50 REF 10 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-2. 08-22-2013-A TOP VIEW Figure 70. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm x 6 mm Body and 0.75 mm Package Height (CP-40-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5205ACPZ-R7 ADL5205-EVALZ 1 Temperature Range -40C to +85C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS-Compliant Part. (c)2016-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13488-0-5/19(A) Rev. A | Page 31 of 31 Package Option CP-40-16