Dual, 35 dB Range, 1 dB Step Size DGA
Data Sheet ADL5205
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2019 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Dual, independent, digitally controlled gain amplifier (DGA)
−9 dB to +26 dB gain range
1 dB step size, ±0.2 dB accuracy at 200 MHz
100 Ω differential input resistance
10 Ω differential output resistance
1.2 dB change in noise figure for first 12 dB of gain reduction
Output third-order intercept (OIP3): 48.5 dBm at 200 MHz, 5 V,
high performance mode
−3 dB bandwidth: 1700 MHz typical in high performance
mode
Multiple control interface options
Parallel 6-bit control interface with latch
Serial peripheral interface (SPI) with fast attack
Gain step up/down interface
Wide input dynamic range
Low power mode
Power-down control
Single 3.3 V or 5 V supply operation
40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS
Differential analog-to-digital converter (ADC) drivers
High intermediate frequency (IF) sampling receivers
High output power IF amplification
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
14dB
TO
26dB
GND
VPOS
VINA+
VINA–
0dB TO 23dB
10Ω
10Ω
100Ω
100Ω
SIDE
A
SPI WITH FA,
PARALLEL WITH LATCH,
UP/DOWN
SIDE B
SPI WITH FA,
PARALLEL WITH LATCH,
UP/DOWN
VOUTA–
VOUTA+
ADL5205
PM
MODE0
MODE1
VINB+
VINB–
VOUTB–
VOUTB+
0dB TO 23dB
LOGIC
LOGIC
CONTROL
CIRCUITRY
PWUPA
PWUPB
14dB
TO
26dB
13488-001
Figure 1.
GENERAL DESCRIPTION
The ADL5205 is a digitally controlled, wide bandwidth, variable
gain dual amplifier (DGA) that provides precise gain control, high
output third-order intercept (OIP3) and a near constant noise
figure for the first 12 dB of attenuation. The excellent OIP3
performance of 48.5 dBm (at 200 MHz, 5 V, high performance
mode, and maximum gain) makes the ADL5205 an excellent
gain control device for a variety of receiver applications.
For wide input dynamic range applications, the ADL5205
provides a broad 35 dB gain range with a 1 dB step size. The
gain is adjustable through multiple gain control and interface
options: parallel, SPI, or gain step up/down control.
The two channels of the ADL5205 can be powered up
independently by applying the appropriate logic level to the
PWUPA and PWUPB pins. The quiescent current of the ADL5205
is typically 175 mA for high performance mode and 135 mA for
low power mode. When disabled, the ADL5205 consumes only
14 mA and offers excellent input to output isolation. The gain
setting is preserved when the device is disabled.
Fabricated on the Analog Devices, Inc., high speed, silicon
germanium (SiGe) complementary BiCMOS process, the
ADL5205 provides precise gain adjustment capabilities with good
distortion performance. The ADL5205 amplifier comes in a
compact, thermally enhanced, 6 mm × 6 mm, 40-lead LFCSP
package and operates over the temperature range of −40°C to
+85°C.
Note that throughout this data sheet, multifunction pins, such
as CSA/A3, are referred to by the entire pin name or by a single
function of the pin, for example, CSA, when only that function
is relevant.
ADL5205 Data Sheet
Rev. A | Page 2 of 31
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Junction to Board Thermal Impedance ..................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 17
Basic Structure ............................................................................ 17
Control/Logic Circuitry ............................................................. 17
Common-Mode Voltage ............................................................ 17
Applications Information .............................................................. 18
Basic Connections ...................................................................... 18
Digital Interface Overview ........................................................ 19
SPI Read ....................................................................................... 20
ADC Interfacing ......................................................................... 21
Noise Figure vs. Gain Setting .................................................... 21
Evaluation Board ............................................................................ 22
Overview ..................................................................................... 22
Power Supply Interface .............................................................. 22
Signal Inputs and Outputs......................................................... 23
Manual Controls ......................................................................... 23
Parallel Interface ......................................................................... 24
Serial Interface ............................................................................ 24
Standard Development Platform (SDP) Interface ................. 25
Evaluation Board Control Software ......................................... 25
Command Line Control Program............................................ 25
Graphical User Interface (GUI) Program ............................... 25
Evaluation Board Schematics and Layout ................................... 27
Bill of Materials ........................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
5/2019—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 4
Changes to Table 3 ............................................................................ 6
4/2016—Revision 0: Initial Version
Data Sheet ADL5205
Rev. A | Page 3 of 31
SPECIFICATIONS
Supply voltage (VPOS) = 3.3 V or 5 V, TA = 25°C, ZLOAD = 200 Ω, maximum gain (Gain code = 000000), frequency = 200 MHz, PM = 0 V,
2 V p-p differential output, unless otherwise noted.
Table 1.
3.3 V Supply 5 V Supply
Parameter1 Test Conditions/Comments Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth High performance mode 1700 1700 MHz
Low power mode 1500 1500 MHz
Slew Rate 5 5 V/ns
INPUT STAGE VINx+ and VINx− pins
Maximum Input Swing2 Gain code = 111111 8 8 V p-p
Differential Input Resistance Differential 100 100 Ω
Input Common-Mode Voltage 1.65 2.5 V
Common-Mode Rejection Ratio (CMRR) Gain code = 000000 48 48 dB
GAIN
Voltage Gain Range 35 35 dB
Maximum Gain Gain code = 000000 26 26 dB
Minimum Gain Gain code = 100011 to 111111 −9 −9 dB
Gain Step Size 1 1 dB
Gain Step Accuracy ±0.2 ±0.2 dB
Gain Flatness From 30 MHz to 200 MHz 0.2 0.2 dB p-p
Gain Temperature Sensitivity Gain code = 000000 2.4 4 mdB/°C
Fast Attack Step Response Delay For VIN = 0.1 V, FA_A or FA_B
changing from 0 to 1 with 16 dB step
15 80 ns
COMMON-MODE INPUTS
VCMA and VCMB Input Resistance 2.6 2.6 kΩ
OUTPUT STAGE VOUTx+ and VOUTx− pins
Output Voltage Swing At P1dB, gain code = 000000 4.5 5.4 V p-p
Common-Mode Voltage Reference VCMA, VCMB 1.2 1.65 1.8 1.4 2.5 2.7 V
Output Common-Mode Offset ((VOUTx+) + (VOUTx−))/2 − VCMx/2 −10 +10 −10 +10 mV
Differential Output Resistance Differential 10 10 Ω
Short-Circuit Current High performance mode 22 22 mA
Low power mode 17 17 mA
NOISE/HARMONIC PERFORMANCE Gain code = 000000, high
performance mode
10 MHz
Noise Figure 6.3 6.5 dB
Second Harmonic VOUT = 2 V p-p −103 −103 dBc
Third Harmonic VOUT = 2 V p-p −101 −100 dBc
Output Third-Order Intercept (OIP3) VOUT = 2 V p-p composite 48.5 47 dBm
Output 1 dB Compression Point
(P1dB)
13.7 17.5 dBm
100 MHz
Noise Figure 6.3 6.6 dB
Second Harmonic VOUT = 2 V p-p −86 −90 dBc
Third Harmonic VOUT = 2 V p-p −87 −94 dBc
OIP3 VOUT = 2 V p-p composite 45 46 dBm
Output P1dB 13.2 17.4 dBm
ADL5205 Data Sheet
Rev. A | Page 4 of 31
3.3 V Supply 5 V Supply
Parameter1 Test Conditions/Comments Min Typ Max Min Typ Max Unit
200 MHz
Noise Figure Increase for First 12 dB of
Gain Reduction
Gain code = 000000 to 001100 1.2 1.2 dB
Noise Figure 6.6 6.6 dB
Second Harmonic VOUT = 2 V p-p −75.5 −75 dBc
Third Harmonic VOUT = 2 V p-p −77 −87.5 dBc
OIP3 VOUT = 2 V p-p composite 44 48.5 dBm
Output P1dB 13 17 dBm
300 MHz
Noise Figure 6.6 6.9 dB
Second Harmonic VOUT = 2 V p-p −63 −64 dBc
Third Harmonic VOUT = 2 V p-p −68 −78 dBc
OIP3 VOUT = 2 V p-p composite 43 43.5 dBm
Output P1dB 12.8 17.3 dBm
500 MHz
Noise Figure 7.8 8.2 dB
Second Harmonic VOUT = 2 V p-p −58 −61.5 dBc
Third Harmonic VOUT = 2 V p-p −57.5 −67.5 dBc
OIP3 VOUT = 2 V p-p composite 37 36 dBm
Output P1dB 13.1 17.7 dBm
DIGITAL INTERFACE
Input Pins A0 to A5, B0 to B5, MODE1,
MODE0, PWUPA, PWUPB, PM,
LATCHA, LATCHB, SDIO
VIH Logic high 2 VPOS 2 3.3 V
VIL Logic low 0 1.0 0 1.0 V
Input Leakage Current Digital input voltage = 0 V to 3.3 V ±3 ±3 μA
Output Pins SDIO
Logic High (VOH) IOH = −2 mA 2.4 2.4 V
Logic Low (VOL) IOL =2 mA 0.5 0.5 V
POWER-INTERFACE
Supply Voltage (VPOS) VPOS 3.15 3.3 3.45 4.75 5 5.25 V
Quiescent Current
High Performance Mode PM = low 175 175 mA
Low Power Mode PM = high 135 135 mA
Power-Down Current PWUPA and PWUPB = low 14 14 mA
1 When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
2 The maximum input swing of 8 V p-p is for the lowest gain setting of −9 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly
to maintain the same maximum output swing.
Data Sheet ADL5205
Rev. A | Page 5 of 31
TIMING SPECIFICATIONS
Table 2. SPI Timing Parameters
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CSA or CSB to SCLK Setup Time tCS 20 ns
SDIO to SCLK Setup Time tDS 10 ns
SCLK to SDIO Hold Time tDH 10 ns
SCLK Pulse Width tPW 25 ns
SCLK Cycle Time tSCLK 50 ns
SCLK to CSA or CSB Setup Time tCH 10 ns
SCLK to SDIO Output Valid Delay tDV 20 ns During readback
Timing Diagrams
SCLK
___ ___
CSA, CSB
SDIO
tSCLK
tCS
tDS tDH
tPW
tCH
DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0
tDV
13488-002
Figure 2. SPI Interface Read/Write Mode Timing Diagram
UPDN_DAT_x
UPDN_CLK_x
UP
t
PW
t
DS
t
DH
t
DH
t
DS
t
DS
DOWN RESET
13488-003
Figure 3. Up/Down Gain Control Timing Diagram
LATCHA,
LATCHB
A5 TO A0
B5 TO B0
t
DH
13488-004
Figure 4. Parallel Mode Timing Diagram
ADL5205 Data Sheet
Rev. A | Page 6 of 31
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Differential Output Voltage Swing ×
Bandwidth Product
3 V-GHz
Supply Voltage, VPOS 5.4 V
PWUPA, PWUPB, A0 to A5, B0 to B5, MODE0,
MODE1, PM, LATCH A, LATCH B
−0.5 V to +3.6 V
Input Voltage (VINx+ ,VINx−) −0.5 V to +3.1 V
Differential Input Voltage ((VINx+) − (VINx−))1 ±1 V
Internal Power Dissipation 1000 mW
Maximum Junction Temperature 135°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1 The differential input voltage limit is significantly lower than the maximum
input swing of 8 V p-p. The maximum input swing is for the lowest gain
setting of −9 dB. As the gain setting is increased, the maximum input swing
must be reduced correspondingly to maintain the same maximum output
swing. The differential input voltage limit takes effect at greater than ~14 dB,
at which point there is no more resistive attenuation on the input and the
signal presented on the pins goes directly on an input ESD protection circuit.
Therefore, the input signal swing must be limited to a low value.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 4 shows the thermal resistance from the die to ambient
(θJA), die to board (θJB), and die to lead (θJC), respectively.
Table 4. Thermal Resistance
Package Type θJA θ
JB θ
JC Unit
40-Lead LFCSP 47.7 24.4 15.4 °C/W
JUNCTION TO BOARD THERMAL IMPEDANCE
The junction to board thermal impedance (θJB) is the thermal
impedance from the die to the leads of the ADL5205. The value
given in Table 4 is based on the standard printed circuit board
(PCB) described in the JESD51-7 standard for thermal testing
of surface-mount components. PCB size and complexity (number
of layers) affect θJB; more layers tend to reduce thermal impedance
slightly.
If the PCB temperature is known, use the junction to board
thermal impedance to calculate the die temperature (also
known as the junction temperature) to ensure that the die
temperature does not exceed the specified limit of 135°C. For
example, if the PCB temperature is 85°C, the die temperature is
given by
TJ = TB + (PDISS × θJB)
The worst case power dissipation for the ADL5205 is 919 mW
(5.25 V × 175 mA, see Table 1). Therefore, TJ is
TJ = 85°C + (0.919 W × 24.4°C/W) = 107.4°C
ESD CAUTION
Data Sheet ADL5205
Rev. A | Page 7 of 31
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT
TO THESE PINS.
2. THE EXPOSED PAD MUST BE CONNECTED TO
A LOW IMPEDANCE GROUND PLANE. THIS IS
THE GROUND (0V) REFERENCE FOR ALL THE
VOLTAGES IN TABLE 1.
PWUPA
VCMA
LATCHA
UPDN_DAT_A/A
0
UPDN_CLK_A/A1
FA_A/A2
PIN 1
INDICATOR
A4
A5
MODE1
MODE0
PM
DNC
SDIO/B5
SCLK/B4
CSA/A3
GS1/CSB/B3
DNC
VPOS
DNC
DNC
VPOS
DNC
VOUTB–
VOUTB+
VOUTA+
VOUTA–
VINA+
VINA–
ADL5205
TOP VIEW
(Not to Scale)
GS0/FA_B/B2
UPDN_CLK_B/B1
UPDN_DAT_B/B0
PWUPB
VCMB
LATCHB
VINB–
VINB+
DNC
DNC
DNC
DNC
13488-005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 CSA/A3 Channel A Select in Serial Mode (CSA). When serial mode is enabled, a logic low selects Channel A.
Bit 3 for Channel A in Parallel Gain Control Interface Mode (A3).
2 A4 Bit 4 for Channel A in Parallel Gain Control Interface Mode (A4).
3 A5 Bit 5 for Channel A in Parallel Gain Control Interface Mode (A5).
4 MODE1
MSB for Mode Control. Use both the MODE0 and MODE1 pins to select parallel, SPI, or up/down
interface mode.
5 MODE0
LSB for Mode Control. Use both the MODE1 and MODE0 pins to select parallel, SPI, or up/down
interface mode.
6 PM
Power Mode. Set this pin to logic low to enable high performance mode, or logic high to enable
low power mode.
7, 19, 20, 23, 25, 26,
28, 31, 32
DNC Do Not Connect. Do not connect to these pins.
8 SDIO/B5 Serial Data Input and Output in SPI Mode (SDIO).
Bit 5 for Channel B in Parallel Gain Control Interface Mode (B5).
9 SCLK/B4 Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Channel B in Parallel Gain Control Interface (B4).
10 GS1/CSB/B3 MSB for the Gain Step Size Control in Up/Down Mode (GS1).
Channel B Select in Serial Mode (CSB). When serial mode is enabled, a logic low selects Channel B.
Bit 3 for Channel B in Parallel Gain Control Mode (B3).
11 GS0/FA_B/B2 LSB for the Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack for Channel B (FA_B). In serial mode, a logic high on this pin attenuates Channel B
according to the FA bit values in the control register.
Bit 2 for Channel B in Parallel Gain Control Interface (B2).
12 UPDN_CLK_B/B1 Clock Interface for the Channel B Up/Down Function (UPDN_CLK_B).
Bit 1 for Channel B in Parallel Gain Control Interface Mode (B1).
13 UPDN_DAT_B/B0 Data Pin for the Channel B Up/Down Function (UPDN_DAT_B).
Bit 0 for Channel B in Parallel Gain Control Interface Mode (B0).
ADL5205 Data Sheet
Rev. A | Page 8 of 31
Pin No. Mnemonic Description
14 LATCHB
Latch B. A logic low on this pin allows the gain to change on Channel B in parallel gain control
interface mode. A logic high on this pin prevents gain changes.
15 VINB− Channel B Negative Analog Input.
16 VINB+ Channel B Positive Analog Input.
17 PWUPB
Channel B Power-Up. A logic high on this pin powers up Channel B, and a logic low on this pin
disables it.
18 VCMB Channel B Common-Mode Output.
21 VOUTB− Channel B Negative Analog Output.
22 VOUTB+ Channel B Positive Analog Output.
24, 27 VPOS Positive Power Supply.
29 VOUTA+ Channel A Negative Analog Output.
30 VOUTA− Channel A Positive Output.
33 VCMA Channel A Common-Mode Output.
34 PWUPA
Channel A Power-Up. A logic high on this pin powers up Channel A, and a logic low on this pin
disables it.
35 VINA+ Channel A Positive Analog Input.
36 VINA− Channel A Negative Analog Input.
37 LATCHA
Latch A. A logic low on this pin allows the gain to change on Channel A in the parallel gain
control interface mode. A logic high on this pin prevents gain changes.
38 UPDN_DAT_A/A0 Data Pin for the Channel A Up/Down Function (UPDN_DAT_A).
Bit 0 for Channel A in Parallel Gain Control Interface Mode (A0).
39 UPDN_CLK_A/A1 Clock Interface for the Channel A Up/Down Function (UPD_CLK_A).
Bit 1 for Channel A in Parallel Gain Control Interface Mode (A1).
40 FA_A/A2
Fast Attack for Channel A (FA_A). In serial mode, a logic high on this pin attenuates Channel A
according to an FA SPI word.
Bit 2 for Channel A in Parallel Gain Control Interface (A2).
EP GND
Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane.
This is the ground (0 V) reference for all the voltages in Table 1.
Data Sheet ADL5205
Rev. A | Page 9 of 31
TYPICAL PERFORMANCE CHARACTERISTICS
Supply voltage (VPOS) = 3.3 V or 5 V, TA = 25°C, ZLOAD = 200 Ω, maximum gain (gain code = 000000), 2 V p-p composite differential
output for intermodulation distortion (IMD) and OIP3, 2 V p-p differential output for second harmonic distortion (HD2) and third
harmonic distortion (HD3), VCMA = VCMB = VPOS/2, unless otherwise noted.
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
–40 25 85
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
3.45V
3.3V
3.15V
5.25V
5.0V
4.75V
13488-006
Figure 6. Supply Current vs. Temperature, PM = 0
–40 25 85
TEMPERATURE (°C)
125
127
129
131
133
135
137
139
141
143
145
SUPPLY CURRENT (mA)
3.45V
3.3V
3.15V
5.25V
5.0V
4.75V
13488-007
Figure 7. Supply Current vs. Temperature, PM = 1
–15
–10
–5
0
5
10
15
20
25
30
0 5 10 15 20 25 30 35 40
GAIN (dB)
GAIN CODE
+25°C
–40°C
+85°C
13488-008
Figure 8. Gain vs. Gain Code over Temperature at 200 MHz
60
0
10
20
30
40
50
0 100 200 300 400 500
OIP3 (dBm)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26dB
3.3V, 14dB
3.3V, 6dB
13488-009
Figure 9. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS at Three
Gain Codes, High Performance Mode
60
0
10
20
30
40
50
0 100 200 300 400 500
OIP3 (dBm)
FREQUENCY (MHz)
5V, +85°C
5V, +25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40°C
13488-010
Figure 10. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS for Three
Temperatures at Maximum Gain, High Performance Mode
60
0
10
20
30
40
50
0 100 200 300 400 500
OIP3 (dBm)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26dB
3.3V, 14dB
3.3V, 6dB
13488-011
Figure 11. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS at Three
Gain Codes, Low Power Mode
ADL5205 Data Sheet
Rev. A | Page 10 of 31
60
0
10
20
30
40
50
0 100 200 300 400 500
OIP3 (dBm)
FREQUENCY (MHz)
5V, +85°C
5V, +25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40°C
13488-012
Figure 12. Output Third-Order Intercept (OIP3) vs. Frequency over VPOS for Three
Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode
60
0
10
20
30
40
50
0 100 200 300 400 500
OIP3 (dBm)
FREQUENCY (MHz)
5.25V
5V
4.75V
3.45V
3.3V
3.15V
13488-013
Figure 13. Output Third-Order Intercept (OIP3) vs. Frequency and VPOS Variance
(±5%), Maximum Gain, High Performance Mode
13488-014
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–
20
0 100 200 300 400 500
IMD3 (dBc)
FREQUENCY (MHz)
5V 26dB
5V 14dB
5V 6dB
3.3V 26dB
3.3V 14dB
3.3V 6dB
Figure 14. Two-Tone Output IMD3 vs. Frequency over VPOS for Three Gain
Codes at 2 V p-p Composite, Low Power Mode
–20
–140
–120
–100
–80
–60
–40
0 100 200 300 400 500
IMD3 (dBc)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26dB
3.3V, 14dB
3.3V, 6dB
13488-015
Figure 15. Two-Tone Output IMD3 vs. Frequency over VPOS for Three Gain
Codes at 2 V p-p, High Performance Mode
0
–120
–100
–80
–60
–40
–20
0 100 200 300 400 500
HD2 (dBc)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26dB
3.3V, 14dB
3.3V, 6dB
13488-016
Figure 16. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three
Gain Codes, High Performance Mode
0
–120
–100
–80
–60
–40
–20
0 100 200 300 400 500
HD2 (dBc)
FREQUENCY (MHz)
5V, +85°C
5V, +25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40°C
13488-017
Figure 17. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three
Temperatures at Maximum Gain, 2 V p-p, High Performance Mode
Data Sheet ADL5205
Rev. A | Page 11 of 31
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD2 (d Bc)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26d B
3.3V, 14d B
3.3V, 6d B
13488-018
Figure 18. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three
Gain Codes at 2 V p-p Composite, Low Power Mode
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD2 (d Bc)
FREQUENCY (MHz)
5V, + 85°C
5V, + 25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40° C
13488-019
Figure 19. Second Harmonic Distortion (HD2) vs. Frequency over VPOS for Three
Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD3 (d Bc)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26d B
3.3V, 14d B
3.3V, 6d B
13488-020
Figure 20. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three Gain
Codes at 2 V p-p Composite, High Performance Mode
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD3 (d Bc)
FREQUENCY (MHz)
5V, + 85°C
5V, + 25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40° C
13488-021
Figure 21. Third Harmonic Distortion (HD3) vs. Frequency vs. VPOS for Three
Temperatures at Maximum Gain, 2 V p-p Composite, High Performance Mode
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD3 (d Bc)
FREQUENCY (MHz)
5V, 26dB
5V, 14dB
5V, 6dB
3.3V, 26d B
3.3V, 14d B
3.3V, 6d B
13488-022
Figure 22. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three Gain
Codes at 2 V p-p Composite, Low Power Mode
0
–120
–100
–80
–60
–40
–20
0100 200 300 400 500
HD3 (d Bc)
FREQUENCY (MHz)
5V, + 85°C
5V, + 25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40° C
13488-023
Figure 23. Third Harmonic Distortion (HD3) vs. Frequency over VPOS for Three
Temperatures at Maximum Gain, 2 V p-p Composite, Low Power Mode
ADL5205 Data Sheet
Rev. A | Page 12 of 31
40
0
10
20
5
15
25
30
35
NOISE FIGURE (dB)
13488-024
0100 200 300 400 500
FREQUENCY (MHz)
GAI N = 26dB TO 14dB
13dB TO –9dB
Figure 24. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 5 V,
High Performance Mode
40
0
10
20
5
15
25
30
35
0100 200 300 400 500
NOISE FIGURE (dB)
FREQUENCY (MHz)
13488-025
GAI N = 26dB TO 14d B
13dB TO –9dB
Figure 25. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 3.3 V,
High Performance Mode
40
0
10
20
5
15
25
30
35
NOISE FIGURE (dB)
13488-026
0100 200 300 400 500
FREQUENCY (MHz)
GAI N = 26dB TO 14dB
13dB TO –9dB
Figure 26. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 5 V,
Low Power Mode
Figure 27. Noise Figure vs. Frequency for 35 dB Gain Range at VPOS = 3.3 V,
Low Power Mode
20
10
12
14
16
18
11
13
15
17
19
0100 200 300 400 500
OP1dB (dBm)
FREQUENCY (MHz)
5V, + 85°C
5V, + 25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40° C
13488-028
Figure 28. Output 1 dB Compression Point (OP1dB) vs. Frequency at Maximum
Gain, High Performance Mode
20
10
12
14
16
18
11
13
15
17
19
0100 200 300 400 500
OP1dB (dBm)
FREQUENCY (MHz)
13488-029
5V, + 85°C
5V, + 25°C
5V, –40°C
3.3V, +85°C
3.3V, +25°C
3.3V, –40° C
Figure 29. Output 1 dB Compression Point (OP1dB) vs. Frequency at Maximum
Gain, Low Power Mode
Data Sheet ADL5205
Rev. A | Page 13 of 31
–100
–80
–60
–40
–20
S-PARAM E TERS ( dB)
0
20
40
50 500
FREQUENCY (MHz)
5000
SDD11
SDD12
SDD21
SDD22
13488-030
Figure 30. Differential S-Parameters (SDD21, SDD12, SDD11, SDD22) vs.
Frequency
13488-032
10M 100M 1G
MAXIMUM VOLTAG E GAIN ( dB)
FREQUENCY (Hz)
–40°C
+25°C
+85°C
Figure 31. Maximum Voltage Gain vs. Frequency over Temperature at
VPOS = 3.3 V
–30
–20
–10
0
10
20
30
10M 100M 1G
VOLTAGE GAIN ( dB)
FREQUENCY (Hz)
13488-132
Figure 32. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 3.3 V, Low
Power Mode
–30
–20
–10
0
10
20
30
10M 100M 1G
VOLTAGE GAIN ( dB)
FREQUENCY (Hz)
13488-133
Figure 33. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 5 V,
High Performance Mode
–30
–20
–10
0
10
20
30
10M 100M 1G
VOLTAGE GAIN ( dB)
FREQUENCY (Hz)
13488-134
Figure 34. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 3.3 V,
High Performance Mode
–30
–20
–10
0
10
20
30
10M 100M 1G
VOLTAGE GAIN ( dB)
FREQUENCY (Hz)
13488-135
Figure 35. Voltage Gain vs. Frequency for Various Gain Steps at VPOS = 5 V,
Low Power Mode
ADL5205 Data Sheet
Rev. A | Page 14 of 31
0
–50
–30
–20
–10
–40
–35
–45
–25
–15
–5
250
–250
–50
50
150
–150
–100
–200
0
100
200
10 100 1k
SDD11 MAGNITUDE (dB)
SDD11 PHASE (Degrees)
FREQUENCY (MHz)
+26dB GAIN MAGNITUDE
–9dB GAIN MAGNITUDE
+26dB GAIN PHASE
–9dB GAIN PHASE
13488-034
Figure 36. Differential Input Reflection (SDD11) Magnitude and Phase vs.
Frequency
–250
–200
–150
–100
–50
0
50
100
150
200
250
–3.0
–2.5
–4.0
–3.5
–5.0
–4.5
–2.0
–1.5
–1.0
–0.5
0
1000
SDD22 PHASE (Degrees)
SDD22 MAGNITUDE (dB)
FREQUENCY (MHz)
+26dB GAIN MAGNITUDE
–9dB GAIN MAGNITUDE
+26dB PHASE
–9dB PHASE
13488-138
Figure 37. Differential Output Reflection (SDD22) Magnitude and Phase vs.
Frequency
12
0
8
4
6
2
10
1.2
–1.2
–0.4
–0.8
0
0.4
0.8
PHASEVARIATION(Degrees)
CUMULATIVE GAIN STEP ERROR (dB)
PROGRAMMED GAIN (dB)
13488-036
–9 –6 –3 0 3 6 9 12 15 18 21 24 26
Figure 38. Phase Variation and Cumulative Gain Step Error vs. Programmed
Gain, Frequency = 200 MHz, VPOS = 3.3 V, 2 V p-p Composite
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
20.0ns/div
12.5GS/s 80.0ps/pt
A CH2 1.57V
3
2
T
13488-037
Figure 39. Enable Time Domain Response at VPOS = 5 V
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
20.0ns/div
12.5GS/s 80.0ps/pt
A CH2 1.56V
3
2
T
13488-038
Figure 40. Enable Time Domain Response at VPOS = 3.3 V
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
20.0ns/div
6.25GS/s 160ps/pt
A CH2 1.57V
3
2
T
13488-039
Figure 41. Disable Time Domain Response at VPOS = 5 V
Data Sheet ADL5205
Rev. A | Page 15 of 31
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
20.0ns/div
6.25GS/s 160ps/pt
A CH2 1.57V
3
2
T
13488-040
Figure 42. Enable Time Domain Response at VPOS = 3.3 V
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
40.0ns/div
25.0GS/s 40.0ps/pt
A CH2 1.53V
3
2
T
13488-041
Figure 43. Fast Attack Step Time Domain Response at VPOS = 5 V
CH2 500mV/div 50Ω
BW
:8.0G
CH3 300mV/div 50Ω
BW
:5.0G
20.0ns/div
25.0GS/s 40.0ps/pt
A CH2 1.53V
3
2
T
13488-042
Figure 44. Fast Attack Step Time Domain Response at VPOS = 3.3 V
70
0
10
30
50
20
40
60
10 100 1k
CMRR (dB)
FREQUENCY (MHz)
CMRR 5V
CMRR 3.3V
13488-043
Figure 45. CMRR vs. Frequency at Maximum Gain
250
200
1.01.21.41.61.82.02.22.42.62.8
150
SETTLING TIME (ns)
VCMA OR VCMB (V)
100
50
0
3.3V 5V
13488-147
SETTLING TO WITHIN 1 dB,
FOR GAIN STEP FROM −9dB TO 26dB
Figure 46. Maximum Gain Transition Settling Time vs. Output Common-
Mode Voltage (VCMA or VCMB)
800
850
900
950
1000
10 100 1000
GROUP DE
L
A
Y (ps)
FREQUENCY (MHz)
3.3V, PM = 0
3.3V, PM = 1
5V, PM = 0
5V, PM = 1
13488-148
Figure 47. Group Delay at Maximum Gain vs. Frequency over VPOS and Power
Modes
ADL5205 Data Sheet
Rev. A | Page 16 of 31
REVERSE ISOLATION (dB)
FREQUENCY (Hz)
3.3V DISABLED STATE
5V DIS ABLED S TATE
3.3V E NABLED
5V ENABL E D
13488-149
Figure 48. Reverse Isolation vs. Frequency
–120
–100
–80
–60
–40
–20
0
10 100 1000
CHANNEL ISOLATION (dB)
FREQUENCY (MHz)
CH A TO CH B
CH B TO CH A
13488-150
Figure 49. Channel Isolation vs. Frequency for Channel A and Channel B
Data Sheet ADL5205
Rev. A | Page 17 of 31
THEORY OF OPERATION
BASIC STRUCTURE
The ADL5205 is a dual differential, digitally controlled variable
gain amplifier (DGA). Each DGA consists of a 100 Ω differential
input, digitally controlled passive attenuator followed by a
digitally controlled gain amplifier. The input, digitally controlled,
binary weighted attenuator has a range of 0 dB to 23 dB with 1 dB
steps, and the amplifier has a range of 14 dB to 26 dB, also with
1 dB steps. On-chip logic circuitry maps the gain codes such
that the first 12 dB of gain reduction from the maximum gain
are accomplished using the digitally controlled gain amplifier,
only. This topology allows the first 12 dB of gain reduction to be
accompanied by typically 1.2 dB of total noise figure degradation
(at 200 MHz). The OIP3 also remains nearly constant over the
first 12 dB of gain range. The noise figure for the DGA
increases by 1 dB for each decibel of attenuation within the
remaining 23 dB attenuation range. The differential output
impedance of the amplifier is 10 Ω.
CONTROL/LOGIC CIRCUITRY
The ADL5205 features three different gain control interfaces: serial,
parallel, or up/down control, determined by the combination of
the MODE1 and MODE0 pins. For details on controlling the
gain in each of these modes, see the Digital Interface Overview
section. In general, the gain step size is 1 dB; however, larger
step sizes can be programmed as described in the Digital
Interface Overview section. Each amplifier has a maximum gain
of +26 dB (Gain Code 000000) to −9 dB (Gain Code 100011 to
Gain Code 111111). Using the performance mode (PM) pin, users
can lower the power consumption of the device with a slight
degradation in linearity performance.
COMMON-MODE VOLTAGE
The ADL5205 is flexible in terms of input/output coupling. It
can be ac-coupled or dc-coupled at the inputs and/or outputs
within the specified output common-mode levels of 1.2 V to
2.7 V, depending on the supply voltage. If no external output
common-mode voltage is applied, the input and output common-
mode voltages are set internally to half of the supply voltage.
The output common-mode voltages of the ADL5205 are controlled
by the voltages on the VCMA and VCMB pins. Each of these pins
is connected internally through 5 kΩ resistors to the VPOS pin
as well as to the exposed pad (EP). As a result, the common-
mode output voltage at each channel is preset internally to half
of the supply voltage at VPOS. Alternatively, the VCMA and
VCMB pins can be connected to the common-mode voltage
reference output from an ADC, and thus the common-mode
levels between the two devices can be matched without
requiring any external components.
10Ω
100Ω14dB
TO
26dB
GND
VPOS
VINA+
VINA–
SIDE A
SPI WITH FA,
PARAL LEL WI TH LATCH,
UP/DOWN
VOUTA–
ADL5205
VOUTA+
PM
MODE0
MODE1
LOGIC
CONTROL
CIRCUITRY
PWUPA
CHANNEL A
CIRCUITRY DUPL ICATE D FOR CHANNEL B
0dB TO 23dB
13488-054
Figure 50. Basic Structure
ADL5205 Data Sheet
Rev. A | Page 18 of 31
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 51 shows the basic connections for operating the ADL5205.
Apply a voltage of 3.3 V or 5 V to the VPOS pins. Decouple
each supply pin with at least one low inductance, surface-mount
ceramic capacitor of 0.1 μF placed as close to the device as possible.
The differential outputs have a dc common-mode voltage that is
approximately half of the supply; therefore, decouple these outputs
using 0.1 μF capacitors to the balanced load. The balanced
differential inputs have the same dc common-mode voltage as
the outputs; the inputs are decoupled using 0.1 μF capacitors as
well. The digital pins, mode control pins, associated SPI pins,
and parallel gain control pins, (PM, PWUPA, and PWUPB)
operatefrom a 3.3 V voltage.
To enable each channel of the ADL5205, pull the PWUPA pin or
the PWUPB pin high (2.0 V ≤ PWUPA/PWUPB ≤ 3.3 V). A logic
low on the PWUPA pin or the PWUPB pin sets the channel to
sleep mode, reducing the current consumption to approximately
7 mA per channel. The VCMA and the VCMB pins are the
reference inputs for the output common-mode voltage of each
channel, and they must be decoupled with 0.1 μF capacitors.
3.3V
3.3V
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
3.3V
3.3V
3.3V
EXPOSED
PAD
BALANCED
LOAD
V
POS
ADL5205
BALANCED
SOURCE
AC
0.1µF
0.1µF
0.1µF
0.1µF
10µF
0.1µF
BALANCED
SOURCE
AC
0.1µF 0.1µF
0.1µF
CHANNEL B
PARALLEL INTERFACE
CHANNEL B
PARALLEL INTERFACE
0.1µF
0.1µF
BALANCED
LOAD
0.1µF
0.1µF
13488-053
PWUPA
VCMA
LATCHA
UPDN_DAT_A/A0
UPDN_CLK_A/A1
FA_A/A2
A4
A5
MODE1
MODE0
PM
DNC
SDIO/B5
SCLK/B4
CSA/A3
GS1/CSB/B3
DNC
VPOS
DNC
DNC
VPOS
DNC
VOUTB–
VOUTB+
VOUTA+
VOUTA–
VINA+
VINA–
GS0/FA_B/B2
UPDN_CLK_B/B1
UPDN_DAT_B/B0
PWUPB
VCMB
LATCHB
VINB–
VINB+
DNC
DNC
DNC
DNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2. THE EXPOSED PAD MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PLANE.
THIS IS THE GROUND (0V) REFERENCE FOR ALL THE VOLTAGES IN TABLE 1.
Figure 51. Basic Connections
Data Sheet ADL5205
Rev. A | Page 19 of 31
DIGITAL INTERFACE OVERVIEW
The three digital control interface options of the ADL5205
DGA are, respectively,
• Parallel control interface
• Serial peripheral interface
• Gain step up/down interface
The digital control interface selection is made via two digital
pins, MODE1 and MODE0, as shown in Tabl e 6. Additionally,
there are three power mode control pins, PM, PWUPA, and
PWUPB. PM selects between the high performance and low
power modes, whereas PWUPA and PWUPB enable (power-
up) the corresponding channel. The gain in each channel is
controlled by a 6-bit binary code (A5 to A0 and B5 to B0).
The same physical pins are shared between three interfaces,
resulting in as many as three different functions per digital pin (see
Table 5).
Table 6. Digital Control Interface Selection Truth Table
MODE1
MODE0
Interface
0 0 Parallel
0 1 Serial (SPI)
1 0 Up/down
1 1 Up/down
Parallel Digital Interface
The parallel digital interface uses six gain control bits and a
latch pin per amplifier. The latch pin controls whether the input
data latch is transparent (logic low) or latched (logic high). In
transparent mode, the gain changes as the input gain control bits
change. In latched mode, the gain is determined by the latched
gain setting and is not changed by changing the input gain
control bits.
Serial Peripheral Interface (SPI)
The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The
SPI data register consists of two bytes: six gain control bits (D0
to D5), two attenuation step size address bits (FA0 and FA1),
one read/write bit (R/W), and seven don't care bits (X), as
shown in Figure 53.
The SPI uses a bidirectional pin (SDIO) for writing to the SPI
register and for reading from the SPI register. To write to the SPI
register, pull the CSA or the CSB pin low and apply 16 clock pulses
to shift the 16 bits into the corresponding SPI register, MSB first.
Individual channel SPI registers can be selected by pulling CSA
or CSB low. By simultaneously pulling the CSA and CSB pins
low, the same data can be written to both SPI registers.
SPI register read back operation is described in the SPI Read
section. Because there is only one SDIO line, the control register
of each channel must be read back individually.
SPI fast attack mode is controlled by the FA_A or FA_B pins. A
logic high on the FA_A pin or FA_B pin results in an attenuation
selected by the FA1 and the FA0 bits in the SPI register.
Table 7. SPI 2-Bit Attenuation Step Size Truth Table
FA1 FA0 Step Size (dB)
0 0 2
0 1 4
1
0
8
1 1 16
Up/Down Interface
The up/down interface uses two digital pins to control the gain.
When the UPDN_DAT_x pin is low, the gain for the
corresponding channel is increased by a clock pulse on the
UPDN_CLK_x pin (rising and falling edges). When the
UPDN_DAT_x pin is high, the corresponding gain is decreased
by a clock pulse on the UPDN_CLK_x pin. Reset is detected
when the rising edge of UPDN_CLK_x latches one polarity on
UPDN_DAT_x, and the falling edge latches the opposite
polarity. Reset results in the minimum gain code of 111111.
UPDN_DAT_x
UP DN RESET
UPDN_CLK_x
13488-055
Figure 52. Up/Down Gain Control Timing
The step size is selectable by the GS1 and GS0 pins. The default
step size is 1 dB. The gain code count rails at the top and
bottom of the control range.
Table 8. Step Size Control Truth Table
GS1 GS0 Step Size (dB)
0 0 1
0 1 2
1 0 4
1 1 8
D0 D1 D2 D3 D4 D5 FA0 FA1 R/W XXXXXXX
DON’ T CARE ( 7 BITS )
READ/WRITE
FAST ATTACK ATTENUATION STEP SIZEADDRESS
GAI N CONT RO L
LSB
DATAMSB LSB MSB
13488-056
Figure 53. 16-Bit SPI Register
ADL5205 Data Sheet
Rev. A | Page 20 of 31
Table 9. Gain Code vs. Voltage Gain
6-Bit Binary Gain Code, D5 to D0 Voltage Gain (dB)
000000 +26
000001 +25
000010 +24
000011 +23
000100 +22
000101 +21
000110 +20
000111 +19
001000 +18
001001 +17
001010 +16
001011 +15
001100 +14
001101 +13
001110 +12
001111 +11
010000 +10
010001 +9
010010 +8
010011 +7
010100 +6
010101 +5
010110 +4
010111 +3
011000 +2
011001 +1
011010 0
011011 −1
011100 −2
011101 −3
011110 −4
011111 −5
100000 −6
100001 −7
100010 −8
100011 to 111111 −9
SPI READ
The ADL5205 can be read back only in the serial mode, during
a read cycle (from CSA/CSB low to CSA/CSB high) after the
R/W bit is set high in the previous cycle. During the read cycle,
data changes at each rising edge of SCLK, and can be latched
using the falling edge of SCLK. There is no continual read opera-
tion. A logic high (1) must be written into the R/W bit to enable
the subsequent read cycle. The sequence for reading back is
shown in Figure 54 to Figure 57, showing the operation of the
input and output functions of the SDIO pin. The actual
waveforms during the readback process are shown in Figure 57
to Figure 59. SDIO is enabled as an output only during the read
cycle in Figure 57.
SCLK
WRITE VALUE
WRITE 0x0054
R/W BIT LOW ON SDIO_IN
DATA WRITTEN ON RISING CLOCK EDGE
13488-047
CSA, CSB
SDIO (IN)
S
DIO (OUT)
Figure 54. Write Gain Control Word
SCLK
SET UP READ
WRITE 0x0100
R/W BIT LOW ON SDIO_OUT
13488-048
CSA, CSB
SDIO (IN)
SDIO (OUT)
Figure 55. Write Logic 1 into R/W Bit
SCLK
SDIO (IN)
SDIO (OUT)
PERFORM READ
READ 0x0154
R/W BIT HIGH
DATA READ ON FALLING CLOCK EDGE
13488-049
CSA, CSB
SDIO OUTPUT ENABLED
Figure 56. Perform Read
CH1 1V/DIV CH2 1V/DIV A CH2 1.6V
CH3 1V/DIV
1
2
3
13488-050
SCLK
SDIO
CSA OR CSB
Figure 57. Write Gain Control Value, 0x0054
Data Sheet ADL5205
Rev. A | Page 21 of 31
CH1 1V CH2 1V
CH3 1V
1
2
3
A CH2 1.6V
13488-051
SCLK
SDIO
CSA OR CSB
Figure 58. Write Read Setup Value, 0x0100
CH1 1V CH2 1V A CH2 760mV
CH3 1V
1
2
3
13488-052
SCLK
SDIO
CSA OR CSB
Figure 59. Read Back Value, 0x0154
ADC INTERFACING
A typical data acquisition system using the ADL5205 together
with an antialiasing filter and an ADC is shown in Figure 60.
The main role of the filter after the amplifier is for attenuating
the broadband noise and out-of-band harmonics generated by
the amplifier. Component values for a 500 MHz acquisition
bandwidth are listed in Table 10. Without this filter, the out-of-
band noise and distortion components alias back into the
Nyquist band, resulting in a reduction of signal-to-noise ratio.
The design of the filter preceding the ADL5205 amplifier is
more specific to the system rejection requirements for the
acquisition system,
C4
R1A
R1B
L3AL1A
L3BL1B
VCM
C2B
C2A
ADC
AMPFILTER
13488-161
Figure 60. ADC Interface (One of Two Channels Shown)
Table 10. Component Values for a 500 MHz Acquisition System
Component Value Description/Comments
Amplifier ½ ADL5205 One channel
L1A, L1B 22 nH Q ≥ 50 at 500 MHz
C2A, C2B 6.8 pF Final value depends on PCB
parasitics
L3A, L3B 22 nH Q ≥ 50 at 500 MHz
C4 1.5 pF
Final value depends on PCB
parasitics
R1A, R1B 10 Ω Not applicable
ADC ½ AD9680 One channel, input
impedance set to 100 Ω
NOISE FIGURE vs. GAIN SETTING
Because of the architecture of the ADL5205, the noise figure
does not degrade significantly for the first 12 dB of gain reduction
from the maximum gain setting. The noise figure increases by 2 dB
only during the first 12 dB of gain reduction, after which it
resumes the 1 dB degradation for each dB of gain reduction.
0
5
10
15
20
25
30
35
40
45
–10 –5 0 5 10 15 20 25 30
NOISE FIGURE (dB)
GAIN (dB)
ADL5205 AT
200 MHz 5V HP
REGULAR ATTENUATOR-
AMPLIFIER CASCADE
1.2dB
INCREASE
11dB
IMPROVEMENT
13488-162
Figure 61. Noise Figure vs. Gain
ADL5205 Data Sheet
Rev. A | Page 22 of 31
EVALUATION BOARD
OVERVIEW
The ADL5205-EVA LZ evaluation board allows the manual
control of the ADL5205 device through the serial and the
parallel interface ports, as well as the control of the device
through the USB port on a Microsoft® Windows® PC via the
system demonstration platform (SDP) interface board. A 3.3 V
low dropout (LDO) voltage regulator supplies the logic circuits
when the device is running on a 5 V supply.
On-board baluns convert single-ended input signals to differential
form for input to the device and convert the differential output
signals of the device to single-ended form for output. To bypass
these baluns, rearrange the 0 Ω resistors on the board as described
in the Signal Inputs and Outputs section.
The ADL5205-EVA LZ provides all of the support circuitry
required to operate the ADL5205 in its various modes and
configurations. Figure 62 shows the typical bench setup used to
evaluate the performance of the ADL5205.
POWER SUPPLY INTERFACE
The ADL5205-EVA LZ evaluation board requires either a 3.3 V
or 5 V power supply, and an optional negative supply to pull
down the output common-mode dc level to match the ADCs
that require a lower common-mode level. If an external 3.3 V
supply is used, connect it to the test point labeled 3P3V. If a 5 V
supply is used, connect it to the test point labeled 5V. Similarly, if an
external negative supply is used, connect it to the VNEG test point
shown in Figure 62.
ADL5205
CHANNEL B
INPUTS CHANNEL B
CONTROLS
CHANNEL A
INPUTS
CHANNEL A
OUTPUTS
SUPPLY
CLUSTER
5V
VNEG
3.3V
CHANNEL B
OUTPUTS
CHANNEL A
CONTROLS
MODE
SWITCHES PARALLEL
INTERFACE
SDP
INTERFACE
SERIAL
INTERFACE
13488-058
Figure 62. ADL5205-EVALZ Evaluation Board
Data Sheet ADL5205
Rev. A | Page 23 of 31
The power supply jumper configurations (S1 to S3) required for
selecting the evaluation board analog supply (VCC) and digital
supply (VDD) from the external 3.3 V or 5 V power supply are
shown in Table 11. When using a 5 V supply, enable the on-board
3.3 V voltage regulator and select it using the S3 and S2 jumpers,
respectively, to provide digital supply (VDD) to the pull-up resistors
for logic signals.
Table 11. Power Supply Selection Jumpers
Jumper Function
Supply Selection
VCC = 3.3 V VCC = 5 V
S1 VCC selection 3P3V 5V
S2 VDD selection 3P3V VREG
S3 VDD LDO enable AGND 5V
SIGNAL INPUTS AND OUTPUTS
Signal inputs and outputs for each channel come through a pair
of SMA connectors. In the default configuration, on-board
baluns convert single-ended signals from VINA− and VINB−
into differential signals to the device. Similarly, differential output
signals from the device are converted through the on-board baluns
into single-ended form to the VOUTA+ and VOUTB+ connectors.
MANUAL CONTROLS
Three sets of switches provide the manual control of the states
of the device. Their functions are listed in Table 12. When the
individual switch is in the up position, the signal controlled by
the switch is set to logic high.
Table 12. Switch Block Functions
Switch Block Function
Device
Pin No.
SW1 Channel B control (eight positions)
Position 1 PWUPB 17
Position 2 LATCHB 14
Position 3 B0 13
Position 4 B1 12
Position 5 B2 11
Position 6 B3 10
Position 7 B4 9
Position 8 B5 8
SW2 Mode control (three positions)
Position 1 Power mode (PM) 6
Position 2 MODE0 (M0) 5
Position 3 MODE1 (M1) 4
SW3 Channel A control (eight positions)
Position 1 A5 3
Position 2 A4 2
Position 3 A3 1
Position 4 A2 40
Position 5 A1 39
Position 6 A0 38
Position 7 LATCHA 37
Position 8 PWUPA 34
Mode Switches
When the power mode (PM) switch is up (logic high or Logic 1),
the device is in low power mode. When the switch is down
(logic low or Logic 0), the device is in high performance mode.
MODE1 and MODE0 (labeled M1 and M0 on the PCB) select
one of three interface modes for the device (parallel, serial/SPI,
or up/down mode), as shown in Table 13. There is no functional
difference between the mode switch settings of 10 and 11.
Table 13. Mode Switch Settings
MODE1, MODE0 Interface
00 Parallel
01 Serial (SPI)
10 Up/down
11 Up/down
Channel Control Switches
The channel control switches include PWUPA, LATCHA, and A5
to A0 for Channel A and PWUPB, LATCHB, and B5 to B0 for
Channel B.
PWUPA and PWUPB are the up positions (logic high) that turn
on their respective channels. When PM is set to logic low (high
performance mode), the total current consumption increases by
approximately 81 mA (that is, one half of the difference between
the enabled current of 175 mA and the disabled current of 14 mA)
when each channel is enabled. When the PM is set to logic high
(low power mode), the total current consumption increases by
approximately 61 mA (that is, one half of the difference between
the enabled current of 135 mA and the disabled current of 14 mA)
when each channel is enabled.
The LATCHA and LATCHB switches are used with the gain control
input bits (A5 to A0 and B5 to B0) to control the corresponding
channel voltage gain. When these switches are in the down (logic
low) position, the gain changes with the position of the gain
control switches. When these switches are in the up position,
the last gain setting is latched into the corresponding channel
of the ADL5205, and the gain stops changing.
For Bits[A5:A0] and Bits[B5:B0], the following equation
determines the voltage gain of each channel of the ADL5205:
Gain = 26 − [A5:A0] dB
where [A5:A0] is the value representing the binary string formed
by Bits[A5:A0] from 0 to 35. When this value exceeds 35, the
gain is set to minimum (−9 dB). The voltage gain for Channel B
is changed by Bits[B5:B0] in the same manner.
ADL5205 Data Sheet
Rev. A | Page 24 of 31
PARALLEL INTERFACE
The functions of Parallel Interface Connector P3 are identical to
those of the switches in the switch block. The pinout of the
Parallel Interface Connector P3 is listed in Table 14. Logic levels
on the P3 pins override the corresponding switch setting. As a
result, the switches for PWUPA and PWUPB must be in the up
position when using the parallel interface to control the device.
Table 14. Parallel Interface Pinout (P3)
Pin Number
Function
1 PWUPB
2 AGND
3 LATCHB
4 AGND
5 B0
6 AGND
7 B1
8 AGND
9 B2
10 AGND
11 B3
12 AGND
13 B4
14 AGND
15 B5
16 AGND
17 VDD
18 AGND
19 Power mode (PM)
20 AGND
21 MODE0
22 AGND
23 MODE1
24 AGND
25 A5
26 AGND
27 A4
28 AGND
29 A3
30 AGND
31 A2
32 AGND
33 A1
34 AGND
35 A0
36 AGND
37 LATCHA
38 AGND
39 PWUPA
40 AGND
SERIAL INTERFACE
When the mode switches are in the 01 position, the ADL5205
operates in the serial/SPI mode. The pins that are relevant in the
serial/SPI mode are brought out to Serial Interface Connector P2.
The pinout for Serial Interface Connector P2 is listed in Table 15.
Note that only four pins (plus AGND) are used for the SPI, and
they include the following:
• CSA and CSB are the active low serial port enable pins for
Channel A and Channel B, respectively.
• SDIO is the serial data input and output line. SDIO is a
bidirectional pin.
• SCLK is the serial clock pin.
For detailed operations and timing diagrams of the serial port
interface, see the Serial Peripheral Interface (SPI) section. These
signals operate at 3.3 V logic levels.
The CSA and CSB lines can be tied together to program both
channels at the same time.
Table 15. Serial Interface Connector (P2) Pinout
Pin Number Function
1 PWUPA
2 Not applicable
3 FA_A
4 Not applicable
5 CSA
6 Not applicable
7 PM
8 Not applicable
9 SDIO
10 Not applicable
11 SCLK
12 Not applicable
13 CSB
14 Not applicable
15 FA_B
16 Not applicable
17 PWUPB
18 Not applicable
19 AGND
20 Not applicable
Data Sheet ADL5205
Rev. A | Page 25 of 31
STANDARD DEVELOPMENT PLATFORM (SDP)
INTERFACE
The ADL5205-EVALZ connects to the universal serial bus
(USB) port on a Windows-based PC through an SDP board.
The SDP interface board plugs into the P1 connector on the
ADL5205-EVALZ evaluation board and provides all the digital
handshaking to communicate with the USB. Use the SDP with
the ADL5205 control software on the PC.
To cont rol t he ADL5205 through the USB to SDP interface,
nine jumpers must be inserted from the odd numbered pins
(Pin 1, Pin 3, Pin 5, Pin 7, Pin 9, Pin 11, Pin 13, Pin 15, and
Pin 17) to the even numbered pins (Pin 2, Pin 4, Pin 6, Pin 8,
Pin 10, Pin 12, Pin 14, Pin 16, and Pin 18 on the P2 connector,
as shown in Figure 63. No jumper is needed for Pin 19 and Pin 20.
USB
SDP
JUMPERS
SDP
INTERFACE
BOARD
13488-059
Figure 63. SDP Interface Board
A dynamically loadable library (DLL), sdpApi1.dll, provides the
software interface to the actual hardware. The control program,
using the USB interface, can communicate with the hardware
through interface functions in this DLL.
EVALUATION BOARD CONTROL SOFTWARE
Two separate programs are available for use with a Windows-
based PC to control the ADL5205 through the USB to SDP
interface: a command line control program and a program with
a graphical user interface.
COMMAND LINE CONTROL PROGRAM
The adl5205_regw_x_x.exe, where x_x represents the revision
of the program, is a command line program that takes the 8-bit
value represented by the command line argument and writes
into the control register of the ADL5205. The syntax for the
program is shown in Figure 64, which contains a sample run
of the command line control program, showing the help listing.
GRAPHICAL USER INTERFACE (GUI) PROGRAM
The adl5205_ctrlsw_y_y.exe, where y_y represents the revision
of the program, is a GUI program that allows the control of the
ADL5205 functions through an on-screen display. The ADL5205
gain and modes of operation can be controlled interactively
using icons on the computer screen. A typical display from the
GUI control is shown in Figure 65, and the corresponding
control functions are listed in Table 16.
13488-165
Figure 64. Sample Listing Showing Usage of the Command Line Program
ADL5205 Data Sheet
Rev. A | Page 26 of 31
13488-060
A
B
C
D
G
F
E
Figure 65. Main Screen of the ADL5205 Control Software
Table 16. Features on the Control Software Main Screen
Feature Description
A SDP and evaluation board connection status
B Gain setting displays
C Gain control for Channel A and Channel B
D Gain setting readback
E Power mode (high performance (HP) or low power (LP))
F Channel A Fast attack step size
G Channel B fast attack step size
Data Sheet ADL5205
Rev. A | Page 27 of 31
EVALUATION BOARD SCHEMATICS AND LAYOUT
REGULATOR
NC
UPDN_DAT_A_A0
2
VINB+ INPUTB+
UPDN_DAT_B_B0
A5
84.5
C16
VOUTB_NEG
0.1UF
0
INPUTB-
4
DNI
R7 R20
C1
TC2-1T+
VINA+
0
C5
2
R45TC1-1-13M+
0.1UF
C17
R11
VOUTB_POS 0.1UF
VOUTA_POS
R40
R48
DNI
R44
T2
R41
84.5
R9
C9
SDIO_B5
GS1_CSB_N_B3
GS0_FA_B_B2
UPDN_CLK_B_B1
VINB_NEG
INPUTA+
R103
DNI
C3
3
2
R8
0
DNI
TC2-1T+
VINA-
R14
R18
DNI
T1
SAMTECTSW10608GS3PIN
C2
5
0.1UF
4
MODE1
21 E1
1
VREG
C21
C26
3
S3
5
2
1
3
8
7
4
6
A1
C24
1
R98 R99
5V
3
2
1
3
2
1
S1
27
24
21
22
30
29
18
33
13
38
12
39
8
9
17 34
6
PAD
4
5
10
11
7
40
32
31
28
26
25
23
20
19
1
3
2
U1
1
3P3V
R51
R42 R46R38
R47
R50
5432
1VOUTB-
5432
1VOUTA-
R35
R30
1GND3
1
VCMB
1
VCMA
C12
C11
5432
1VOUTB+
5 2
1VOUTA+
2
6
4
3
1
6
4
3
1
T4
C10
1VCC
C13C14C15 C20
1GND2
1
1VDD
C19 C18
95OHM A T 100MHZ
2.2UF
VNEG
NEG_VOLTAGE
1UF
PWUPA
VCC
VCC
DNI
0
VOUTB+
DNI
RED
VCC
0DNI
0
0
0
50
0
0
0
0
0
0
50
A4
FA_A_A2
CSA_N_A3
UPDN_CLK_A_A1
SCLK_B4
RED
10UF
VDD
0.1UF
VCMA
0.1UF
0.1UF10UF0.1UF
PWUPB
BLKBLK
VCMB
ADL5205
YEL
YEL
RED
10UF
3P3V
RED
DNI
VREG
0
DNI
VOUTA-
VOUTB-
100PF100PF
0.01UF
1
VDD
5V
3P3V
C23
BLK
GND1
RED
ADP3303ARZ-3.3
14
16
37
15
36
5V
S2
345
1
5
1
2
DNI
0
1
1
R29
MODE0
C6
0
VINA_POS
2
1SD_N
0
INPUTA-
35
BLK
VNEG
DNI
0
50
0.1UF
EOUT
330K
0.1UF
0
VINB_POS
C7
R1 R17 0.1UF
0
2
R16
R24
R21
3
PM
LATCHB
R2
35
4
T3
0
0.1UF
VINB-
R19
0
R15
0
DNI
0
0.1UF
C8
0.1UF
0
0
R102
DNI
0
R101
0
0
DNI
R104
LATCHA
VINA_NEG
0
R4
84.5
R39
0.1UF
DNI
50
R32
0
R36
0
R37
84.5
R34
0
R10
34.8
DNI
R43
34
VOUTA+
R49
R3
R6
34.8
R5
VOUTA_NEG 0.1UF
C4
0
R31
34.8
34.8
R12
TC1-1-13M+
0
AGND
AGND
AGND
AGND
AGND
AGND
AGND
NC
SEC PRI
AGND
NC
SEC PRI
AGND
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGND
PAD
FA/A2
UPDN_CLK/A1
UPDN_DAT/A0
LATCH_A
VINA-
VINA+
PWUPA
VCMA
NC
NC
VOUTA-
VOUTA+
NC
VPOS
NC
NC
VPOS
NC
VOUTB+
VOUTB-
NC
NC
VCMB
PWUPB
VINB+
VINB-
LATCH_B
UPDN_DAT/B0
UPDN_CLK/B1
GS0/FA/B2
GS1/CSB/B3
SCLK/B4
SDIO/B5
GND
PM
MODE0
MODE1 A5
A4
CSA_N/A3
AGND
AGND
IN
NR
IN1 OUT
OUT1
ERR_N
GND
SD_N
AGND
AGND
AGND
AGND
13488-061
Figure 66. ADL5205-EVALZ Evaluation Board Schematic, Page 1
ADL5205 Data Sheet
Rev. A | Page 28 of 31
13488-062
(P:116)
(P:56)
(P:45)
(P:47)
(P:76)
(P:74)
(P:79)
(P:80)
5435802-2
33K
200
1K 33K
33K1K
5435802-9
200
JEDEC_TYPE=MSOP8
24LC32A-I/MS
DGND
TSW-110-08-G-D
TSW-120-08-G-D
TSW-120-08-G-D
33K
33K
33K
33K
33K
0
0
33K
1K
1K
33K
1K
0.1UF
E014160
FX8-120S-SV(21)
FX8-120S-SV(21)
200
200
200
200
200
200
200
200
100K
DNI
TBD0402
100K
33K
33K
1K
33K
1K
1K
1K
1K
1K
33K
33K
33K
1K
1K
1K
1K
33K1K
33K1K
5435802-9
1K
DGND
33K1K
SW2
P3
P3
R100
SW3
R77
R76
R75
R97
R96
R95
R74
R73
R72
R71
R67
R69
R68
R70
R94
R93
R92
R91
R90
R89
R88
R87
SW1
R65
R64
R63
R61
R62
R60
R59
R85
R84
R83
R82
R81
R80
R79
R58 R78
R57
R56
R55
R54
R53
R52
R28
R23
R22
R13
P2
R33
R26
R27
R25
C22
U2
P1P1
A4
GS1_CSB_N_B3
PWUPA
UPDN_DAT_B_B0
MODE0
GPIO6_SDP
SCL_SDP
TWI_A0
UPDN_CLK_B_B1
PWUPB
LATCHB
PM
A5
CSA_N_A3
FA_A_A2
UPDN_CLK_A_A1
UPDN_DAT_A_A0
LATCHA
PWUPA
VDD
VDD
SDIO_B5
GS1_CSB_N_B3
GS0_FA_B_B2
SCLK_B4
GPIO1_SDP
5V
GPIO0_SDP
SDA_SDP
VDD
TWI_A0
FA_A_A2
CSA_N_A3
SDIO_B5
SCLK_B4
GPIO7_SDP
GPIO4_SDP
GPIO0_SDP
GPIO3_SDP
GPIO2_SDP
GPIO1_SDP
PM
PWUPB
GS0_FA_B2
GPIO6_SDP
GPIO4_SDP
GPIO5_SDP
SDA_SDP
SCL_SDP
GPIO3_SDP
GPIO5_SDP
GPIO7_SDP
SCL_SDP
GPIO2_SDP
GPIO4_SDP
3.3V
3.3V
MODE1
1B
2B
3A 3B
2A
1A
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
1B
2B
3B
4B
5B
6B
7B
8B8A
7A
6A
5A
4A
3A
2A
1A
1B
2B
3B
4B
5B
6B
7B
8B
8A
7A
6A
5A
4A
3A
2A
1A
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7
4
8
5
6
3
2
1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AGND
VSS
VCC
WP
A2
A1
A0
SCL SDA
DGND
AGND
DGND
AGND
DGND
DGND
AGND
Figure 67. ADL5205-EVALZ Evaluation Board Schematic, Page 2
Data Sheet ADL5205
Rev. A | Page 29 of 31
13488-063
Figure 68. ADL5205-EVALZ Evaluation Board Side A
13488-064
Figure 69. ADL5205-EVALZ Evaluation Board Side B
ADL5205 Data Sheet
Rev. A | Page 30 of 31
BILL OF MATERIALS
Table 17. Bill of Materials
Qty. Description Reference Designator Manufacturer Part No.
1 PCB Not applicable Analog Devices 08_039771B
5 Connectors, PCB test points, red, CNLOOPTP 5V, VCC, VDD, 3P3V, VREG Components
Corporation
TP-104-01-02
1 IC, high accuracy, 200 mA, low dropout linear regulator,
SO8
A1 Analog Devices ADP3303ARZ-3.3
17 Capacitors, ceramic, X7R 0402, 0.1 µF, C0402, 10%, 16 V C1 to C12, C15 to C17,
C19, C22
Murata GRM155R71C104KA88D
2 Capacitors, ceramic, X5R 0603, 10 µF, C0603, 20%, 6.3 V C13, C20 Murata GRM188R60J106ME47D
2 Capacitors, ceramic, monolithic chip, C0G, 100 pF,
C0402, 5%, 50 V
C14, C18 Murata GRM1555C1H101JA01D
1 Capacitors, ceramic, 0805 X7R, 1 µF, C0805H53, 10%, 50 V C21 Murata GRM21BR71H105KA12L
1 Capacitor, ceramic, X5R, 10 µF, C0805H60, 10%, 10V C23 KEMET C0805C106K8PACTU
1 Capacitor, ceramic, monolithic X7R, 2.2 µF, C1206H71,
10%, 50 V
C24 Murata GRM31CR71H225KA88L
1 Capacitor, ceramic, C0G 0805, 0.01 µF, C0805, 5%, 50 V C26 Murata GCM2195C1H103JA16D
1 Inductor chip ferrite bead, 0.3 Ω, maximum dc
resistance, 0.5 A, 95 Ω at 100 MHz, L1206-3
E1 Laird Technologies, Inc. LF1206E152R-10
4 Connectors, PCB test point black, CNLOOPTP GND1to GND3, VNEG Components
Corporation
TP-104-01-00
1 Connectors, PCB vertical type receptacle SMD,
FX8-120S-SV(21), CNHRSFX8-120S-SV
P1 Hirose FX8-120S-SV(21)
1 Connectors, PCB BERG header ST male 20P,
TSW-110-08-G-D, CNBERG2X10H330LD36
P2 Samtec TSW-110-08-G-D
1 Connectors, PCB header 40P male, TSW-120-08-G-D,
CNSAMTECTSW-120-08-T-D
P3 Samtec TSW-120-08-G-D
21 Resistors, chip SMD jumper, 0 Ω, R0402, 5% R1, R2, R16 to R21, R24,
R29, R31 to R35, R43 to
R45, R49, R98, R100
Panasonic ERJ-2GE0R00X
4 Resistors, chip SMD ,0402, 84.5 Ω, R0402, 1% R3, R4, R9, R10 Panasonic ERJ-2RKF84R5X
8 Resistors, high frequency chip, 0402, 50 Ω, R0402, 1% R39 to R42, R101 to R104 Vishay FC0402E50R0FST1
4 Resistors, precision thick film chip, 34.5 Ω, R0402, 1% R5, R6, R11, R12 Panasonic ERJ-2RKF34R5X
10 Resistors, film SMD 1206, 200 Ω, R1206, 2% R13, R22, R23, R28, R52 to
R57
Welwyn 200R WCR 1206
2 Resistors, precision thick film chip, R0402, 100 kΩ,
R0402, 1%
R25, R27 Panasonic ERJ-2RKF1003X
1 Resistors, film SMD 0805, 330 kΩ, R0805, 5% R51 Panasonic ERJ-6GEYJ334V
19 Resistors, thick film chip, 1 kΩ, R0603, 1% R58 to R65, R67 to R77 Vishay CRCW06031K00FKEAHP
19 Resistors, chip SMD 0603, 33 kΩ, R0603, 0.5% R78 to R85, R87 to R97 SUSUMU RR0816P-333-D
3 Connectors, PCB BERG header ST male 3P,
SAMTECTSW10608GS3PIN, CNBERG1X3H205LD36
S1 to S3 Samtec TSW-103-08-G-S
2 Switches, DIP SPST, side actuated, 5435802-9,
SWL880W380H310
SW1, SW3 TE Connectivity 5435802-9
1 Switch, SPST DIP, three position AU
(ALCOSWITCH-7000), 5435802-2, SWSQ380H310
SW2 TE Connectivity 5435802-2
2 XFMR RF 1:1, TC1-1-13M+, AT224-1 T2, T4 Mini-Circuits TC1-1-13M+
2 XFMR RF 2:1, TC2-1T+, AT224-1 T1, T3 Mini-Circuits TC2-1T+
1 IC, 35 dB step size programmable DGA, ADL5205,
QFN40_6X6
U1 Analog Devices ADL5205
1 IC, 32 kb serial EEPROM, 24LC32A-I/MS, MSOP8 U2 Microchip Technology 24LC32A-I/MS
2 Connectors, PCB test point yellow, CNLOOPTP VCMA, VCMB Components
Corporation
TP-104-01-04
8 Connectors, PCB coaxial SMA end launch,
JOHNSON142-0701-801, CNJOHNSON142-0701-801
VINA+, VINA−, VINB+,
VINB−, VOUTA+, VOUTA−,
VOUTB+, VOUTB−
Johnson 142-0701-801
Data Sheet ADL5205
Rev. A | Page 31 of 31
OUTLINE DIMENSIONS
1
0.50
BSC
BOTTOM VIEWTOP VI EW
PI N 1
INDICATOR
40
11
20
21
3031
10
EXPOSED
PAD
PI N 1
INDICATOR
SEATING
PLANE
0.05 M AX
0.02 NOM
0.20 RE F
COPLANARITY
0.08
0.30
0.23
0.18
6.10
6.00 S Q
5.90
0.80
0.75
0.70
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 M IN
3.05
2.90 S Q
2.75
COM P LIANT T O JEDEC S TANDARDS M O-220-WJJD-2.
08-22-2013-A
PKG-004333
4.50 RE F
Figure 70. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADL5205ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-16
ADL5205-EVALZ Evaluation Board
1 Z = RoHS-Compliant Part.
©2016–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13488-0-5/19(A)