256Kx32 SSRAM/4Mx32 SDRAM External Memory Solution for Texas Instruments TMS320C6000 DSP WED9LC6816V FEATURES DESCRIPTION Clock speeds: The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 256K x 32 SBSRAM and two 4Mx16 SDRAM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm x 22mm, BGA. * SSRAM: 200, 166,150, and 133 MHz * SDRAMs: 125 and 100 MHz DSP Memory Solution * Texas Instruments TMS320C6201 * Texas Instruments TMS320C6701 Packaging: The WED9LC6816V provides a total memory solution for the Texas Instruments TMS320C6201 and the TMS320C6701 DSPs The Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150 and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . * 153 pin BGA, JEDEC MO-163 3.3V Operating supply voltage Direct control interface to both the SSRAM and SDRAM ports on the "C6x" The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port. Common address and databus 65% space savings vs. monolithic solution Reduced system inductance and capacitance The WED9LC6816V is available in both commercial and industrial temperature ranges. This product is subject to change without notice. Figure 1 - PIN CONFIGURATION TOP VIEW PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 A0-17 A DQ19 DQ23 VCC VSS VSS VSS VCC DQ24 DQ28 DQ0-31 Address Bus Data Bus B DQ18 DQ22 VCC VSS SDCE# VSS VCC DQ25 DQ29 SSCK SSRAM Clock C VCCQ VCCQ VCC SDWE# SDA10 NC VCC VCCQ VCCQ SSADC# SSRAM Address Status Control D DQ17 DQ21 VCC VSS VSS VSS VCC DQ26 DQ30 SSWE# SSRAM Write Enable E DQ16 DQ20 VCC VSS SDCK VSS VCC DQ27 DQ31 SSOE# SSRAM Output Enable F VCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ SDCK SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe G NC NC NC VSS A2 A4 A5 SDRAS# H NC NC A8 VSS VSS NC A1 A3 A10 SDCAS# J A6 A7 A9 VSS VSS NC A0 A11 A12 SDWE# SDRAM Write Enable K A17 NC/A18 NC/A19 VSS VSS NC NC A13 A14 SDA10 SDRAM Address 10/auto precharge L NC NC NC BWE2# BWE3# NC NC A15 A16 SDRAS# SDCAS# BWE0-3# SSRAM Byte Write Enables SDRAM SDQM 0-3 M VCCQ VCCQ VCC BWE0# BWE1# NC VCC VCCQ VCCQ SSCE# Chip Enable SSRAM Device N DQ12 DQ11 VCC VSS VSS VSS VCC DQ4 DQ0 SDCE# Chip Enable SDRAM Device P DQ13 DQ10 VCC VSS SSCK VSS VCC DQ5 DQ1 VCC Power Supply pins Data Bus Power Supply pins, R VCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ VCCQ T DQ14 DQ9 VCC SSADC# SSWE# NC VCC DQ6 DQ2 VSS Ground U DQ15 DQ8 VCC SSOE# SSCE# NC VCC DQ7 DQ3 NC No Contact Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 1 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 2 - BLOCK DIAGRAM A0-17 A0 A1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 SSWE# BWE0# BWE1# BWE2# BWE3# BWE# BW1# BW2# BW3# BW4# SSCE# SSOE# SSADC# CE2# OE# ADSC# SSCK# SDA10 DQ0-7 DQ9-16 DQ8-15 DQ17-24 DQ16-23 DQ25-32 DQ24-31 CK# A12 A13 SDCE# SDRAS# SDCAS# SDWE# SDCK# A12 A13 Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com DQ1-8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM# UDQM# CS# RAS# CAS# WE# CK# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A10/AP BA0 BA1 LDQM# UDQM# CS# RAS# CAS# WE# CK# 2 DQ0-31 DQ0-7 DQ0-7 DQ8-15 DQ8-15 DQ0-7 DQ16-23 DQ8-15 DQ24-31 4377.04E-0816-ss-WED9LC6816V WED9LC6816V OUTPUT FUNCTIONAL DESCRIPTIONS Symbol SSCK SSADC# SSOE# SSWE# SSCE# SDCK SDCE# SDRAS# SDCAS# SDWE# Type Input Signal Pulse Polarity Positive Edge Input Pulse Active Low Input Input Input Pulse Pulse Pulse Active Low Positive Edge Active Low Input Pulse Active Low Function The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. When sampled at the positive rising edge of the clock, SSADC#, SSOE#, and SSWE# define the operation to be executed by the SSRAM. SSCE# disable or enable SSRAM device operation. The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. SDCE# disable or enable device operation by masking or enabling all inputs except SDCK and BWE0 When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE# define the operation to be executed by the SDRAM. A0-17, SDA10 Input Level -- Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to precharge. DQ0-31 Input Output Level -- Data Input/Output are multiplexed on the same pins. BWE0-3# Input Pulse VCC, VSS VCCQ Supply Supply BWE0-3# perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0# is associated with DQ0-7, BWE1# with DQ8-15, BWE2# with DQ16-23 and BWE3# with DQ24-31. Power and ground for the input buffers and the core logic. Data power supply pins, VCC and VCCQ are internally tied together Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 3 4377.04E-0816-ss-WED9LC6816V WED9LC6816V ABSOLUTE MAXIMUM RATINGS Voltage on VCC Relative to VSS VIN (DQx) Storage Temperature (BGA) Junction Temperature Short Circuit Output Current RECOMMENDED DC OPERATING CONDITIONS (0C tA 70C, Commercial; -40C tA 85C, Industrial) -0.5V to +4.6V -0.5V to VCC +0.5V -55C to +125C +150C 100 mA Parameter Supply Voltage (1) Input High Voltage (1,2) Input Low Voltage (1,2) Input Leakage Current 0 VIN VCC Output Leakage (Output Disabled) 0 VIN VCC SSRAM Output High (IOH = -4mA) (1) SSRAM Output Low (IOL = 8mA) (1) SDRAM Output High (IOH = -2mA) SDRAM Output Low (IOL = 2mA) *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol VCC VIH VIL ILI ILO Min 3.135 2.0 -0.3 -10 -10 Max 3.6 VCC +0.3 0.8 10 10 Units V V V A A VOH VOL VOH VOL 2.4 -- 2.4 -- -- 0.4 -- 0.4 V V V V NOTES: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH +6.0V for t tKC/2 Underershoot: VIL -2.0V for t tKC/2 DC ELECTRICAL CHARACTERISTICS (0C tA 70C, Commercial; -40C tA 85C, Industrial) Description Power Supply Current Operating (1,2,3) Conditions SSRAM Active / DRAM Auto Refresh Power Supply Current Operating (1,2,3) SSRAM Active / DRAM Idle Power Supply Current Operating (1,2,3) SDRAM Active / SSRAM Idle CMOS Standby TTL Standby Auto Refresh SSCE# and SDCE# VCC -0.2V, All other inputs at VIN 0.2 or VIN VCC -0.2V SSCE# and SDCE# VIH, All other inputs at VIN VIL or VIN VIH SSRAM Idle / DRAM Auto Refresh Symbol Frequency ICC1 133MHz 150MHz 166MHz 200MHz ICC2 133MHz 150MHz 166MHz 200MHz ICC3 83MHz 100MHz 125MHz ISB1 ISB2 ICC5 Max 625 650 700 800 425 450 495 585 625 650 700 40.0 55.0 300 Units mA mA mA mA mA mA NOTES: 1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading. 2. "Device idle" means device is deselected (CE = VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25C. ICC (operating) is specified at specified frequency. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 4 4377.04E-0816-ss-WED9LC6816V WED9LC6816V SSRAM AC CHARACTERISTICS (0C tA 70C, Commercial; -40C tA 85C, Industrial) Parameter Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to output valid Clock to output invalid Clock to output on Low-Z Clock to output in High-Z Output Enable to output valid Output Enable to output in Low-Z Output Enable to output in High-Z Address, Control, Data-in Setup Time to Clock Address, Control, Data-in Hold Time to Clock Symbol tKHKH tKLKH tKHKL tKHQV tKHQX tKQLZ tKQHZ tOELQV tOELZ tOEHZ tS tH 200MHz Min Max 5 1.6 1.6 3.0 1.5 0 1.5 3 3.0 0 3.0 1.5 0.5 166MHz Min Max 6 2.4 2.4 3.5 1.5 0 1.5 3.5 3.5 0 3.5 1.5 0.5 150MHz Min Max 7 2.6 2.6 3.8 1.5 0 1.5 3.8 3.8 0 3.5 1.5 0.5 133MHz Min Max 8 2.8 2.8 4.0 1.5 0 1.5 4.0 4.0 0 3.8 1.5 0.5 Units ns ns ns ns ns ns ns ns ns ns ns ns SSRAM OPERATION TRUTH TABLE Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None External External External Current Current Current Current Current Current SSCE# H L L L X X H H X H SSADC# L L L L H H H H H H SSWE# X L H H H H H H L L SSOE# X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D NOTE: 1. X means "don't care", H means logic HIGH. L means logic LOW. 2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time for SSOE# and staying HIGH through out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. BGA CAPACITANCE Description Address Input Capacitance (1) Input/Output Capacitance (DQ) (1) Control Input Capacitance (1) Clock Input Capacitance (1) Conditions tA = 25C; f = 1MHz tA = 25C; f = 1MHz tA = 25C; f = 1MHz tA = 25C; f = 1MHz Symbol CI CO CA CCK Max 8 10 8 6 Units pF pF pF pF NOTE: 1. This parameter is sampled. SSRAM PARTIAL TRUTH TABLE Function READ WRITE one Byte (DQ0-7) WRITE all Bytes SSWE# H L L Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com BWE0# X L L 5 BWE1# X H L BWE2# X H L BWE3# X H L 4377.04E-0816-ss-WED9LC6816V WED9LC6816V FIGURE 3 - SSRAM READ TIMING L L C DC CE DD 1 3 4 E E EL V WE L V 1 D 3 4 Figure 4 - SSRAM WRITE TIMING L L C DC CE DD 3 1 4 E E s W WE D D 1 Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com D D 3 6 D 4 D 4377.04E-0816-ss-WED9LC6816V WED9LC6816V SDRAM AC CHARACTERISTICS (0C tA 70C, Commercial; -40C tA 85C, Industrial) Parameter Clock Cycle Time (1) Symbol CL = 3 CL = 2 Clock to valid Output delay (1,2) Output Data Hold Time (2) Clock HIGH Pulse Width (3) Clock LOW Pulse Width (3) Input Setup Time (3) Input Hold Time (3) CK to Output Low-Z (2) CK to Output High-Z Row Active to Row Active Delay (4) RAS\ to CAS\ Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time - Operation (4) Row Cycle Time - Auto Refresh (4,7) Last Data in to New Column Address Delay (5) Last Data in to Row Precharge (5) Last Data in to Burst Stop (5) Column Address to Column Address Delay (6) tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD 125MHz Min 8 10 100MHz Max 1000 1000 6 3 3 3 2 1 2 Min 10 12 3 3 3 2 1 2 7 20 20 20 50 70 70 1 1 1 1 83MHz Max 1000 1000 7 10,000 Min 12 15 3 3 3 2 1 2 7 20 20 20 50 80 80 1 1 1 1 Units Max 1000 1000 8 10,000 8 24 24 24 60 90 90 1 1 1 1 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK NOTES: 1. Parameters depend on programmed CAS# latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. A new command may be given tRFC after self-refresh exit. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 7 4377.04E-0816-ss-WED9LC6816V WED9LC6816V CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM (Unit = number of clock) Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) CAS Latency 3 3 2 tRC 70ns 9 7 6 tRAS 50ns 6 5 4 tRP 20ns 3 2 2 tRRD 20ns 2 2 2 tRCD 20ns 3 2 2 tCCD 10ns 1 1 1 tCDL 10ns 1 1 1 tRDL 10ns 1 1 1 REFRESH CYCLE PARAMETERS Parameter Symbol Refresh Period (1,2) tREF -10 Min -- -12 Max 64 Min -- Units Max 64 ms NOTES: 1. 4096 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. SDRAM COMMAND TRUTH TABLE Function Mode Register Set Auto Refresh (CBR) Precharge Single Bank Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Device Deselect Data Write/Output Disable Data Mask/Output Disable SDCE# L L L L L L L L L L L H X X SDRAS# L L L L L H H H H H H X X X SDCAS# L L H H H L L L L H H X X X SDWE# L H L L H L L L H L H X X X BWE# X X X X X X X X X X X X L H A12, A13 X BA X BA BA BA BA BA X X X X X SDA10 A11-0 OP CODE X L H Row Address L H L H X X X X X Notes 2 2 2 2 2 2 3 4 4 NOTES: 1. All of the SDRAM operations are defined by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE 0-3 at the positive rising edge of the clock. 2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 8 4377.04E-0816-ss-WED9LC6816V WED9LC6816V MODE REGISTER SET TABLE 11 10 8 9 7 6 3 4 1 ss 0 s s s 11 10 W 0 C L s L 0 s s s. 1 0 3 L 0 3 0 0 0 0 0 1 0 1 0 1 1 0 0 s s 1 0 1 s s 1 1 0 s s 1 1 1 1 1 0 4 4 1 8 1 8 s s 3 0 1 4 6 7 8 9 0 0 - - L 0 0 s 0 0 1 s 0 1 0 0 1 1 1 0 0 s 1 0 1 s 1 1 0 s 1 1 1 s 3 6- 0 D s - W s s s s 0 L 1 Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com C 0 9 L ss 4377.04E-0816-ss-WED9LC6816V WED9LC6816V SDRAM CURRENT STATE TRUTH TABLE Current State Idle Row Active Read Write SDCE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H Command SDRAS# SDCAS# SDWE# A12 & A13 A11-A0 (BA) L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 10 Action Notes Set the Mode Register Start Auto No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst 1 1 Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect 2 1 1 3 1 4,5 4,5 2 5,6 5,6 2 5,6 5,6 4377.04E-0816-ss-WED9LC6816V WED9LC6816V SDRAM CURRENT STATE TRUTH TABLE (cont'd) Current State Read with Auto Precharge Write with Auto Precharge Precharging Row Activating SDCE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H Command SDRAS# SDCAS# SDWE# A12 & A13 A11-A0 (BA) L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X X X X X X Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 11 Action Notes Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD No Operation; Row active after tRCD 2 2 2 2 2 2 20 2 2 2 2 4377.04E-0816-ss-WED9LC6816V WED9LC6816V SDRAM Current State Truth Table (cont'd) Current State Write Recovering Write Recovering with Auto Precharge Refreshing Mode Register Accessing SDCE# L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H Command SDRAS# SDCAS# SDWE# A12 & A13 A11-A0 (BA) L L L OP Code L L H X X L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X X BA BA BA X X X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X OP Code X X Row Address Column Column X X X Action Notes Description Mode Register Set Auto orSelf Refresh ILLEGAL ILLEGAL Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles 2 2 6 6 2 2 2,6 2,6 NOTES: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The RAS# to CAS# Delay (tRCD) must occur before the command is given. 5. Address SDA10 is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 12 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 5 - SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3, BURST LENGTH = 1 0 1 6 4 3 7 8 9 10 11 1 13 14 1 16 17 18 19 DC CC C CL CD DCE CD D CCD DC 0 1 C C DD C 1 13 D 10 C C D D L DWE WE W D Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 13 C E 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 6 - SDRAM POWER UP SEQUENCE 0 1 6 4 3 7 8 9 10 11 1 13 14 1 16 17 18 19 DC DCE C C D DC DD 0 1 1 13 D 10 - D DWE s WE ss s s s s D Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 14 C E 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 7 - SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 3 1 0 4 6 5 7 8 9 10 11 1 13 14 15 16 17 18 19 DC 1 C DCE CD D DC C 0 DD 0 1 C 0 1 13 D 10 C 3 4 0 CL D DL C 1 D 0 3 D 1 D D 3 4 C 3 0 CL 3 DL C 3 1 D 0 D 1 D D 3 DWE WE - - - - W - D C E NOTES: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 15 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 8 - SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 1 0 3 6 4 7 8 9 10 11 1 13 14 1 16 17 18 19 DC DCE CD D DC C 0 DD 0 1 C 0 C 0 C 0 1 13 D 10 DL 0 CL 1 0 D 0 1 D D 1 D 0 D 1 D 0 D 1 CDL 0 CL 3 3 1 D 0 D 1 DWE 3 1 WE - - W - - W - - D C E NOTES: 1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 16 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 9 - SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 1 0 3 7 6 4 8 9 10 11 1 13 14 1 16 17 18 19 DC 1 DCE D DC C DD 0 1 C C C C 1 13 D 10 0 CL 1 3 0 1 3 0 3 0 1 0 1 0 1 3 0 1 0 1 0 D 0 CL 3 1 1 1 DWE WE - - - - - - - D C E - NOTES: 1. SDCE# can be "don't care" when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 17 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 10 - SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 1 3 4 7 6 8 9 10 11 1 13 14 1 16 17 18 19 DC DCE D DC C DD 0 1 C C C 1 13 D 10 CDL D D 0 D 1 D D DL 3 D 0 D 1 D D 3 D 0 D 1 D 0 D 1 DWE 1 WE - - W - W - W - W - s D C E NOTES: 1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 18 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 11 - SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 1 0 3 7 6 4 8 9 10 11 1 13 14 1 16 17 18 19 0 1 DC DCE D DC C DD 0 1 C C 1 13 D 10 CDL 0 CL 1 3 D 0 D 1 D D 3 D 0 D 1 D D 3 1 D CL 3 0 1 3 0 1 DWE WE - - W - - D C E - - NOTES: 1. tCDL should be met to complete write. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 19 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 12 - SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4 1 0 2 3 6 4 7 8 9 10 11 12 13 14 1 16 17 18 19 DCL DCE D DC C DD 0 12 D C 1 13 10 0 CL 2 1 2 3 0 1 2 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D CL 3 3 DWE WE W - - - D - C E NOTES: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode) Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 20 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 13 - SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE 1 0 2 3 4 6 7 8 9 10 11 12 13 14 0 1 0 1 16 17 2 3 4 1 2 3 18 19 DC DCE D DC C DD 0 12 C 1 13 D 10 21 0 CL 2 1 2 3 4 0 1 2 3 1 D 2 2 CL 3 4 4 DWE WE - - s - D C E NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 21 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 14 - SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE 1 0 2 3 6 4 7 8 9 10 11 12 13 14 1 16 17 18 19 DC DCE D DC C DD 0 12 C 1 13 D 10 DL DL 2 D D 0 D 1 D 2 D 3 D D 4 0 D 1 D 2 D 3 D 4 D DWE WE - W - W - s D C E NOTES: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE# at write interrupt by precharge command is needed to prevent invalid write. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row recharge cycle will be masked internally. 3. Burst stop is valid at every burst length. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 22 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 15 - SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2 1 0 2 3 6 4 7 8 9 10 11 12 13 14 1 16 17 18 19 0 1 DC DCE D DC 0 12 D C C DD C C 1 13 10 CL 2 D 0 CL 3 D 0 0 1 D 0 D 0 D 1 1 0 1 DWE WE - - W - W s D - C E NOTES: 1. BRSW modes enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to "1" regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 23 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Figure 16 - SDRAM MODE REGISTER SET CYCLE 0 1 2 3 4 6 7 SDRAM AUTO REFRESH CYCLE 8 0 1 2 3 4 6 7 8 9 10 DC DCE 2 C D 1 DC 3 DD D - - DWE WE s C C D C E *Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle. NOTES: MODE REGISTER SET CYCLE 1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new SDRAS# activation. 3. Please refer to Mode Register Set Table. Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 24 4377.04E-0816-ss-WED9LC6816V WED9LC6816V PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY) JEDEC MP-163 153 0.762 0.030 9 8 7 6 5 4 3 2 1 C D 22.1 0.870 19.05 0.750 E L 1.27 0.61 0.050 10.16 0.400 14.1 0.555 1.97 0.02 0.078 NOTE: Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined. ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Ordering Information Commercial (0C TA 70C) Industrial (-40C TA 85C) Part Number SSRAM Access SDRAM Access Part Number SSRAM Access SDRAM Access WED9LC6816V2012BC 200MHz 125MHz WED9LC6816V2012BI 200MHz 125MHz WED9LC6816V2010BC 200MHz 100MHz WED9LC6816V2010BI 200MHz 100MHz WED9LC6816V1612BC 166MHz 125MHz WED9LC6816V1612BI 166MHz 125MHz WED9LC6816V1610BC 166MHz 100MHz WED9LC6816V1610BI 166MHz 100MHz WED9LC6816V1512BC 150MHz 125MHz WED9LC6816V1512BI 150MHz 125MHz WED9LC6816V1510BC 150MHz 100MHz WED9LC6816V1510BI 150MHz 100MHz WED9LC6816V1312BC 133MHz 125MHz WED9LC6816V1312BI 133MHz 125MHz WED9LC6816V1310BC 133MHz 100MHz WED9LC6816V1310BI 133MHz 100MHz Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 25 4377.04E-0816-ss-WED9LC6816V WED9LC6816V Document Title 256Kx32 SSRAM/4Mx32 SDRAM - External Memory Solution for Texas Instruments TMS320C6000 DSP Revision History Rev # History Release Date Status Rev 2 Changes (Pg. 1, 26) July 2010 Final February 2013 Final August 2016 Final 2.1 Corrected pinout - Row C missing - added, B4 - VSS, B5 - SDCE# 2.2 Corrected MO drawing Rev 3 Changes (Pg. 2, 4, 5, 8) 3.1 Add A17 to Figure 2 - Block Diagram 3.2 Correct DC electrical characteristics: a) Remove TYP Values b) Add SDRAM to conditions for power supply current operations c) Add SSRAM idle / DRAM auto refresh to auto refresh d) Update COMS and TTL standby conditions 3.3 Change SSRAM AC characteristics: a) Clock to output valid from 2.5 max to 3.0 max @ 200MHz b) Output enable to output valid from 2.5 max to 3.0 max @ 200MHz 3.4 Remove clock frequency and latency parameters - 100MHz DRAM 3.5 Change column address to column address delay to 1 versus 1.5 3.6 Remove number of valid output data Rev 4 Changes (Pg. All) (ECN 10156) 4.1 Change document layout from Microsemi to Mercury Systems Mercury Corp. - Memory and Storage Solutions * (602) 437-1520 * www.mrcy.com 26 4377.04E-0816-ss-WED9LC6816V