1
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256Kx32 SSRAM/4Mx32 SDRAM
External Memory Solution for Texas Instruments TMS320C6000 DSP
WED9LC6816V
FEATURES
Clock speeds:
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
Packaging:
• 153 pin BGA, JEDEC MO-163
3.3V Operating supply voltage
Direct control interface to both the SSRAM and SDRAM
ports on the “C6x”
Common address and databus
65% space savings vs. monolithic solution
Reduced system inductance and capacitance
DESCRIPTION
The WED9LC6816V is a 3.3V, 256K x 32
Synchronous Pipe line SRAM and a 4Mx32
Synchronous DRAM array con struct ed with
one 256K x 32 SBSRAM and two 4Mx16
SDRAM die mounted on a multilayer
laminate sub strate. The device is packaged
in a 153 lead, 14mm x 22mm, BGA.
The WED9LC6816V provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150 and 133 MHz, allowing the user to de vel op a fast
external memory for the SSRAM interface port .
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the SDRAM
interface port.
The WED9LC6816V is available in both commercial and in dus tri al
temperature ranges.
This product is subject to change without notice.
TOP VIEW
123456789
ADQ19 DQ23 VCC VSS VSS VSS VCC DQ24 DQ28
BDQ18 DQ22 VCC VSS SDCE# VSS VCC DQ25 DQ29
CVCCQ VCCQ VCC SDWE# SDA10 NC VCC VCCQ VCCQ
DDQ17 DQ21 VCC VSS VSS VSS VCC DQ26 DQ30
EDQ16 DQ20 VCC VSS SDCK VSS VCC DQ27 DQ31
FVCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ
GNC NC NC SDRAS# SDCAS# VSS A2 A4 A5
HNC NC A8 VSS VSS NC A1 A3 A10
JA6 A7 A9 VSS VSS NC A0 A11 A12
KA17 NC/A18 NC/A19 VSS VSS NC NC A13 A14
LNC NC NC BWE2# BWE3# NC NC A15 A16
MVCCQ VCCQ VCC BWE0# BWE1# NC VCC VCCQ VCCQ
NDQ12 DQ11 VCC VSS VSS VSS VCC DQ4 DQ0
PDQ13 DQ10 VCC VSS SSCK VSS VCC DQ5 DQ1
RVCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ
TDQ14 DQ9 VCC SSADC# SSWE# NC VCC DQ6 DQ2
UDQ15 DQ8 VCC SSOE# SSCE# NC VCC DQ7 DQ3
PIN DESCRIPTION
A0-17 Address Bus
DQ0-31 Data Bus
SSCK SSRAM Clock
SSADC# SSRAM Address Status Control
SSWE# SSRAM Write Enable
SSOE# SSRAM Output Enable
SDCK SDRAM Clock
SDRAS# SDRAM Row Address Strobe
SDCAS# SDRAM Column Address Strobe
SDWE# SDRAM Write Enable
SDA10 SDRAM Address 10/auto precharge
BWE0-3# SSRAM Byte Write Enables SDRAM SDQM 0-3
SSCE# Chip Enable SSRAM Device
SDCE# Chip Enable SDRAM Device
VCC Power Supply pins
VCCQ Data Bus Power Supply pins,
VSS Ground
NC No Contact
Figure 1 – PIN CONFIGURATION
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WED9LC6816V
Figure 2 – BLOCK DIAGRAM
A0-17
DQ8-15
DQ0-7
DQ8-15
DQ0-7
DQ8-15
DQ0-7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A11
A12
A13
A14
A15
A16
A17
BWE#
BW1#
BW2#
BW3#
BW4#
CE2#
OE#
ADSC#
CK#
DQ0-31
A0
A1
DQ24-31
DQ16-23
DQ25-32
DQ17-24
DQ9-16
DQ1-8
DQ8-15
DQ0-7
A10/AP
BA0
BA1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A10/AP
BA0
BA1
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK#
A12
A13
A12
A13
DQ24-31
DQ16-23
SSWE#
BWE0#
BWE1#
BWE2#
BWE3#
SSCE#
SSOE#
SSADC#
SSCK#
SDA10
SDCE#
SDRAS#
SDCAS#
SDWE#
SDCK#
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WED9LC6816V
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol Type Signal Polarity Function
SSCK Input Pulse Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADC#
SSOE#
SSWE#
Input Pulse Active Low When sampled at the positive rising edge of the clock, SSADC#, SSOE#, and SSWE# defi ne the operation
to be executed by the SSRAM.
SSCE# Input Pulse Active Low SSCE# disable or enable SSRAM device operation.
SDCK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE# Input Pulse Active Low SDCE# disable or enable device operation by masking or enabling all inputs except SDCK and BWE0
SDRAS#
SDCAS#
SDWE#
Input Pulse Active Low When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE# defi ne
the operation to be executed by the SDRAM.
A0-17,
SDA10 Input Level —
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-11, SDA10 defi nes the row address (RA0-10) when sampled at the
rising clock edge.
During a Read or Write command cycle, A0-7 defi nes the column address (CA0-7) when sampled at the
rising clock edge. In addition to the row address, SDA10 is used to invoke autoprecharge operation at the
end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 defi ne
the bank to be precharged. If SDA10 is low, autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which
bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13.
If SDA10 is low, then A12 and A13 are used to defi ne which bank to precharge.
DQ0-31 Input
Output Level — Data Input/Output are multiplexed on the same pins.
BWE0-3# Input Pulse BWE0-3# perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0#
is associated with DQ0-7, BWE1# with DQ8-15, BWE2# with DQ16-23 and BWE3# with DQ24-31.
VCC, VSS Supply Power and ground for the input buffers and the core logic.
VCCQ Supply Data power supply pins, VCC and VCCQ are internally tied together
WED9LC6816V
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ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Relative to VSS -0.5V to +4.6V
VIN (DQx) -0.5V to VCC +0.5V
Storage Temperature (BGA) -55°C to +125°C
Junction Temperature +150°C
Short Circuit Output Current 100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in operational sections of this specifi cations is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Parameter Symbol Min Max Units
Supply Voltage (1) VCC 3.135 3.6 V
Input High Voltage (1,2) VIH 2.0 VCC +0.3 V
Input Low Voltage (1,2) VIL -0.3 0.8 V
Input Leakage Current 0 ≤ VIN ≤ VCC ILI -10 10 μA
Output Leakage (Output Disabled) 0 ≤
VIN ≤ VCC
ILO -10 10 μA
SSRAM Output High (IOH = -4mA) (1) VOH 2.4 — V
SSRAM Output Low (IOL = 8mA) (1) VOL — 0.4 V
SDRAM Output High (IOH = -2mA) VOH 2.4 — V
SDRAM Output Low (IOL = 2mA) VOL — 0.4 V
NOTES:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tKC/2
Underershoot: VIL ≤ -2.0V for t ≤ tKC/2
DC ELECTRICAL CHARACTERISTICS
(0°C tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Description Conditions Symbol Frequency Max Units
Power Supply Current Operating
(1,2,3)
SSRAM Active / DRAM Auto Refresh ICC1 133MHz 625 mA
150MHz 650
166MHz 700
200MHz 800
Power Supply Current Operating
(1,2,3)
SSRAM Active / DRAM Idle ICC2 133MHz 425 mA
150MHz 450
166MHz 495
200MHz 585
Power Supply Current Operating
(1,2,3)
SDRAM Active / SSRAM Idle ICC3 83MHz 625 mA
100MHz 650
125MHz 700
CMOS Standby SSCE# and SDCE# ≥ VCC -0.2V, All other inputs at VIN ≤ 0.2 or VIN ≥ VCC -0.2V ISB1 40.0 mA
TTL Standby SSCE# and SDCE# ≥ VIH, All other inputs at VIN ≤ VIL or VIN ≥ VIH ISB2 55.0 mA
Auto Refresh SSRAM Idle / DRAM Auto Refresh ICC5 300 mA
NOTES:
1. ICC (operating) is specifi ed with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE = VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specifi ed at specifi ed frequency.
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WED9LC6816V
SSRAM AC CHARACTERISTICS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Parameter Symbol
200MHz 166MHz 150MHz 133MHz
UnitsMin Max Min Max Min Max Min Max
Clock Cycle Time tKHKH 5678ns
Clock HIGH Time tKLKH 1.6 2.4 2.6 2.8 ns
Clock LOW Time tKHKL 1.6 2.4 2.6 2.8 ns
Clock to output valid tKHQV 3.0 3.5 3.8 4.0 ns
Clock to output invalid tKHQX 1.5 1.5 1.5 1.5 ns
Clock to output on Low-Z tKQLZ 0000ns
Clock to output in High-Z tKQHZ 1.5 3 1.5 3.5 1.5 3.8 1.5 4.0 ns
Output Enable to output valid tOELQV 3.0 3.5 3.8 4.0 ns
Output Enable to output in Low-Z tOELZ 0000ns
Output Enable to output in High-Z tOEHZ 3.0 3.5 3.5 3.8 ns
Address, Control, Data-in Setup Time to Clock tS1.5 1.5 1.5 1.5 ns
Address, Control, Data-in Hold Time to Clock tH0.5 0.5 0.5 0.5 ns
SSRAM OPERATION TRUTH TABLE
Operation Address Used SSCE# SSADC# SSWE# SSOE# DQ
Deselected Cycle, Power Down None H L X X High-Z
WRITE Cycle, Begin Burst External L L L X D
READ Cycle, Begin Burst External L L H L Q
READ Cycle, Begin Burst External L L H H High-Z
READ Cycle, Suspend Burst Current X H H L Q
READ Cycle, Suspend Burst Current X H H H High-Z
READ Cycle, Suspend Burst Current H H H L Q
READ Cycle, Suspend Burst Current HHHHHigh-Z
WRITE Cycle, Suspend Burst Current X H L X D
WRITE Cycle, Suspend Burst Current H H L X D
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time for SSOE# and staying HIGH through out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
BGA CAPACITANCE
Description Conditions Symbol Max Units
Address Input Capacitance (1) tA = 25°C; f = 1MHz CI 8 pF
Input/Output Capacitance (DQ) (1) tA = 25°C; f = 1MHz CO 10 pF
Control Input Capacitance (1) tA = 25°C; f = 1MHz CA 8 pF
Clock Input Capacitance (1) tA = 25°C; f = 1MHz CCK 6 pF
NOTE:
1. This parameter is sampled.
SSRAM PARTIAL TRUTH TABLE
Function SSWE# BWE0# BWE1# BWE2# BWE3#
READ H XXXX
WRITE one Byte (DQ0-7) L L H H H
WRITE all Bytes LLLLL
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WED9LC6816V
FIGURE 3 – SSRAM READ TIMING
C
WE
L L

CE
DC
D

L
13 4
 V


DD
1  3 4
E
ELV
E
Figure 4 – SSRAM WRITE TIMING
L L

 W
s
D1 D D3 D4 D
E
1  3 4 
C
WE
CE
DC
D
DD
E
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WED9LC6816V
SDRAM AC CHARACTERISTICS
(0°C ≤ tA ≤ 70°C, Commercial; -40°C ≤ tA ≤ 85°C, Industrial)
Parameter Symbol 125MHz 100MHz 83MHz Units
Min Max Min Max Min Max
Clock Cycle Time (1) CL = 3 tCC 8 1000 10 1000 12 1000 ns
CL = 2 tCC 10 1000 12 1000 15 1000 ns
Clock to valid Output delay (1,2) tSAC 678ns
Output Data Hold Time (2) tOH 333ns
Clock HIGH Pulse Width (3) tCH 333ns
Clock LOW Pulse Width (3) tCL 333ns
Input Setup Time (3) tSS 222ns
Input Hold Time (3) tSH 111ns
CK to Output Low-Z (2) tSLZ 222ns
CK to Output High-Z tSHZ 778ns
Row Active to Row Active Delay (4) tRRD 20 20 24 ns
RAS\ to CAS\ Delay (4) tRCD 20 20 24 ns
Row Precharge Time (4) tRP 20 20 24 ns
Row Active Time (4) tRAS 50 10,000 50 10,000 60 10,000 ns
Row Cycle Time - Operation (4) tRC 70 80 90 ns
Row Cycle Time - Auto Refresh (4,7) tRFC 70 80 90 ns
Last Data in to New Column Address Delay (5) tCDL 111CK
Last Data in to Row Precharge (5) tRDL 111CK
Last Data in to Burst Stop (5) tBDL 111CK
Column Address to Column Address Delay (6) tCCD 111CK
NOTES:
1. Parameters depend on programmed CAS# latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. A new command may be given tRFC after self-refresh exit.
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WED9LC6816V
CLOCK FREQUENCY AND LATENCY PARAMETERS – 125MHz SDRAM (Unit = number of clock)
Frequency CAS
Latency tRC
70ns tRAS
50ns tRP
20ns tRRD
20ns tRCD
20ns tCCD
10ns tCDL
10ns tRDL
10ns
125MHz (8.0ns) 3 9 6323111
100MHz (10.0ns) 3 7 5222111
83MHz (12.0ns) 2 6 4222111
REFRESH CYCLE PARAMETERS
Parameter Symbol -10 -12 Units
Min Max Min Max
Refresh Period (1,2) tREF —64—64ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
SDRAM COMMAND TRUTH TABLE
Function SDCE# SDRAS# SDCAS# SDWE# BWE# A12, A13 SDA10 A1 1-0 Notes
Mode Register Set L L L L X OP CODE
Auto Refresh (CBR) L L L H X X X
Precharge Single Bank L L H L X BA L 2
Precharge all Banks L L H L X X H
Bank Activate L L H H X BA Row Address 2
Write L H L L X BA L 2
Write with Auto Precharge L H L L X BA H 2
Read L H L L X BA L 2
Read with Auto Precharge L H L H X BA H 2
Burst Termination L H H L X X X 3
No Operation L H H H X X X
Device Deselect H X X X X X X
Data Write/Output Disable X X X X L X X 4
Data Mask/Output Disable X X X X H X X 4
NOTES:
1. All of the SDRAM operations are defi ned by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE 0-3 at the positive rising edge of the clock.
2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled and become high impedance after a two
clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
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WED9LC6816V
MODE REGISTER SET TABLE
30
1
4
8
s
s
s

31
1
4
8
s
s
s
s


sss
0
-
0
-
D
-
0
1
s


CL
s
s
3
s
s
s
s
sL
0
0
1
0
1
0
1
0
1
sLCL
97643
810
 s
sss
1
0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1
3
4
0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1
6
0
0
0
0
1
1
1
1
6-0
8 7

10
11
s
W
0
1
Ws
sL
Lss
9

111000
s
s.
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WED9LC6816V
SDRAM CURRENT STATE TRUTH TABLE
Current
State Command Action Notes
SDCE# SDRAS# SDCAS# SDWE# A12 & A13
(BA) A11-A0 Description
Idle L L L L OP Code Mode Register Set Set the Mode Register 1
L L L H X X Auto or Self Refresh Start Auto 1
L L H L X X Precharge No Operation
L L H H BA Row Address Bank Activate Activate the specifi ed bank and row
L H L L BA Column Write w/o Precharge ILLEGAL 2
L H L H BA Column Read w/o Precharge ILLEGAL 1
L H H L X X Burst Termination No Operation 1
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation
Row Active L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge Precharge 3
L L H H BA Row Address Bank Activate ILLEGAL 1
L H L L BA Column Write Start Write; Determine if Auto Precharge 4,5
L H L H BA Column Read Start Read; Determine if Auto Precharge 4,5
L H H L X X Burst Termination No Operation
L H H H X X No Operation No Operation
H X X X X X Device Deselect No Operation
Read L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge Terminate Burst; Start the Precharge
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write Terminate Burst; Start the Write cycle 5,6
L H L H BA Column Read Terminate Burst; Start a new Read cycle 5,6
L H H L X X Burst Termination Terminate the Burst
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Write L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge Terminate Burst; Start the Precharge
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write Terminate Burst; Start a new Write cycle 5,6
L H L H BA Column Read Terminate Burst; Start the Read cycle 5,6
L H H L X X Burst Termination Terminate the Burst
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
11
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WED9LC6816V
SDRAM CURRENT STATE TRUTH TABLE (cont'd)
Current
State Command Action Notes
SDCE# SDRAS# SDCAS# SDWE# A12 & A13
(BA) A11-A0 Description
Read
with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge ILLEGAL 2
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write ILLEGAL
L H L H BA Column Read ILLEGAL
L H H L X X Burst Termination ILLEGAL
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Write
with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge ILLEGAL 2
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write ILLEGAL
L H L H BA Column Read ILLEGAL
L H H L X X Burst Termination ILLEGAL
L H H H X X No Operation Continue the Burst
H X X X X X Device Deselect Continue the Burst
Precharging L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge No Operation; Bank(s) idle after tRP
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write w/o Precharge ILLEGAL 2
L H L H BA Column Read w/o Precharge ILLEGAL 20
L H H L X X Burst Termination No Operation; Bank(s) idle after tRP
L H H H X X No Operation No Operation; Bank(s) idle after tRP
H X X X X X Device Deselect No Operation; Bank(s) idle after tRP
Row
Activating L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge ILLEGAL 2
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write ILLEGAL 2
L H L H BA Column Read ILLEGAL 2
L H H L X X Burst Termination No Operation; Row active after tRCD
L H H H X X No Operation No Operation; Row active after tRCD
H X X X X X Device Deselect No Operation; Row active after tRCD
12
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WED9LC6816V
SDRAM Current State Truth Table (cont'd)
Current
State Command Action Notes
SDCE# SDRAS# SDCAS# SDWE# A12 & A13
(BA) A11-A0 Description
Write
Recovering L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto orSelf Refresh ILLEGAL
L L H L X X Precharge ILLEGAL 2
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write Start Write; Determine if Auto Precharge 6
L H L H BA Column Read Start Read; Determine if Auto Precharge 6
L H H L X X Burst Termination No Operation; Row active after tDPL
L H H H X X No Operation No Operation; Row active after tDPL
H X X X X X Device Deselect No Operation; Row active after tDPL
Write
Recovering
with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto orSelf Refresh ILLEGAL
L L H L X X Precharge ILLEGAL 2
L L H H BA Row Address Bank Activate ILLEGAL 2
L H L L BA Column Write ILLEGAL 2,6
L H L H BA Column Read ILLEGAL 2,6
L H H L X X Burst Termination No Operation; Precharge after tDPL
L H H H X X No Operation No Operation; Precharge after tDPL
H X X X X X Device Deselect No Operation; Precharge after tDPL
Refreshing L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge ILLEGAL
L L H H BA Row Address Bank Activate ILLEGAL
L H L L BA Column Write ILLEGAL
L H L H BA Column Read ILLEGAL
L H H L X X Burst Termination No Operation; Idle after tRC
L H H H X X No Operation No Operation; Idle after tRC
H X X X X X Device Deselect No Operation; Idle after tRC
Mode Register
Accessing L L L L OP Code Mode Register Set ILLEGAL
L L L H X X Auto or Self Refresh ILLEGAL
L L H L X X Precharge ILLEGAL
L L H H BA Row Address Bank Activate ILLEGAL
L H L L BA Column Write ILLEGAL
L H L H BA Column Read ILLEGAL
L H H L X X Burst Termination ILLEGAL
L H H H X X No Operation No Operation; Idle after two clock cycles
H X X X X X Device Deselect No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then the action may be legal
depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfi ed.
4. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfi ed.
13
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Figure 5 – SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3,
BURST LENGTH = 1
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC
DCE
D
DC
DD
01
113
D
10
D
DWE
CC C CL
CD

 
CD
 
 
   
CCD

C
C
L







 C C C 





 
 D 
  W 


DC
E
WE
14
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WED9LC6816V
Figure 6 – SDRAM POWER UP SEQUENCE
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC
DCE
D
DC
DD
01
113
D10
D
DWE
WE

-

s
s s s
DC
E
 
sss

C C

-
15
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WED9LC6816V
Figure 7 – SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0134567 8 9 10 11 1 13 14 15 16 17 18 19
DC
DCE
D
DWE
DD  C0 C0
CL
CL3
C
3
C
3
C
C
4
4
0 1 
01
113
D10  
WE

-

-

-

-
W
-

-
DC
E
DC

D


3 D0 D1 D D3
0 1  3 D0 D1 D D3
DL
DL
C
CD
1
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ)
after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
16
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Figure 8 – SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC
D
DWE
WE
DC
DD  C0 C0 C0
C0
01
113
D
10 
CL 0 1 0 1  D0
D0 D1 D1
DL
CL3
D
0 1  3 D0
D0 D1 D1
CDL

-

-

-
W
-
W
-

-
DC
E
CD
DCE

3
1
NOTES:
1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
17
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Figure 9 – SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC
DWE
DC
DD  C C C
C
C
01
113
D
10  
CL 1
0  3 0 1  1
3 0 0 1 0 1
CL3
D
1
0  3 0 1 0 3 1 0 1 0 1

-

-

-

-

-

-

- 
-
DC
E
DCE
D
WE

1
NOTES:
1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
18
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Figure 10 – SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC

DCE
D
DC
DD  C  C
C
C
01
113
D
10  
D D0 D1 D D3 D0 D1 D D3 D0
D0 D1 D1
DL
CDL
DWE
WE

-

-
W
-
W
-
W
-
W
-

s
DC
E
1
NOTES:
1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
19
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Figure 11 – SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
013467 8 9 10 11 1 13 14 1 16 17 18 19
DC
D
DWE
DC
DD  C  C  C
01
113
CL 1
0  3 D
D0 D1 D3
1
0 1 
0 3
1  D
D0 D1 D3 0 1
CDL
CL3
D

-

-

-

-
W
-

-

-
DC
E
DCE
WE
D
10   
NOTES:
1. tCDL should be met to complete write.
20
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Figure 12 – SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH = 4
0123467 8 9 10 11 12 13 14 1 16 17 18 19
1
0 2 3 D2
D0 D1 D3
0 3
1 2 D2
D0 D1 D3
  C C
 
DCL
CL2
CL3
D

-

-


-


-
W

-


-
DC
DCE
D
DC
DD
01
1213
DWE
D
10
WE
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
21
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Figure 13 – SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @
BURST LENGTH = FULL PAGE
0123467 8 9 10 11 12 13 14 1 16 17 18 19
DC
D
DC
DD  C C
01
1213
D
10 
CL2 0 1 2 3
2
1
4 1
0 2 3 4 
CL3
D
0 1 2 3 4 0 1 2 3 4 

-

-
s 
-

-
DC
E
DCE
DWE
WE
1
2
2
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
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Figure 14 – SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @
BURST LENGTH = FULL PAGE
0123467 8 9 10 11 12 13 14 1 16 17 18 19
DC

-
W
-
s W
-

-
DC
E
DCE
DWE
D
DC
DD  C C
01
1213
D
10 
D D2D1D0 D3 D4
DL
D3
D0 D1 D2 D4 D
WE
DL
2
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defi ned by AC parameter of tRDL. BWE# at write interrupt by
precharge command is needed to prevent invalid write.
BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row recharge cycle will be masked
internally.
3. Burst stop is valid at every burst length.
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Figure 15 – SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
0123467 8 9 10 11 12 13 14 1 16 17 18 19
DC
DCE
D
DC
DD  C  C C
C
01
1213
CL2 0
D0
D0
1 0
D0 1
1 1 D0 10
CL3
D

- 
-
W
-


-

-

-
W

-

s
D
10  
DWE
DC
E


WE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fi xed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in
the case of BRSW write command, the next cycle starts the precharge.
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Figure 16 –
SDRAM MODE REGISTER SET CYCLE SDRAM AUTO REFRESH CYCLE
D
DC
DD
WE
DC
DCE


D
C  
C  
s 
DWE
DC
E
C
- -
2
1
3

012 34678 01234678910
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS# activation.
3. Please refer to Mode Register Set Table.
25
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WED9LC6816V
PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY) JEDEC MP-163
1.970.078

0.610.02

1.270.050
10.160.400
C
D
E
L
14.10.555
22.10.870
19.050.750
9
1530.7620.030
87654321
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE:
Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defi ned.
Ordering Information
Commercial (0°C ≤ TA ≤ 70°C)
Part Number SSRAM Access SDRAM Access
WED9LC6816V2012BC 200MHz 125MHz
WED9LC6816V2010BC 200MHz 100MHz
WED9LC6816V1612BC 166MHz 125MHz
WED9LC6816V1610BC 166MHz 100MHz
WED9LC6816V1512BC 150MHz 125MHz
WED9LC6816V1510BC 150MHz 100MHz
WED9LC6816V1312BC 133MHz 125MHz
WED9LC6816V1310BC 133MHz 100MHz
Industrial (-40°C ≤ TA ≤ 85°C)
Part Number SSRAM Access SDRAM Access
WED9LC6816V2012BI 200MHz 125MHz
WED9LC6816V2010BI 200MHz 100MHz
WED9LC6816V1612BI 166MHz 125MHz
WED9LC6816V1610BI 166MHz 100MHz
WED9LC6816V1512BI 150MHz 125MHz
WED9LC6816V1510BI 150MHz 100MHz
WED9LC6816V1312BI 133MHz 125MHz
WED9LC6816V1310BI 133MHz 100MHz
26
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Document Title
256Kx32 SSRAM/4Mx32 SDRAM – External Memory Solution for Texas Instruments TMS320C6000 DSP
Revision History
Rev # History Release Date Status
Rev 2 Changes (Pg. 1, 26)
2.1 Corrected pinout – Row C missing - added, B4 - VSS, B5 - SDCE#
2.2 Corrected MO drawing
July 2010 Final
Rev 3 Changes (Pg. 2, 4, 5, 8)
3.1 Add A17 to Figure 2 – Block Diagram
3.2 Correct DC electrical characteristics:
a) Remove TYP Values
b) Add SDRAM to conditions for power supply current operations
c) Add SSRAM idle / DRAM auto refresh to auto refresh
d) Update COMS and TTL standby conditions
3.3 Change SSRAM AC characteristics:
a) Clock to output valid from 2.5 max to 3.0 max @ 200MHz
b) Output enable to output valid from 2.5 max to 3.0 max @ 200MHz
3.4 Remove clock frequency and latency parameters – 100MHz DRAM
3.5 Change column address to column address delay to 1 versus 1.5
3.6 Remove number of valid output data
February 2013 Final
Rev 4 Changes (Pg. All) (ECN 10156)
4.1 Change document layout from Microsemi to Mercury Systems
August 2016 Final