intel. 82586 IEEE 802.3 ETHERNET LAN COPROCESSOR a Performs Compiete CSMA/CD Medium m Supports Minimum Component Systems Shared Bus Configuration Access Control Functions Independently of CPU High-Level Command Interface w Supports Established and Emerging LAN Standards IEEE 802.3/Ethernet (10BASE5) IEEE 802.3/Cheapernet (10BASE2) IEEE 802.3/StarLAN (1BASE5) Proposed 10BASE-T Proposed 10BASE-F Proprietary CSMA/CD Networks up to 10 Mb/s w On-Chip Memory Management Automatic Buffer Chaining Buffer Reclaim After Receipt of Bad Frames Save Bad Frames, Optionally a Interfaces to 8-Bit and 16-Bit Microprocessors Interface to 80186 and 80188 Microprocessors Without Glue w Supports High-Performance Systems Bus Master, with On-Chip DMA - 5-MB/s Bus Bandwidth Compatible with Dual-Port Memory Back-to-Back Frame Reception at 10 Mb/s CRC Error Tally mw Network Management Alignment Error Tally Location of Cable Faults @ Self-Test Diagnostics Internal Loopback External Loopback Internal Register Dump Backoff Timer Check @ 48-Pin DIP and 68-Pin PLCC (see Intel Packaging Documant, Order Number: 231369) SYSTEM INTERFACE SYSTEM CLOCK AND CONTROL SIGNALS BUS INTERFACE UNIT MOST SIGNIFICANT ADDRESS (Ag3 - Ais) Oma CONTROL (4 CHANNELS) on MULTIPLEXED MUX ADDRESS ANO DATA Figure 1. 82586 Functional Block Diagram ZN wn Katy eave Ke = / I W/ | a ae oe Tw MICROINSTAUCTION| FROM SERIAL INTERFACE RECEIVE FIFO (16 BYTES) RECEIVER i+ COT P* CRS r+ -~ RXD 8 we. vara Kod Z J) INTERFACE UNIT TRANSMIT H {16 BYTES} TRANSMITTER b-- TXD p TX /_> ~- CTS *IBM is a trademark of international Busi 1ess Machines Corporation. November 1991 Order Number: 231246-007 231246-182586 in azo 4 aD vec aves []2 a7D a2 ave 3 ap azz ( avr ds sD a2a (WR) ates ab tHE ants 8 43 HOLD ana 7? 42D LOA ani Ja 41D #1 (Ov/A) api2 (9 4b & (BEN) ADT 39D READY (ALE) Apro 36 INT ss 372 aAROY/SADY aoe 3D Vcc aos asf CA aor 4D REGET ADs 3p Mway 405 32h cLK ape a1 CAs aD3 yop coT AD2 20> CTs Apt 28h ATs ADO 27h 1x0 RRE 26 TR ss 25f AXD 231246-2 NOTE: The symbols in parentheses correspond to minimum mode. Top zmoa oun apna iw je geSegRe PSoRR SREB 34 33 32 30 29 28 27 26 25 24 23 22 21 20 19 18 NB2586 43 68L PLCC g 44 (TOP VIEW} ADII \ 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Bur QGwnonaweond Ta mowaa NL ~-eeree a ia eae eh 92 SSIB\ aac PIN NO. 1 MARK << 2 ny =i < 28 Plastic Leaded Chip Carrier ARDY/SROY INT READY(ALE) 50(0EN) S1(DT/R) NC NC 231246-41 Figure 2. 82586 Pinout Diagramsintel. The 82586 is an intelligent, high-perormance Local Area Network coprocessor, implementing the CSMA/CD access method (Carrier Sense Multiple Access with Collision Detection). It performs all time- critical functions independently of trie host proces- sor, which maximizes performance anc. network efficiency. The 82586 performs the full set of IEEE 802.3 CSMA/CD Medium Access Control and channel in- terface functions including: framing, preamble gen- eration and stripping, source address generation, destination address checking, CRC generation and checking, short frame detection. Any data rate up to 10 Mb/s can be used. The 82586 features a powerful host system inter- face. It automatically manages memory structures with command chaining and bidirecti2nal cata chain- ing. An on-chip DMA controller manages four chan- nels transparently to the user. Buffers containing er- rored or collided frames can be automatically recov- ered. The 82586 can be configured for 8 -bit or 16-bit data path, with maximum burst transfer rate of 2 or 4 MB/s respectively. Memory adudress space is 16 megabytes maximum. 82586 The 82586 provides two independent 16-byte Fi- FOs, one for receiving and one for transmitting. The threshold for block transfer to/from memory is pro- grammable, enabling the user to optimize bus over- head for a given worst case bus latency. The 82586 provides a rich set of diagnostic and net- work management functions including: internal and external loopbacks, exception condition tallies, channel activity indicators, optional capture of all frames regardless of destination address, optional capture of errored or collided frames, and time do- main reflectometry for locating faults in the cable. The 82586 can be used in either baseband or broad- band networks. It can be configured for maximum network efficiency (minimum contention overhead) for any length network operating at any data rate up to 10 Mb/s. The controller supports address field lengths of 1, 2, 3, 4, 5, or 6 bytes. It can be contfig- ured for either the IEEE 802.3/Ethernet or HDLC method of frame delineation. Both 16-bit and 32-bit CRCs are supported. The 82586 is fabricated in Intels reliable HMOS II 5-V technology and is available in a 48-pin DIP or 68-pin PLCC package. Table 1. 82586 Pin Description 48 Pin DIP | 68 Pin PLCC| Type Symbol Pin No. Pin No. | Level Name and Function Vee: Voc 48, 36 8,9, 10,17, System Power: + 5V Power Supply. 61, 62 Vss. Vss 12, 24 26, 27, 41, System Ground. 42, 43, 4 RESET 34 13 | RESET is an active HIGH internally synchronized signal, TTL | causing the 82586 to terminate present activity immediately. The signal must be HIGH for at least four clock cycles. The 82586 will execute RESET within ten | system clock cycles starting from RESET HIGH. When i RESET returns LOW, the 82586 waits for the first CA to begin the initialization sequence. TxD 27 22 0 Transmitted Serial Data output signal. This signal is HIGH TTL | when not transmitting. _ eet 4 Tx 26 23 | Transmit Data Clock. This signal provides timing * information to the internal serial logic, depending upon the , mode of data transfer. For NRZ mode of operation, data is transferred to the TxD pin on the HIGH to LOW clock ' transition. | 4 i RxD 25 24 | Received Data Input Signal. TTL _ RxC 23 28 | Received Data Clock. This signal provides timing * information to the internal shifting logic depending upon the mode of data trarisfer. For NRZ data, the state of the RxD L ae _| ; pin is sampled on the HIGH to LOW clock transition. | *See D.C. Characteristics. 4-382586 intel. Table 1. 82586 Pin Description (Continued) Symbol 48 Pin DIP Pin No. 68 Pin PLCC Pin No. Type Level Name and Function a ee 28 at 0 TTL Request To Send signal. When LOW, notifies an external interface that the 82586 has data to transmit. It is forced HIGH after a Reset and while the Transmit Serial Unit is not sending data. | Qa aA a 29 20 | TTL Active LOW Clear To Send input enables the 82586 transmitter to actually send data. It is normally used as an interface handshake to RTS. This signal going inactive stops transmission. It is internally synchronized. If CTS goes inactive, meeting the setup time to TxC negative edge, transmission is stopped and ATS goes inactive within, at most, two TxC cycles. Od aD Oy 31 TTL | oO oO 4 30 Active LOW Carrier Sense input used to notify the 82586 that there is traffic on the serial link. It is used only if the 82586 is configured for external Carrier Sense. When so configured, external circuitry is required for detecting serial link traffic. It is internally synchronized. To be accepted, the signal must stay active for at least two serial clock cycles. 19 I TTL Active LOW Collision Detect input is used to notify the 82586 that a collision has occurred. It is used only if the 82586 is configured for external Collision Detect. External circuitry is required tor detecting the collision. It is internally synchronized. To be accepted, the signal must stay active, for at least two serial clock cycles. During transmission, the | 82586 is able to recognize a collision one bit time after preamble transmission has begun. INT 38 Active HIGH Interrupt request signal. CLK 32 0 |r | MOS 15 The system clock input from the 80186 or another symmetrical clock generator. MN/MX 33 14 | TTL When HIGH, MN/MX selects RD, WR, ALE DEN, DT/R (Minimum Mode). When LOW, MN/MxX selects A22, A23, READY, SO, S1 (Maximum Mode). Note: This pin should be static during 82586 operation. ADO-AD15 6-11, 13-22 a. TTL 29~33, 36- 40, 45, 48, 49, 50, 53, 54 A16-A18 A20-A23 1,3-5 45-47 These lines form the time multiplexed memory address (t1) and data (t2, t3, tW, t4) bus. When operating with an 8-bit bus, the high byte will output the address only during T1. ADO-AD15 are floated after a RESET or when the bus is not acquired. 55-57, 59, 0 63~65 TTL A19/S6 These lines constitute 7 out of 8 most significant address bits for memory operation. They switch during t1 and stay valid during the entire memory cycle. The lines are floated after RESET or when the bus is not acquired. Address lines A22 and A23 are not available for use in minimum mode. | During t1 it forms line 19 of the memory address. During t2 through t4 it is used as a status indicating that this is a Master peripheral cycle, and is HIGH. Its timing is identical to that of ADO-AD15 during write operation.intel. 82586 Tabie 1. 82586 Pin Description (Continued) Symbol 48 Pin DIP Pin No. 68 Pin PLCC Pin No. Type Level Name and Function HOLD 43 67 0 TTL HOLD is an active HIGH signal used by the 82586 to request local bus mastership at the end of the current CPU bus transfer cycle, or at the end of the current DMA burst transfer cycle. In normal operation, HOLD goes inactive before HLDA. The 82586 can be forced off the bus by HLDA going inactive. In this case, HOLD goes inactive within four clock cycles in word mode and eight clock cycles in byte mode. HLDA 42 68 HLDA is an active HIGH Hold Acknowledge signal indicating that the CPU has received the HOLD request and that bus control has been relinquished to the 82586. It is internally synchronized. After HOLD is detected as LOW, the processor drives HLDA LOW. Note, CONNECTING Vcc TO HLDA IS NOT ALLOWED because it will cause a deadlock. Users wanting to give permanent bus access to the 82586 should connect HLDA with HOLD. 35 12 The CA pin is a Channel Attention input used by the CPU to initiate the 82586 execution of memory resident Command Blocks. The CA signal is synchronized internally. The signal must be HIGH for at least one system clock period. It is latched internally on HIGH to LOW edge and then detected by the 82586. ; o x mi 44 66 TTL The Bus High Enable signal (BHE) is used to enable data onto the most significant half of the data bus. Its timing is identical to that of A16-A23. With a 16-bit bus it is LOW and with an 8-bit bus it is HIGH. Note: after RESET, the 82586 is configured to 8-bit bus. READY 39 TTL This active HIGH signal is the acknowledgement from the addressed memory that the transfer cycle can be completed. While LOW, it causes wait states to be inserted. This signal must be externally synchronized with the system clock. The Ready signal internal to the 82586 is a logical OR between READY and SRDY/ARDY. ARDY/SRDY 37 TTL This active HIGH signal performs the same function as READY. If it is programmed at configure time to SRDY, it is identical to READY. ff itis programmed to ARDY, the positive edge of the Ready signal is internally synchronized. Note, the negative edge must still meet setup and hold time specifications, when in ARDY mode. The ARDY signal must be active for at least one system clock HIGH period for proper strobing. The Ready signal internal to the 82586 is a logical OR between READY (in Maximum Mode only) and SRDY/ARDY. Note that following RESET, this pin assumes ARDY mode. 1-582586 intel. Table 1. 82586 Pin Description (Continued) Symbol! 48 Pin DIP Pin No. 68 Pin PLCC. Type PinNo. ._ Level Name and Function g a 40,41 4,3 i oO TT. Maximum mode only. These status pins define the type of DMA transfer during the current memory cycle. They are encoded as follows: Read Memory Write Memory 1 1 Passive ! Status is active from the middle of t4 to the end of t2. They | return to the passive state during t3 or during tW when READY or ARDY is HIGH. These signals can be used by the 8288 Bus Controller to generate all memory control and : timing signals.* Any change from the passive state, signals the 8288 to start the next t1 to t4 bus cycie. These pins are pulled HIGH and floated after a system RESET and when the bus is not acquired. S1 SO 0 0 Not Used 0 1 1 0 we et 46 64 0 TTI. Used in minimum mode only. The read strobe indicates that : the 82586 is performing a memory read cycle. RD is active LOW during t2, t8 and tW of any read cycle. This signal is pulled HIGH and floated after a RESET and when the bus is not acquired. 45 65 0 TT. Used in minimum mode only. The write strobe indicates that the 82586 is performing a write memory cycle. WR is active LOW during t2, t8 and tW of any write cycle. it is pulled HIGH and floats after RESET and when the bus is not acquired. ALE 39 TTL Used in minimum mode only. Address Latch Enable is provided by the 82586 to latch the address into the 8282/8283 address latch Itis a HIGH pulse, during t1 (clock low) of any bus cycle. Note that ALE is never floated. Oo m 2 40 TTL Used in minimum mode only. Data ENable is provided as output enable for the 8286/8287 transceivers in a stand- i alone (no 8288) system. DEN is active LOW during each | memory access. For a read cycle, itis active from the ' middle of t2 until the teginning of t4. For a write cycle, it is active from the beginning of t2 until the middle of t4. It is putled HIGH and floats after a system RESET or when the bus is not acquired. DT/R 41 TTL NOTE: *8288 does not support 10 MHz operation. 1-6 Used in minimum mode only. OT/R is used in non-8288 systems using an 8286/8287 data bus transceiver. It controls the direction of data fiow through the Transceiver. Logically, DT/R is equivalent to $1. It becomes valid in the t4 preceding a bus cycie and remains valid until the final t4 of the cycle. This signa! is pulled HIGH and floated after a RESET or when the bus is not acquired. we Le Ee a ee eeintel. 82586/HOST CPU INTERACTION Communication between the 82586 and the host is carried out via shared memory. The 82586s on-chip DMA capability allows autonomous transfer of data blocks (buffers, frames) and relieves the CPU of byte transfer overhead. The 82586 s optimized to interface the iAPX 186, but due to the small number of hardware signals between the &2586 and the CPU, the 82586 can operate easily with oiher proc- essors. The 82586/host interaction is explained separately in terms of the logical interface and the hardware bus interface. The 82586 consists of two independent units: Com- mand Unit (CU) and Receive Unit (RU). The CU exe- cutes commands from shared memory. The RU handles all activities related to frame reception. The CU and RU enable the 82586 to engage in the two types of activities simultaneously: the Cl! may be fetching and executing commands out of memory, and the RU may be storing received iramess in mem- ory. CPU intervention is only required after the CU executes a sequence of commands cr the RU stores a sequence of frames. The only hardware signals that connect the CPU and the 82586 are INTERRUPT and CHANNEI. ATTEN- TION (see Figure 3). Interrupt is used by the 82586 to draw the CPUs attention to a change ir the con- tents of the SCB. Channel Attention is usad by the CPU to draw the 82586's attention. 82586 SYSTEM MEMORY STRUCTURE The Shared Memory structure consists of four parts: Initialization Root, System Control Block (SCB), 82586 Command List, and Receive Frame Area (RFA) (see Figure 4). The Initialization Root is at a predetermined location in the memory space, (OFFFFF6H), known to both the host CPU and the 82586. The root is accessed at initialization and points to the System Control Block. The System Control Block (SCB) functions as a bidi- rectional mail drop between the host CPU, CU and RU. It is the central element through which the CPU and the 82586 exchange control and status informa- tion. The SCB consists of two parts, the first of which entails instructions from the CPU to the 82586. These include: control of the CU and RU (START, ABORT, SUSPEND, RESUME), a pointer to the list of commands for the CU, a pointer to the receive frame area, and a set of Interrupt acknowl- edge bits. The second entails status information keyed by the 82586 to the CPU, including: state of the CU and RU (e.g. IDLE, ACTIVE READY, SUS- PENDED, NO RECEIVE RESOURCES), interrupts bits (command completed, frame received, CU not ready, RU not ready), and statistics (see Figure 4). The Command List serves as a program for the CU. Individual commands are placed in memory units called a Command Block, or CB. CBs contain com- mand specific parameters and command specific statuses. Specifically, these high level commands are called Action Commands (e.g. Transmit, Config- ure). A specific command, Transmit, causes transmission of a frame by the 82586. The Transmit command block includes Destination Address, Length Field, and a pointer to a list of linked buffers that holds the frame to be constructed from several buffers scat- tered in memory. The Command Unit performs with- CHANNEL ATTENTION Log --. -: INTR INTERRUPT SHARED MEMORY CA 82596 INITIALIZATION ROOT h SYSTEM CONTROL BLOCK (SCB): . yY MAILBOX RECEIVE FRAME comma NO AREA 231246-3 Figure 3. 82586/Host CPU Interaction 1-782586 INITIALIZATION ROOT SYSTEM CONTROL | BLOCK (SCB) STATUS COMMAND COMMAND LIST POINTER COMMAND BLOCK RECEIVE FRAME POINTER STATISTICS COMMAND LIST (C@L) RECEIVE FRAME AREA =A (RFA) xy | "| COMMAND BLOCK TRANSMIT COMMANO (2 (N) TRANSMIT BUFFER DESCRIPTOR REC! BUFFER DESCRIPTOR {ABO} IVE HeCEIvE DESCRIETOR ns (ASO) BUFFER Le ( RECEIVE | RECEIVE | | | a) J RECEIVE BUFFER BUFFER i (2) J L (N} J 231246-4 Figure 4. 82586 Shared Memory Structure out the CPU intervention, the DMA o! each buffer and the prefetching of references to r-ew buffers in parallel. The CPU is notified only after successful transmission or retransmission. The Receive Frame Area is a list of Freie Frame De- scriptors (Descriptors not yet used) anc a list of buff- ers prepared by the user. It is conceptually distinct from the Command List. Frames arrive without being solicited by the 82586. The 82586 mus: be pepared to receive them even if it is engaged i! other activi- ties and to store them in the Free Frarie Araa. The Receive Unit fills the buffers upon fra:ne reception and reformats the Free Buffer List :nto received frame structures. The frame structur:: is virtually identical to the format of the frame to br- transmitted. The first frame descriptor is referenced by SCB. A Frame Descriptor and the associate Bufer De- scriptor wasted upon receiving a Bad Frame (CRC or Alignment errored, Receive DMA overrun errored, or Collision fragmented frame) are automatically re- claimed and returned to the Free Buffe: List. unless the chip is configured to Save Bad Fra:nes 1-8 Receive buffer chaining (i.e. storing incoming frames in a linked list of buffers) improves memory utiliza- tion significantly. Without buffer chaining, the user must allocate consecutive blocks of the maximum frame size (1518 bytes in Ethernet) for each frame. Taking into account that a typical frame size may be about 100 bytes, this practice is very inefficient. With buffer chaining, the user can allocate smail buffers and the 82586 uses only as many as needed. In the past, the drawback of buffer chaining was the CPU processing overhead and the time involved in the buffer switching (especially at 10 Mb/s). The 82586 overcomes this drawback by performing buff- er management on its own for both transmission and reception (completely transparent to the user). The 82586 has a 22-bit memory address range in minimum mode and 24-bit memory address range in maximum mode. All memory structures, the System Control Block, Command List, Receive Descriptor List, and alt buffer descriptors must reside within one 64K-byte memory segment. The Data Buffers can be located anywhere in the memory space.intel. TRANSMITTING FRAMES The 82586 executes high level action commands from the Command List in external memory. Action commands are fetched and executed in parallel with the host CPUs operation, thereby significantly im- proving system performance. The general action commands format is shown in Figure 5. COMMAND STATUS CONTROL FIELDS COMMAND LINK FIELD df. Next (POINTER TO NEXT COMMAND) COMMAND PARAMETER FIELD (COMMANO-SPECIFIC PARAMETERS) 231246-5 Figure 5. Action Command Format Message transmission is accomplished by using the Transmit command. A single Transmit command contains, as part of the command-specific parame- ters, the destination address and length field for the transmitted frame along with a pointer to a buffer area in memory containing the data portion of the frame. (See Figure 15.) The data field is contained in a memory data structure consisting of a Buffer De- scriptor (BD) and Data Buffer (or a linked list of buff- er descriptors and buffers) as shown in Figure 6. The BD contains a Link Field which points to the next BD on the list and a 24-bit address pointing to the Data Buffer itself. The length of the Data !3uffer is speci- fied by the Actual Count field of the 83D. Using the BDs and Data Buffers, multiple Data Buff- ers can be chained together. Thus, a frarne with a long Data Field can be transmitted using multiple (shorter) Data buffers chained together. This chain- ing technique allows the system desicner to develop efficient buffer management policies. The 82586 automatically generates the preamble {alternating 1s and 0s) and start frame delimiter, fetches the destination address and length field from the Transmit command, inserts its unique address as the source address, fetches the ata field from 82586 TRANSMIT (BO} ACTUAL COUNT [~ NEXT BUFFER DESCRIPTOR +INK FIELD 4 oBappness (24 BITS) Burren (OB) 231246-6 Figure 6. Data Buffer Descriptor and Data Buffer Structure buffers pointed to by the Transmit command, and computes and appends the CRC at the end of the frame. See Figure 7. The 82586 can be configured to generate either the Ethernet or HDLC start and end frame delimiters. In the Ethernet mode, the start frame delimiter is 10101011 and the end frame delimiter indicated by the lack of a signal after transmitting the last bit of the frame check sequence field. When in the HDLC mode, the 82586 will generate the 01111110 flag for the start and end frame delimiters and perform the standard bit stuffing/stripping. In addition, the 82586 will optionally pad frames that are shorter than the specified minimum frame length by append- ing the appropriate number of flags to the end of the frame. In the event of a collision (or collisions), the 82586 manages the entire jam, random wait and retry pro- cess, reinitializing DMA pointers without CPU inter- vention. Multiple frames can be sent by linking the appropriate number of Transmit commands togeth- er. This is particularly useful when transmitting a message that is larger than the maximum frame size (1518 bytes for Ethernet). RECEIVING FRAMES In order to minimize CPU overhead, the 82586 is designed to receive frames without CPU supervi- sion. The host CPU first sets aside an adequate START PREAMBLE| FRAME ADDE OBR DELIMITER LENGTH DATA FRAME END FIELD FIELD CHECK FRAME SEQUENCE | DELIMITER Figure 7. Frame Format 1-982586 SYSTEM CONTROL 4 BLOCK Poco Ppo coo FRAME | OESCRIPTOR (RFD) FD 7800 | FO | a FREE BUFFER LIST (FBL) i | RECEIVE SUFFER RED ot e0eny RED | | DESCRIPTOR (RBD) | \ DATA ' BUFFER (DE) ba 068 I RECEIVER FRAME AREA (RFA) amount of receive buffer space and then enables the 82586s Receive Unit. Once enabled, the RU watches for any of its frames which it automatically stores in the Receive Frame Area (RFA). The RFA consists of a Receive Descriptor List (FIDL) and a list 231246-7 Figure 8. Receive Frame Area Diagram RECEIVE FRAME STATUS NEXT RECEIVE LINK FIELD T-_ FRAME DESCRIPTOR of free buffers called the Free Buffer List (FBL) as shown in Figure 8. The individual Receive Frame Descriptors that make up the RDL are used by the 82586 to store the destination and so.irce address, length field and status of each frame that is re- ceived. (Figure 9.) The 82586, once enabled, checks each passing frame for an address match. The 82586 will recog- nize its own unique address, one or more multicast addresses or the broadcast address. |i a match oc- curs, it stores the destination and source address and length fieid in the next available RFD. It then begins filling the next free Data Buffer on the FBL (which is pointed to by the current R&D) with the data portion of the incoming frame. As one DB 1s filled, the 82586 automatically fetches the next DB on the FBL until the entire frame is recerved. This buffer chaining technique is particularly memory effi- cient because it allows the system designer to set aside buffers that fit a frame size that may be much shorter than the maximum allowable frame BUFFER DESCRIPTOR - BUFFER DESCRIPTOR LINK FIELO DESTINATION ADORESS SOURCE ADDRESS LENGTH FIELD 231246-8 Figure 9. Receive Frame Descriptor Once the entire frame is received without error, the 82586 performs the following housekeeping tasks: e Updates the Actual Count field of the last Buffer Descriptor used to hold the frame just received with the number of bytes stored in its associated Data Buffer.intel. e Fetches the address of the next free Receive Frame Descriptor. Writes the address of the next ree Buffer De- scriptor into the next free Receive F-ame De- scriptor. @ Posts a Frame Received interri pt status bit in the SCB. Interrupts the CPU. In the event of a frame error, such s a CRC error, the 82586 automatically reinitializes its (YMA point- ers and reclaims any data buffers coritainirg the bad frame. As long as Receive Frame L[iescriotors and data buffers are available, the 82586 will sontinue to receive frames without further CPU ? elp 82586 NETWORK MANAGEMENT AND DIAGNOSTIC FUNCTIONS The behavior of data communicatr:-n --etworks is typically very complex due to their jistritbuted and asynchronous nature. It is particularly difficult to pin- point a failure when it occurs. The 42586 was de- signed in anticipation of these protiems and includes a set of features for improvir 3 re iability and testability. The 82586 reports on the followir3 events after each frame transmitted: Transmission successful * Transmission unsuccessful: iost C arrier Sense. * Transmission unsuccessful; lost Clear. to-Send. Transmission unsuccessful: DMA ursierrun be- cause the system bus did not ke3p +f with the transmission. Transmission unsuccessful; number ci collisions exceeded the maximum allowed. The 82586 checks each incoming fra ne ard reports on the following errors, (if configured: to Save Bad Frame): CRC error: incorrect CRC in a wel: alignad frame. Alignment error: incorrect CRC i a isaligned frame. e Frame too short: the frame is storter than the configured value for minimum fran-e ie-ngth. Overrun: the frame was not compistely placed in memory because the system bus id m2: keep up with incoming data. Out of buffers: no memory resourc 3s 1) store the frame, so part of the frame was discardad. 82586 NETWORK PLANNING AND MAINTENANCE To perform proper planning, operation, and mainte- nance of a communication network, the network management entity must accumulate information on network behavior. The 82586 provides a rich set of network-wide diagnostics that can serve as the ba- sis for a network management entity. Network Activity information is provided in the status of each frame transmitted. The activity indicators are: * Number of coilisions: number of collisions the 82586 experienced in attempting to transmit this frame. * Deferred transmission: indicates if the 82586 had to defer to traffic on the link during the first trans- mission attempt. Statistics registers are updated after each received frame that passes the address filtering, and is longer than the Minimum Frame Length configuration pa- rameter. CRC errors: number of frames that experienced a CRC error and were properly aligned. e Alignment errors: number of frames that experi- enced a CRC error and were misaligned. No-resources: number of correct frames lost due to lack of memory resources. Overrun errors: number of frame sequences fost due to DMA overrun. The 82586 can be configured to Promiscuous Mode. In this mode it captures all frames transmitted on the Network without checking the Destination Address. This is usetul in implementing a monitoring station to capture all frames for analysis. The 82586 is capable of determining if there is a short or open circuit anywhere in the Network using the built in Time Domain Reflectometer (TDR) mech- anism. STATION DIAGNOSTICS The chip can be configured to External Loopback The transmitter to receiver interconnection can be placed anywhere between the 82586 and the link to locate faults, for example: the 82586 output pins, the Serial Interface Unit, the Transceiver cable, or in the Transceiver82586 The 82586 has a mechanism recognizing the trans- ceiver heart beat signal for verifying the correct op- eration of the Transceivers collision detection cir- Ccuitry. 82586 SELF TESTING The 82586 can be configured to Internal Loopback. It disconnects itself from the Serial Interface Unit, and any frame transmitted is receivec immediately. The 82586 connects the Transmit Data to the Re- ceive Data signal and the Transmit Clack to the Re- ceive Clock. The Dump Command causes the chip to write over 100 bytes of its internal registers to memory. The Diagnose command checks the exponential Backoff random number generator internal to the 82586. CONTROLLING THE 82586 The CPU controls operation of the &2586 s Com- mand Unit (CU) and Receive Unit (RU} of the 82586 via the System Control Block. THE COMMAND UNIT (CU) The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to a CPU program. A Commande Block (CB) is associated with each Action Command. intel. The CU can be modeled as a logical machine that takes, at any given time, one of the following states: e IDLECU is not executing a command and is not associated with a CB on the list. This is the initial state. e SUSPENDEDCU is not executing a command but (different from IDLE) is associated with a CB on the list. e ACTIVECU is currently executing an Action Command, and points to its CB. The CPU may affect the CU operation in two ways: issuing a CU control Command or setting bits in the COMMAND word of the Action Command. THE RECEIVE UNIT (RU) The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a logical machine that takes, at any given time, one of the following states: e {DLERU has no memory resources and is dis- carding incoming frames. This is the initial RU state. NO-RESOURCESRU has no memory resourc- es and is discarding incoming frames. This state differs from the IDLE state in that RU accumu- lates statistics on the number of frames it had to discard. e SUSPENDEDRU has free memory resources to store incoming frames but discard them any- way. 15 ODDBYTE EVENBYTE 0 T T T 7 T T T STAT 0 CUS a AUS of of] o | o (status) 1. 4 4 4 1 1 4 ' T ' \\ T T R T 7 SCB+2 ACK cuc E Auc lL i 4 \ i 1 s 1 i \\ AA (COMMAND) CBL OFFSET SCB+4 RFA OFFSET SCB+6 CRCERRS SCB+8 ALNERRS SCB+ 10 ASCEARS SCB+ 12 OVRNERRAS SCB+ 14 231246-9 Figure 10. System Control Block (SCB) Formatintel. * READY-RU has free memory -esources and stores incoming frames. The CPU may affect RU operation in three ways: issuing an RU Control Command, setting bits in Frame Descriptor, FD, COMMANC: word of the frame currently being received, or setting EL bit of Buffer Descriptor, BD, of the buffer currently being filled. SYSTEM CONTROL BLOCK (SCB) The System Control Block is the :ommunication mail-box between the 82586 and the host CPU. The SCB format is shown in Figure 10. The host CPU issues Control Commands to the 82586 via the SCB. These commands may appear at any time during routine operation, as determined by the host CPU. After the requirec Control Com- mand is setup, the CPU sends a CA sigrial to the 82586. SCB is also used by the 82586 to return status infor- mation to the host CPU. After inserting the required status bits into SCB, the 82586 issues an Interrupt to the CPU. The format is as follows: STATUS word: Indicates the status of the 82586. This word is modified only by the 82586. Defined bits are: * Acommand in the CBL CX (Bit 15) having its I (nterrupt) bit set has been executed. FR (Bit 14) A frame has been received. CNR | (Bit 13) The Commar d Unit left the Active state. ANA | (Bit 12) The Receive -Jnit jeft the Ready state. (3 bits) this ficid contains the status of he Command CUS | (Bits 8-10) Unit. Valid values are: 0 Idle 1 Suspendec 2 Active 3-7 Notl'sed (3 bits) this fie'd coritains the status of the Receive Unit. Valid vaues are: 0 Idle 1 Susp anded 2 No Resources 3 Not Used 4 5- RUS | (Bits 46) Reacy 7 Notl'sed 82586 COMMAND word: Specifies the action to be per- formed as a result of the CA. This word is set by the CPU and cleared by the 82586. Defined bits are: AGK-CX | (Bit 15) * Acknowledges the command executed event. Acknowledges the frame received event. * Acknowledes that the Command Unit became not ready. ACK-RNA | (Bit 12) * Acknowledges that the Receive Unit became not ready. (3 bits) this field contains the command to the Command Unit. NOP (doesnt affect current state of the unit). Start execution of the first command on the CBL. If a command is in execution, then complete it before Starting the new CBL. The beginning of the CBL is in CBL OFFSET. Resume the operation of the command unit by executing the next command. This operation assumes that the command unit has been previously suspended. Suspend execution of commands on CBL after current command is complete. Abort execution of commands immediately. 5-7 Reserved, illegal for use. RUC (Bits 4-6) | (3 bits) This field contains the command to the receive unit. Valid values are: : 0 | @ NCP (does not alter current state of unit). Start reception of frames. If a frame is being received, then complete reception before starting. The beginning cf the RFA is contained in the RFA OFFSET. 2 Resume frame receiving (only when in suspended state.) Suspend frame receiving. If a frame is being received, then complete its reception before suspending. Abort receiver operation immediately. Reserved, illegal foruse. =; Reset chip (logically the same as hardware ACK-FR_ | (Bit 14) ACK-CNA | (Bit 13) CUC (Bits 8-10) 0 1 nm e w e 4 = e w e p e 5-7 (Bit 7) RESET RESET).82586 CBL-OFFSET: Gives the 16-bit offset address of the first command (Action Command) in the command list to be execut- ed following CU-START. Thus, the 82586 reads this word only if the CUC field contained a CUU-START Control Command. RFA-OFFSET: Points to the first Receive Frame De:criptor in the Receive Frame Area. CRCERRS: CRC Errors - contains the numbe of properly aligned frames received with a CRC e'ror ALNERRS: Alignment Errors - contains the number of misa- ligned frames received with a CRC en 3r. RSCERRS: Resource Errors - records the number of ccrrect in- coming frames discarded due to lack of memory resources (buffer space or received f ame descrip- tors). OVRNERRS: Overrun Errors - counts the numbe of received frame sequences lost because the me nory ous was not available in time to transfer them. ACTION COMMANDS The 82586 executes a program that 3 made up of action commands in the Commard Lis As shown in Ss intel. Figure 5, each command contains the command field, status and control fields, link to the next action command in the CL, and any command-specific pa- rameters. This command format is called the Com- mand Block. The 82586 has a repertoire of 8 commands: NOP Setup Individual Address Configure Setup Multicast Address Transmit TDR Diagnose Dump NOP This command results in no action by the 82586, except as performed in normal command process- ing. It is preseni to aid in Command List manipula- tion. NOP command includes the following fields: STATUS word (written by 82586): C (Evt 15) Command Completed B (Bit 14) Busy Executing Command OK (Et 13) Error Free Completion COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14} * Suspend After Completion | (Bit 13) Interrupt After Completion CMD | (Bits0-2) | *NOP = 0 LINK OFFSET: Address of next Command Block 15 ODD BYTE EVEN BYTE 0 0 clpefic|a ZEROS (STATUS) ro - aa T F e | s |i <5 a SEED CMO = 0 2 fF Fe, (COMMAND) LINK OFFSET 4 231246-10 Figure 11. The NOP Command Blockintel. IA-SETUP This command loads the 82586 witt the individual Address. This address is used by the 82586 for rec- 82586 ognition of Destination Address during reception and insertion of Source Address during transmission. The f[A-SETUP command includes the following fields: 1 ODD BYTE EVENBYTE 0 0 c |B | ox] a ZEROS (STATUS) T T . 2 ely s ' CMO =1 (COMMAND) i L LINK OFFSET 4 2ND BYTE ; 1ST BYTE 5 | | --- ; INDIVIDUAL ADDRESS 8 i s = 7s 1 i 10 NTH BYTE ' 231246-11 STATUS word (written by 82586). Cc (Bit 15) | Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Cornpletion A (Bit 12) * Command Aborted COMMAND word: _ EL (Bit 15) End of Command List Ss (Bit 14) Suspend Afte: Cor pletion I (Bit 13) Interrupt Afte: Cornpletion CMD | (BitsO-2) | *IA-SSETUP = 1 __ LINK OFFSET: Address of next Cominand Block INDIVIDUAL ADDRESS: Individual Address pararn- eter The least significant bit of the individual Address pa- rameter must be zero for IEEE 8(2.3/ Ethernet. However, no enforcement of 0 is provided by the 82586. Thus, an Individual Address with least signifi- cant bit 1, is possible. CONFIGURE The CONFIGURE command is used o update the 82586 operating parameters. Figure 12. The |A-SETUP Command Block The CONFIGURE command includes the following fields: STATUS word (written by 82586): Cc (Bit 15) Command Completed B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Completion A (Bit 12) Command Aborted COMMAND word: EL (Bit 15) e End of Command List Ss (Bit 14} Suspend After Completion | (Bit 13) Interrupt After Completion CMD | (BitsO-2) | Configure = 2 LINK OFFSET: Address of next Command Block Byte 6-7: BYTE CNT, (Bits 0-3)| Byte Count, Number of i bytes including this one, holding the parameters to be configured. A number smaller than 4 is interpreted as 4. A number greater than 12 is interpreted as 12.a 82586 intel. 15 ODO BYTE EVEN BYTE o c B oK A ZEROS oo EL $ ' CMD a oz AL. 1 LINK OFFSET 04 Tt qt T T qv T FIFO LIM BYTE CNT 06 1 1 i 1 1 weft | TERY [te] soomeen | Si fete INTERFRAME SPACING er ACA LIN PRIO OA + -++4 i 1 AETRY NUM SLT TM (H} SLOT TIME {lL} oc cDT | cns t 8T CAC INCACTTONO! MAN Bc SAC corr SHC CaF / PAD | ste | 16 | ins |cas| St | pis [PRM| DE MIN FRM LEN 10 231246-13 Figure 13. The CONFIGURE Command Block FIFO-LIM (Bits 8-11)] Value of FIFO 1 Address and Length Threshold. Fields are part of the Byte 8-9: ~~ Transmit/Receive data yte 8-9: buffers, including SRDY/ARDY | (Bit 6) Source Address (which 0 * SRDY/ ARDY pin is not inserted by the operates as ARDY 82586). (internal PREAN- (Bits * Preamble Length synchronization). LEN 12-13) including Beginning of 1 SRDY/ ARDY pin Frame indicator: operates as SRDY 00 - 2 bytes (external 01 - 4 bytes synchronization). 10 - 8 bytes SAV-BF (Bit 7) 11-16 bytes 0 Received bad INT-LPBCK | (Bit 14) Internal Loopback frames are not saved EXT-LPBCK|(Bit15) | External Loopback. Inmemory. NOTE: Bits 14 and 15 1 Received bad configured to 1, cause frames are saved in Internal Loopback. memory. . ADD-LEN | (Bits 8-10)| Numbe: of address Byte 10-11: byes. NOTE: 7 is LIN-PRIO =| (Bits O-2)| Linear Priority interpreted as 0. ACR (Bits 4-6)) * Accelerated Contention AL-LOC (Bit 11) Resolution (Exponential 0 e Address and Length Priority) Fields separated BOF-MET | (Bit 7) Exponential Backoff from data and Method associated with 0 - IEEE 802.3/Ethernet Transmit Corimand 1 - Alternate Method Block cr Recsive Frame iJescr:ptor. For transmitted Frame, Source Address is inserted by the &2586 1-16intel. 82586 INTER FRAME SPACING (Bits 8-15) Numbe: indicating the Interframe Spacing in TxC period units. Byte 12-13: SLOT- TIME (L) SLT-TM (H) RETRY- NUM (Bits 0-7) (Bits 8-10) (Bits 12-15) Slot Time Number, Low Byte Slot Tire Number, High Bits Maximum Number of Transmission Retries on Collisions Byte 14-15: PRM BC-DIS MANCH/ NRZ TONO-CRS NGRC-INS CRC-16 BT-STF PAD CRSF CRS-SRC (Bit 0) (Bit 1) (Bit 2) 0 1 (Bit 3) (Bit 4) (Bit 5) 0 1 (Bit 6) 0 (Bit 7) 0 1 (Bits 8-9) (Bit 11) 0 1 Promiscuous Mode * Broadcast Disable * Manchester or NRZ Encoding/Decoding *NAZ Manchester Transmit on No Carrier Sense * Cease Transmission if CRS Goes Inactive During Frame Transmission * Continue Transmission Even if no Carrier Sense e No CRC Insertion CRC Type: @ 32 bit Autodin Il CRC Polynomial * 16 bit COITY CRC Polynomial Bitstuffing: End of Carrier Mode (Ethernet) HDLC like Bitstuffing Mode Padding * No Padcling Perform Padding by Transmitting Flags for Remainder of Slot Time Carrier Sense Filter in Bit Times Carrier Sense Source External Internal CDTF (Bits * Collision Detect 12-14 Filter in Bit Times CDT-SRC | (Bit 15) Collision Detect Source 0 External 1 * Internal Byte 16: MIN-FRM- | (Bits 0-7) | Minimum Number of Bytes in a Frame CONFIGURATION DEFAULTS The default values of the configuration parameters are compatible with the IEEE 802.3/Ethernet Stan- dards. RESET configures the 82586 according to the defaults shown in Table 2. Table 2. 82586 Default Values Broadcast Disable CRC-16/CRC-32 No CRC Insertion Bitstuffing/EOC Padding Slot Time (Bits) Number of Retries Linear Priority Manchester/NRZ Internal CRS CRS Filter Internal CDT COT Filter Transmit On No CRS FIFO THRESHOLD SRDY/ARDY Save Bad Frame INT Loopback EXT Loopback Promiscucus Mode Preamble Length (Bytes) Address Length (Bytes) Min-Frame-Length (Bytes) Interframe Spacing (Bits) Accelerated Contention Resolution = Exponential Backoff Method = Address/Length Location il a to al Hi I eo0C0CTCOmMmODOOOMO OC OO 1-17a 82586 intel. 15 ODD BYTE EVENBYTE 0 c a | ox] a ZEROS (STATUS) EEE 4 LEIS. t ' 2 e] s]is we CMD = 3 ee EES ' : (COMMAND) LINK OFFSET 4 ss MC-CNT 6 EE MC LIST 2ND BYTE \ 1ST BYTE Mcp ' NTH BYTE ' ADDITIONAL MC-ID'S 291246-14 Figure 14. The MC-SETUP Command Block MC-SETUP Issuing a MC-SETUP command with MC-CNT=0 This command sets up the 82586 with a set of Multi- cast Addresses. Subsequently, incoming frames with Destination Addresses from this set are accept- ed. The MC-SETUP command includes the following fields: STATUS word (written by 82586): Cc (Bit 15) Command Cempleted B (Bit 14) Busy Executing Command OK (Bit 13) Error Free Compietion A (Bit 12) * Command Atorted COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) e Suspend After Completion | (Bit 13) Interrupt After Completion CMD | (Bits 0-2) | MC-SETUP = 3 LINK OFFSET: Address of next Command Block MC-CNT: A 14-bit field indicating tiie number of bytes in the MC-LIST field. MC-CNT is trurcated to the nearest multiple of Address Length (in bytes). disables reception of any incoming frame with a Mui- ticast Address. MC-LIST: A list of Multicast Addresses to be accept- ed by the 82586. Note that the most significant byte of an address is followed immediately by the least significant byte of the next address. Note also that the least significant bit of each Multicast Address in the set must be a one. The Transmit-Byte-Machine maintains a 64-bit HASH table used for checking Multicast Addresses during reception. An incoming frame is accepted if it has a Destination Address whose least significant bit is a one, and af- ter hashing points to a bit in the HASH table whose value is one. The hash function is selecting bits 2 to 7 of the CRC register. RESET causes the HASH ta- ble to become all zeros. After the Transmit-Byte-Machine reads a MC-SET- UP command from TX-FIFO, it clears the HASH ta- ble and reads the bytes in groups whose length is determined by the ADDRESS length. Each group is hashed using CRC logic and the bit in the HASH table to which bits 2-7 of the CRC register point is set to one. A group that is not complete has no ef- fect on the HASH table. Transmit-Byte-Machine noti- fies CU after completion.a i ntl 82586 15 ODD BYTE EVENBYTE 0 7 v c B | oK A o | sto] 59 | sa |] s7 | se | ss} o MAX COLL 3 = > ++ (STATUS) oP Zee = Ca Ce wl, =o | ak 2 {COMMAND) LINK OFFSET 4 NEXT BD OFFSET 5 ' 2ND BYTE ' 1ST BYTE mc le I DESTINATION ADDRESS A i NTH BYTE c .ENGTH FIELD E 231246-15 | Figure 15 The Transmit Command Block TRANSMIT S6 (Bit 6) Heart Beat, indicates that a during Interframe The TRANSMIT command causes qransmission Spacing period after the (and if necessary retransmissior) of @ frame. previous transmission, a i ine. fielce: pulse was detected on TRANSMIT Ga includes the followine fields: the Collision Detect pin. $5 (Bit 5) * Transmission attempt STATUS word (written by 82586): stopped due to number of rn aa oT oe 7 collisions exceeding the [ C (Bit 15) * Command Cc mpleted maximum number of B (Bit 14) Busy Executing retries. : Command MAX- | (Bits 3-0) | Number of Collisions OK (Bit 13) Error Free Complhution COLL experianced by this A (Bit 12) # Command Ab orted frame. S5 = 1 and MAX- $10 (Bit 10) No Carrier Se xse signal ' COLL = 0 indicates that | during transm ssion there were 16 collisions. | (between beg nninc of ' Destination A:/dres:s and COMMAND word: | end of Frame Chec EL (Bit 15) End of Command List | Sequene). Ss (Bit 14) * Suspend After Sg (Bit 9) Transmission Completion | unsuccessful stopped) \ (Bit 13) Interrupt After due to loss oi Slear-to- Completion Seni signal. CMD | (Bits0-2) | TRANSMIT = 4 $8 (Bit 8) Transmission unsuccessful - stopped due o DMA undettun LINK OFFSET: Address of next Command Block | , 5 .6. data not suppled | -Homthe syier for TBD OFFSET: Address of list of buffers holding the i | transmission) information field. TBD-OFFSET = OFFFFH indi- S7 (Bit) |e Transmission vad eo cates that there is no Information field. ____Peter to iraffic on the link. | DESTINATION ADDRESS: Destination Address of the frame LENGTH FIELD: Length field of the frame.a 82586 ] ntel e STATUS word: er measures the time elapsed from transmission ; oo start until echo is obtained. Echo is indicated by EOF * Indicates that this is the Collision Detect going active or Carrier Sense signal Buffer Descriptor of the drop. last buffer of this frames Information Field. TDR command includes the following fields: ACT- (Bits 0-13) | Actual number of data COUNT bytes in buffer (can be pyre or odd) STATUS word (written by 82586): Cc (Bit 15) e Command Completed NEXT BD OFFSET: points to next Buifer Descriptor B (Bit 14) Busy Executing Command in list. tf EOF is set, this field is meaningless. OK (Bit 13) Error Free Completion BUFFER ADDRESS: 24-bit absolute address of buffer. COMMAND word: EL (Bit 15) e@ End of Command List TIME DOMAIN REFLECTOMETER - s (Bit 14) | * Suspend After Completion TDR | (Bit 13) Interrupt After Compietion CMD | (Bits0-2) | e TDR = 5 This command performs a Time Domain Reflectom- eter test on the serial link. By performing the com- mand, the user is able to identify shorts or opens and their location. Along with transmission of All Ones, the 82586 triggers an internal timer. The tim- 15 ODD BYTE EVEN BYTE 0 /, T T Tv T T T TOT OT T + T T EOF ACT COUNT ZL L 1 1 4 1 1 1 1 1 1 1 i 1 (STATUS) NEXT 8D OFFSET 2 BUFFER ADDRESS LLL LLL I f [ L [ /LLL 6 231246-16 Figure 16. The Transmit Buffer Description 18 ODD BYTE EVEN BYTE 0 c B | ox] A ZEROS a (STATUS) LI Eu s$ CMD=5 Z L Z, A L i (COMMAND) LINK OFFSET 4 [ist | Se) re 291246-17 Figure 17. The TDR Command Block 1-20intel. LINK OFFSET: Address of next Command Block RESULT word: LNK-OK |(Bit 15) No Link Problem Identified Transceiver Catle Problem identified (valid only in the case ofa Transceiver that does not return Carner Sense during transmission). Open on thie link identified (valid only in the case o a Transceiver that returns Carrier Sense during transmission). (Bit 12) @ Short on the link identified (valid only in the case o! a Transceiver that returns Carrier Sense during transmission). (Bits 0-10); Specifying the distance to a problem 3n the link (if one exists) in transmit clock cycles. XCVR-PRB|(Bit 14) ET-OPN = |(Bit 13) ET-SRT TIME DUMP This command causes the contents of ovar a hun- dred bytes of internal registers to be placed in mem- ory. It is supplied as a self diagnostic tool, as well as to supply registers of interest to the user. DUMP command includes the followixg fie'ds: 82586 STATUS word (written by 82586): Cc (Bit 15) Command Compieted B (Bit 14) * Busy Executing Command OK (Bit 13) * Error Free Completion COMMAND word: EL (Bit 15) * End of Command List $s (Bit 14) * Suspend After Completion I (Bit 13) @ Interrupt After Completion CMD | (BitsO~-2) | DUMP = 6 LINK OFFSET: Address of next Command Block BUFFER OFFSET: This word specifies the offset portion of the memory address which points to the top of the buffer ailocated for the dumped registers contents. The length of the buffer is 170 bytes. DUMP AREA FORMAT Figure 18 shows the format of the DUMP area. The fields are as follows: Bytes 00H to OAH: These bytes correspond to the 82586 CONFIGURE command field. Bytes OCH to 11H: The Individual Address Register content. IARO is the Individual Address least signifi- cant byte. Bytes 12H to 13H: Status word of last command block (only bits 0-13). 15 0 c | 8 | ox| a ZEROS 0 <> (STATUS) i is T ea CRE 4 (COMMAND) LINK OFFSET 4 BUFFER OFFSET 231246-18 | i Figure 13. The DUMP Command Block 1-2182586 Bytes 14H to 17H: Content of the Transrnit CRC generator. TXCRCRO is the least significant byte. The contents are dependent on the activity before the DUMP command: After RESET - All Ones. After successful transmission - All Zeros. After MC-SETUP command - Generated CRC value of the last MC address, on MC-LIST After unsuccessful transmission, depends on where it stopped. NOTE: For 16-bit CRC only TXCRCRO and 7XCRCR1 are valid. In 9 9 6 7 86 #& 3 2 1 0 18 14 13912 11 1-22 FIFO Lit 00 02 INTERFRAME SPACING 04 NUM | 1 fect TM SLOT TIME (LOW) 06 A ed ed os MIN FRM LEN oa ian oc ian2 oe AR 4 10 of oe AF o] COLL NLM 12 TXCACA TXCACAD TXCACR 3 TKCRCR? 16 RXCACA 1 AXCACAD 18 AXCACR I RXCACR 2 1A TEMPR 1 TEMPRC 1c TEMPR 3 TEMPR Zz 1 TEMPR 5 TEMPR 4 20 a] food VP db 22 MASHR | HASHR ( 24 HASHR 3 HASHAZ 26 HASHR 5 HASHR 4 28 HASHA 7 HASHR 2 ant 2c vy4 2 a0 32 a6 36 36 aa ac o}ofo 3E NXT RB SIZE 40 231246-19 Figure 19 1$ 1413 12:11 10 9 8 7 6 S$ # 3 2? Ff if NXT RB ADA (HIGH) a2 NXT RB AOR (LOW) CUR RB SIZE a6 LA ROD AOR a NXT ROD ADA aa CUR ABD ADR ac CUR RB EBC ae NKT FD AOR 50 CUR FO AOR 52 TEMPORARY $a NXT TB CNT 56 BUF AOR se NXT TB ADA 5A NXT TBD ADR sc LATED AOR SE CLES PEY 60 NXT CB AOR 6? cuR CB 6a 66 SCB AOR 68 o]o}o 5A ojo 6C o|o 6E 70 72 74 76 78 7A 7c Te a0 a2 a4 a6 as eA ac BE ololo BUF ADA PTR (HIGH) 90 BUF ADR PRT (LOW) 92 ACY OMA BC 94 QR ADR- 96 a}olo ACV OMA ADA 9a RCV OMA ADAL 9A 9 o}0 ac 9E ao az aa a6 ae 231246-20 . The DUMP Areas intel. Bytes 18H to 1BH: Contents of Receive CRC Checker. RXCRCRO is the least significant byte. The contents are dapendent on the activity per- formed before the DUMP command: After RESET - All Ones. After good frame reception 1. For CRC-CCITT - OIDOFH 2. For CRC-Autodin-ll - C704DD7E-H After Bad Frame reception - corresponds to the re- ceived information. After reception attempt, i.e. unsuccessful check for address match, corresponds to the CRC performed on the frame address. NOTE: Any frame on the serial link modifies this register contents. Bytes 1CH to 21H: Temporary Registers. Bytes 22H to 23H: Receive Status Fegister. Bits 6, 7, 8, 10, 11 and 13 assume the sarne meaning as corresponding bits in the Receive Frame Descriptor Status field. Bytes 24H to 2BH: HASH TABLE. Bytes 2CH to 2DH: Status bits of the last time TDR command that was performed. NXT-RB-SIZE: Let N be the last bu'fer o* the last received frame, then NXT-RB-SIZE is the number of bytes of available in the N + 1 buffer, El. - The EL bit of the Receive Buffer Descriptor. NXT-RB-ADR: Let N be the last Fileceive Buffer used, then NXT-RB-ADR is the BUFFER-ADDRESS field in the N + 1 Receive-Buffer Descripter, i.e. the pointer to the N + 1 Receive Buffer. CUR-RB-SIZE: The number of bytes in the fast buff- er of the last received frame. EL - Tha El. oit of the last buffer in the last received frame. LA-RBD-ADR: Look Ahead Buffer Descriptor, i.e. the pointer to N + 2 Receiver Buffer Descriptor. NXT-RBD-ADR: Next Receive Buffer Descriptor Ad- dress. Similar to LA-RBD-ADR but pcints to N + 1 Receive Buffer Descriptor. CUR-RBD-ADR: Current Receive Bufer Descriptor Address. Simiiar to LA-RBD-ADR, but point to Nth Receive Buffer Descriptor. 82586 CUR-RB-EBC: Current Receive Buffer Empty Byte Count Let N be the currently used Receive Buffer. Then CUR-RB-EBC indicates the Empty part of the buffer, i.e. the ACT-COUNT of buffer N is given by the difference between its SIZE and the CUR-RB- EBC. NXT-FD-ADR: Next Frame Descriptor Address. De- fine N as the last Receive Frame Descriptor with bits C = 1 andB = 0, then NXT-FD-ADR is the address of N + 2 Receive Frame Descriptor (with B = C = 0) and is equal to the LINK-ADDRESS field in N + 1 Receive Frame Descriptor. CUR-FD-ADR: Current Frame Descriptor Address. Similar to next NXT-FD-ADR but refers to N + 1 Receive Frame Descriptor (with B = 1, C = 0). Bytes 54H to 55H: Temporary register. NXT-TB-CNT: Next Transmit Buffer Count. Let N be the last transmitted buffer of the TRANSMIT com- mand executed recently, the NXT-TB-CNT is the ACT-COUNT field in the Nth Transmit Buffer De- scriptor. EOF - Corresponds to the EOF bit of the Nth Transmit Buffer Descriptor. EOF = 1 indicates that the last buffer accessed by the 82586 during Transmit was the last Transmit Buffer in the data buffer chain associated with the Transmit Corn mand. BUF-ADR: Buffer Address. The BUF-PTR field in the DUMP-STATUS Command Block. NXT-TB-AD-L: Next Transmit Buffer Address Low Let N be the last Transmit Buffer in the transmit buff- er chain of the TRANSMIT Command performed recently, then NXT-TB-AD-L are the two least signifi- cant bytes of the Nth buffer address. LA-TB-ADR: Look Ahead Transmit Buffer Descrip- tor Address. Let N be the last Transmit Buffer in the transmit buffer chain of the TRANSMIT Command performed recently, then LA-TBD-ADR is the NEXT- BD-ADDRESS field of the Nth Buffer Descriptor. NXT-TBD-ADR: Next Transmit Buffer Descriptor Address. Similar in function to LA-TBD-ADR but re- lated to Transmit Buffer Descriptor N-1. Actually, it is the address of Transmit Buffer Descriptor N. Bytes 60H, 61H: This is a copy of the 2nd word in the DUMP-STATUS command presenily executing. NXT-CB-ADR: Next Command Block Address. The LINK-ADDRESS field in the DUMP Command Block presently executing. Points to the next command. CUR-CB-ADR: Current Command Block Address. The address of the DUMP Command Block currently executing. 1-2382586 SCB-ADR: Offset of the System Control Block (SCB). Bytes 7EH, 7FH: RU-SUS-RQ (Bit 4) - Receive Unit Siuspeid Re- quest. Bytes 80H, 81H: CU-SUS-RQ (Bit 4) - Command Unit Suspend Re- quest. END-OF-CBL (Bit 5) - End of Command Block List. If 41 indicates that DUMP-STATUS is tne last com- mand in the command chain. ABRT-IN-PROG (Bit 6) - Command Unit Abort Re- quest. RU-SUS-FD (Bit 12) - Receive Unit Suspend Frame Descriptor Bit. Assume N is the Receive Frame De- scriptor used recently, then RU-SUS-F'D is equiva- lent to the S bit of N + 1 Receive Frame Descriptor. Bytes 82H, 83H: RU-SUS (Bit 4) - Receive Unit in SUSPE NDED state. RU-NRSRC (Bit 5) - Receive Unit in NC: RESOURC- ES state. RU-RDY (Bit 6) - Receive Unit in READY state. RU-IDL (Bit 7) - Receive Unit in IDLE state RNR (Bit 12) - RNR Interrupt in Service: bit. CNA (Bit 13) - CNA Interrupt in Service bit. FR (Bit 14) - FR Interrupt in Service bit CX (Bit 15) - CX Interrupt in Service bit Bytes 90H to 93H: BUF-ADR-PTR - Buffer pointer is the absolute ad- dress of the bytes following the DUMP Command block. Bytes 94H to 95H: RCV-DMA-BC - Receive DMA Byte Count. This field contains number of bytes to be transferred during the next Receive DMA operation. The value de- pends on AL-LOCation configuration bi*. 1-24 a intel. 1. If AL-LOCation = 0 then RCV-DMA-BC = (2 times ADDR-LEN plus 2) if the next Receive Frame Descriptor has already been fetched. 2. If AL-LOCation = 1 then it contains the size of the next Receive Buffer. BR + BUF --PTR + 96H - Sum of Base Address plus BUF PTR field and 96H. RCV-DMA-ADR - Receive DMA absolute Address. This is the next RCV-DMA start address. The value depends on AL-LOCation configuration bit. 1. If AL-LOCation = 0, then RCV-DMA-ADR is the Destination Address field located in the next Re- ceive Frame Descriptor. 2. If AL-LOCation = 1, then RCV-DMA-ADR is the next Receive Data Buffer Address. The following nomenclature has been used in the DUMP table: 0 * The 82586 writes zero in this location. 1 * The 82586 writes one in this location. x The 82586 writes zero or one in this location. tl The 82586 copies this location from the corresponding position in the memory structure. DIAGNOSE The DIAGNOSE Command triggers an internal self test procedure of backoff related registers and coun- ters. The DIAGNOSE command includes the following: STATUS word (written by 82586): Cc (Bit 15) * Command Completed B (Bit 14) * Busy Executing Command OK (Bit 13) Error Free Completion FAIL (Bit 11) Indicates that the Seif Test Procedured Failed COMMAND word: EL (Bit 15) End of Command List Ss (Bit 14) Suspend After Completion I (Bit 13) e Interrupt After Completion CMD | (BitsO-2) | # DIAGNOSE = 7 LINK OFFSET: Address of next Command Block.a i n 82586 5 . 0 c B | ox] A | FAL ZEROS 9 ; ; (STATUS) aoe ' Se a oe a od CMD=7 2 EL] s Lr Ce - rl 1 (COMMAND) LINK OFFSET 231246-21 Figure 20. The DIAGNOSE Command Block tel scp |}_. RFA powres| STATISTICS | | ! To { COMMAND | BLOCK | List fee RECEIVE FRAME AREA __ 1 WFD 1 1 STATUS STATUS STATUS STATUS ' 1 aa 1 RECEIVE 1 { FRAME ' ' DESCRIPTORS =| ' 1 ' 1 ' aap i Eo ! ' 0 | ACT-ent 1] ACT-cnt Jt 0 | ACT-cnt 0] ACT-cnt 0 | ACT-cnt RECEIVE ' \ : BUFFER ' ' DESCRIPTORS =| \ 1 ' 1 i 1 1 1 1 1 ' : i 1 t i 1 1 RECEIVE \ VAUID vauD | | BUFFERS { DATA DATA | | 1 1 ! BUFFES 1 @UFFER2 | BUFFER 3 BUFFER 4 BUFFER 5 ' ' t RECEIVE FRAME LIST 9=~e1-.__ FREE FRAMELIST 9.___ I l 231246-22 Figure 21. The Receive Frame Area RECEIVE FRAME AREA (RFA) The Receive Frame Area, RFA, is trepared by the host CPU, data is placed into the RFA by ihe 82586 as frames are received. RFA consists 9 a list of Receive Frame Descriptors (FD), each o which is associated with a frame. RFA-OFFS:T field of SCB points to the first FD of the chain; the !ast FD is identified by the End-of-Listing flag (:L). See Figure 21. FRAME DESCRIPTOR (FD) FORMAT The FD includes the following fields: STATUS word (set by the 82586): Cc (Bit 15) * Completed Storing Frame. B (Bit 14) FD was Consumed by RU. 4-25os 82586 intel. 15 ODD BYTE EVENBYTE O c B OK 0 Sti] Sto] $9 SB $7 $6 ZEROS 0 ms i; = (STATUS) a Ge ae ee SF 2 LINK OFFSET 4 RBO-OFFSET 6 2NO BYTE | 1ST BYTE wc fa DESTINATION ADDRESS 0 NTH BYTE 12 2ND BYTE | 1ST BYTE 4 SOURCE ADDRESS 16 NTH BYTE | 8 1ST BYTE 2ND BYTE LENGTH FIELD 20 231246-23 Figure 22. The Frame Descriptor (FD) Format OK (Bit 13) e Frame receive. LINK OFFSET: Address of next FD in list. Sooo t this vl . RBD-OFFSET: (initially prepared by the CPU and lat- sel, t With o ot thes e er may be updated by 82586): Address of the first thet h i bits wil te ' RBD that represents the Information Field. RBD- ne offer DUS wih indicate OFFSET = OFFFFH means there is no Information the natura of the error. Field $11 (Bit 11) Received Frame , Experienced CRC Error. DESTINATION ADDRESS (written by 82586): S10 | (Bit 10) * Received Frarie Contains Destination Address of received frame. Experienced a The length in bytes, it is determined by the Address Alignment Errcr. Length configuration parameter. 59 (Bit 9) RU ran out of resources during receptic.n of this SOURCE ADDRESS (written by 82586): Contains frame. Source Address of received frame. Its length is the $8 (Bit 8) RCV-DMA Ove rrun. same as DESTINATION ADDRESS. $7 (Bit 7) Received fram: had fewer bits than LENGTH FIELD (written by 82586): Contains the 2 configured Minimum byte Length or Type Field of received frame. Frame Length. $6 (Bit 6) No EOF fiag detected (only when cor:figured to RECEIVE BUFFER DESCRIPTOR L | Bitstutfing). FORMAT The Receive Buffer Descriptor (RBD) holds informa- COMMAND word: tion about a buffer; size and location, and the means _ OO for forming a chain of RBDs, (forward pointer and EL (Bit 15) Last FD in the | ist. end-of-frame indication). $s (Bit 14) RU should be suspended after receiving his frame. The Buffer Descriptor contains the following fields. 1-26intel 82586 EOF Ff ACT COUNT o 1 4 A L 1 i 1 1 1 i 1 1 (STATUS) NEXT BO OFFSET 2 BUFFER AODRESS 4 EL iV, SIZE 8 LZ) 231246-24 : Figure 23. The Receive Buffer Descriptor (RBD) Format STATUS word (written by the 82586). Bre ADDRESS: 24-bit absolute address of uffer. EOF (Bit 15) Last buffer in received frame. F (Bit 14) ACT COUNT field is valid. EL/SIZE: ACT (Bits 0-13)! * Number of oytes in the EL (BIT 15) Last BD in list. COUNT buffer that are actually SIZE | (Bits 0-13) | * Number of bytes the occupied. buffer is capable of holding. NEXT ABD OFFSET: Address of next BC) in list of BD's. | 1-2782586 intel ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Ambient Temperature Under Bias .. .... OC to 70C *WARNING: Stressing the device beyond the Absolute Storage Temperature............. 65C 0 150C = Maximum Ratings may cause permanent damage. Voltage on Any Pin with These are stress ratings only. Operation beyond the Respect to Ground.............. 1.0V to +7V Operating Conditions is not recommended and ex- oo, tended exposure beyond the Operating Conditions Power Dissipation...................-. 3.0 Watts may affect device reliability. D.C. CHARACTERISTICS Ta = OC to 70C, To = OC to 10C, Vog = 5V +10%, CLK has MOS levels (See Vit, Vain, YMOL: VmMon). TxC and RxC have 82C501 compatible levels (Vivi_, VTIH; VRIH). All other signals have TTL levels (see Vit Vit Vo, On) Symbol Parameter Min Max Units Test Conditions Vit input Low Voltage (TTL) || 0.5 +08 V Vin input High Voltage (TTL 2.0 Veo +051 V VoL Output Low Voltage (TT > 0.45 Vv lo. = 2.6mA VoH Output High Voltage (TTL) 2.4 Vv lon 400 pA VMIL Input Low Voltage (MOS) -0.5 0.6 Vv VMI input High Voltage (MOS) 3.9 Veo tos | V Vrin input High Voltage (Tx 3.3 Veo +05] Vv VRiH input High Voltage (AxC: 3.0 Veo +05 | Vv Vmo. | Output Low Voltage (MC'S) 0.45 V | lo. 25mA VMOH Output High Voltage (MOS) Voc 0.5 Vv lon 400 pA lot Input Leakage Current +10 pA 0< Vin < Voc ILo Output Leakage Current _ +10 pA 0.45 < Vout < Voc Cin Capacitance of Input Bu'fer : 10 pF FC = 1 MHz Cout Capacitance of Output Buffer 20 pF FC = 1 MHz loc Power Supply Current _ 550 mA Ta = 0C gk 450 Ta = 70C 1-28 |intel . 82586 SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS Ta = 0C to 70C, Te = 0C to 108C, Vic = 5V +10%. Figures 24 and 25 define how the measurements should be done. INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS 24- 5 TEST POINTS 1.5 045- 231246-25 AC Testing Inputs are Driven at 2.4V for a Loyic 1 ard 0.45 for a Logic 0. Timing measurements are made at 1.5V for both a Logic 1 and 0 Figure 24. TTL Input/Output Voltage Levels for Timing Measurements Ts Pe T2 TT? 3.9V oe 3.64 N wv = \, HIGH LEVEL MAY VARY WITH VCC 0.9V 0.6V 231246-26 MOS 1/O measurements are taken at 0.1 and 0.9 of he voltage swing Figure 25. System Clock CMOS Input Voitage Levels for Timing Measurements [ 1-2982586 INPUT TIMING REQUIREMENTS* intel. _ 82586-6 82586 2586-10 Symbol Parameter (6 MHz) (8 MHz) (10 MHz) Comments Min | Max | Min | Max | Min Max TH CLK Cycle Period 166 | 2000] 125 | 2000] 100 | 200 T2 CLK LowTimeat15V. 73 | 1000] 55 | 1000] 44 | 1000 13 CLK Low Time at 0.9V 42.5 | 1000] 42.5 | 1000 T4 CLK High Time at 1.5V 73 55 44 T5 CLK High Time at 3.6V 42.5 42.5 T6 CLK Rise Time - 15 15 12 Note 1 17 CLK Fall Time 15 15 12 Note 2 T8 Data in Setup Time _ 20 20 15 T9 Data in Hold Time _ 10 10 10 T10 Async RDY Active Setup T:me 20 20 15 Note 3 TH Async RDY Inactive Setup Time | 35 35 25 Note 3 T12 Async RDY Hold Time 15 15 15 Note 3 T13 Synchronous Ready/Active Setup | 35 35 20 T14 Synchronous Ready Hold Time 0 0 0 T15 HLDA Setup Time _ 20 20 20 Note 3 T16 HLDA Hoid Time 10 10 5 Note 3 T17 Reset SetupTime 20 20 20 Note 3 T18 Reset Hold Time 10 10 10 Note 3 T19 CA Pulse Width _ 171 171 171 T20 CA Setup Time _ 20 20 20 Note 3 T21 CA Hold Time 10 10 10 Note 3 OUTPUT TIMINGS** Symbol Parameter a Min | Max | Min | Max | Min | Max | Comments T22 DT/R Valid Delay _ o | 6 | o | 6 | o | 44 723 WA, DEN Active Delay o | 70 | o | 7 | o | 56 T24 WR, DEN Inactive Delay to | 65 | 10 | 6 | 10 | 45 T25 int. Active Delay _ o | 8 | o | 8 | o | 70 Note 4 T26 Int. Inactive Delay o | 3 | o | e | o | 7 Note 4 127 Hold Active Delay - o | 6 | o | a | o | 70 Note 4 T28 Hold Inactive Delay i o | 3 | o | a5 | o | 70 Note 4 T29 Address Valid Delay _ o | 55 / 0 | 55 | o | 50 T30 Address FloatDelay o | 5 | o | so | 12 | 50 31 Data Valid Delay a o | 5 | o | 6 | o | 50 Note 7 T32 Data Hold Time _ 0 o | 0 | 33 Status Active Delay 10 | 60 | 10 | 60 | 10 | 45 1-30intel : 82586 OUTPUT TIMINGS** (Continued) 82582-6 82586 82586-10 Symbol Parameter (6 MHz) (8 MHz) (10 MHz) Comments Min Max Min Max Min Max T34 Status Inactive Delay | 10 | 70 10 | 70 | 10 | 50 | Notes | T35 ALE Active Delay 79 45 0 45 0 35 | Notes | 136 AlE Inactive Delay 0 45 0 45 0 37 | Notes 137 ALEWidth ts T2-10 T2-10 T2-10 Note5 | T38 Address Valid to ALELcw | T240 T2~30 12-25 "| T39 Address Hold to ALE Inactive | T410 T4~10 T410 T40 RD Active Delay _ 10 95 10 95 10 95 | T41 RD Inactive Delay 10 | 70 | 10 | 70 10 | 70 | T42 RD Width | att 50 271-50 | 271-46 | T43 Address Float to RD Active 10 10 | 0 | T44 AD Inactive to Address Active | 11-40 T140 T1-34 "| TA5 WR Width ~~ | aT 1-40 2T1~40 271-34 | T46 Data Hold After WR! T2-25 T2-25 72-25 | 147 Control Inactive After Reset ; 0 60 0 60 0 60 Note 6 | *All units are in ns. **CL on all outputs is 20~200 pF unles: otherwise specified. NOTES: 1. 1.0V to 3.5V 6. Affects: 2. 3.5V to 1.0V MIN MODE: RD, WA, OT/R, DEN 3. To guarantee recognition at next clocs MAX MODE: SO, St 4.CL = 50 pF 7. High address lines (A16-A24, BHE) become valid one 5.CL = 100 pF clock before T1 only on first memory cycle after the 82586 acquired the bus. 8. 51, SO go inactive just prior to T4. cL N _ XL 4 -$} 125 126 INT SS 231246-27 i 231246-28 | Figure 26. INT Output Timing Figure 27. CA Input Timing cu ~ _* | jo 117 Tih RESET | -| Taz i: | \ | sp - | 23124620 | ee . I Figure 28. RESET Timing | 1-3182586 1-32 READY SIGNAI. T2 T3 ____. CuK XK _, ae, NV ai (-+4 Th2 | CC ARDY 82586, INPUT { a | T4 _ Tha as SRDY i OR VALID READY *K ' -| Ta je 82586 INPUTS ~ 231246-30 Figure 29. ARDY and SRDY Timings Relative to CLK LK Ae ee RNR ET Ln. HOLD ~ : a he ve = ys HLDA = 2 an i BNE ADD apis *O f = | 16-823 $0 1 T16 wt be DT/R RD Wi se > CPU MASTER naan t 82585-MASTER Tt 2 = fe 130 231246-31 Figure 30 HOL.D/HLDA Timing Relative to CLKin 82586 2 v3 T4 BHE A16-A18 419/56 ADO-ADIS DATA IN AG rat 291246-32 Figure 31. Read Cycle Timing _ Ty 8 17 Tw VCH CLK \ \ A VCL 14 8 s1 ee oo taa_ {_/ 29 Py 734 a 129 BHE a16-Ai8 A20-A23K A19/56 x ANS Y $6 ined fo-- 131 32 -] A moc ALE y h i. T35 r met fe 136 ~ rae} tetas raz wf ADO-AD15 K aoa's | DATA OUI 129 he [ - le 730 WR - 8 45 r46 WR __} JS = T23 T2a> am OEN 7?3___.| pe _ 124 " ' 231246-33 Figure 32. Write Cycle Timing 1-3382586 SERIAL INTERFACE A.C. TIMING CHARACTERISTICS for Manchester: f min = 500 kHz + + f max = 10 MHz CLOCK SPECIFICATION Applies for TxC, AxC for NRZ: f min = 100 f max = 10 MHz + 100 ppm kHz + 100 ppm A.C. CHARACTERISTICS ; T51, 1752 = ~+5% af TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION 100 ppm 100 ppm for Manchester, symmetry is needed: intel. symbol | Parameter Min [. Max L. Comments TRANSMIT CLOCK PARAMETERS 748 TxC Cycle _ 100 1000 | Notes 14, 2 148 TxG Cycle _ 100 Notes 14, 3 T49 TxC Rise Time - 5 Note 14 | T50 TxCFallTime 5 Note 14 mo | FxC High Time @ 3.0V 40 1000 | Note 14 T52 TxC LowTime @0.9V. 40 Notes 14, 4 TRANSMIT DATAPARAMETERS __ 153 TxDRiseTime 10 Notes 5, 13 T54 TxD FaliTime 10 Notes 5, 13 T55 TxD Transition-Transiti in Min (T51, Notes 2,5 T52)- 7 T56 TxC LowtoTxD Valid 40 Notes 3, 5 T57 TxC Low to TxD Transiion 30 Notes 2,5 T58 TxC High to TxD 7 ransition " 30 Notes 2,5 T59 TxC Low to TxD High a the Transmission End 40 Note 5 | REQUEST TO SEND/CLEAR TO SEND PARAMETERS - T6O TxC Low to RTS Low. 1:me to Activate RTS 40 Note 6 T61 GTS Valid to TxG Low. (STS Setup Time 45 T62 TxC Low to CTS Invalid CTS Hold Time 20 Note 7 763 | TC Low to ATS High, t me ic Deactivate RTS 40 Note 6 RECEIVE CLOCK PARAMETERS _ 64 RxC Clock Cycle a 100 Notes 15, 3 | 765 AXC Rise Time _ 5 Note 15 T66 AxCFallTime 5 Note 15 67 AXxC High Time @2.7V 36 1000 | Notei5 | 168 FXC Low Time @09V 40 Note15 *All units are in 1-34 ns.a intel 82586 A.C. CHARACTERISTICS (continued) TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION (Continued) Symbol | Parameter | Min | Max | Comments RECEIVE DATA PARAMETERS __ T69 RxD Setup Time 30 Note 1 _| T70 RxD Hold Time 30 Note 1 T71 RxD Rise Time 10 Note 1 T72 RxD Fall Time 10 Note 1 CARRIER SENSE/COLLISION DETECT PARAMETERS 173 CDT Valid to TxC High Ext. Collision 30 Note 12 Detect Setup Time 174 TxC High to CDT liactive. COT Hold Time 20 Note 12 T75 CDT Low to Jamming Start Note 8 T76 CRS Valid to TxC High Ext. Carrier Sense Setup Time 30 Note 12 177 TxC High to CRS iiactive. CRS Hold Time 20 Note 12 T78 CRS Low to Jamm-ng Start Note 9 T79 Jamming Period Note 10 T80 CRS Inactive Setu Tir to RxC High 60 End of Receive Friame T81 CRS Active Hold Time from RxC High 3 INTERFRAME SPACING PARAMETER Ta2 Inter Frame Delay Note 14 *All units are in ns. NOTES: 1. TTL levels 2. Manchester only 3. NAZ only 4. Manchester requires 50% duty cycle 5.1 TTL load + 50 pF 6.1 TTL load + 100 pF 7. Abnormal! end of transmission CTS -xpires before RTS 8. Programmable value: T75 = NGDF - T48 + (12.5 to 23.1) - 148 if collision occurs after preamble NCDFThe collision dete:stion filter :ontiguration value 9. Programmabie value: T78 -- NCSF - T48 + (12.5 '0 23 }) - 1748 NCSFThe carrier sense filter confi juration value TBD is a unction of internal/externa carrer sense bit 10.179 = 32 + T48 11. Programmable value: T82 - NIFS - T48 NIFSthe IFS configuration value *12. To guarantee recagnition an the nest clock 13. Applies 10 TTL levels 14. 82C501 compatible levels, see Fig.:e 34 15. 820501 compatible levels, see Fig.:e 3: 1-3582586 in e A.C. TIMING CHARACTERISTICS Input and Output Waveforms for AC Tests . 1.5 on OK 231246-34 AC testing inputs are driven at 2.4V for a Logic 1 and 0.45 for a Logic 0. Timing measurements are made at 1.5V for both a Logic 1 and 0. TEST POINTS 15 Figure 33. TTL Input/Output Voltage Levels for Timing Measurements HIGH LEVELS MAY VARY WITH Voc 231246-35 Figure 34, TxC Input Voltage Levels for Timing Measurements oov - --- ~~ oav 18 85 231246-36 Figure 35. RxC Input Voltage Levels for Timing Measurements 1-36i ntel . 82586 PW) ISON I _ y eT Tas aia 152 oe eB 7 NL aor Tet Te cat 789 7 _ #4 as ap bee on AL XE XY TN 1S tse weet IP 80232 TN Sh 7d" Sr 0 Ts3 Ts 231246-37 . i LP YY SNS T79 f 778 Ts _. wg f-__.._/] N }-- mt CN a Bt 73 -_ ee Fin 176 ERS. tt WJ. et v7 -- wa OXY NN TSS XXX NSN ANS {MANCHESTER} 231246-38 Figure 36. Transmit and Control and Data Timing T65 66 KW oat 231246-39 Figure 37. RxD Timing Relative to RxC ee | crs =e] T80 | Ta 231246-40 Figure 38. CRS Timing Relative to RxC 1-37