R5432V SERIES 3 to 5 Cells Li-ion Battery Protector IC NO.EA-263-1600711 OUTLINE The R5432V is a high voltage CMOS-based protection IC for overcharge /discharge of rechargeable three-cell / four-cell / fivecell Lithium-ion / Lithium- polymer battery, further include a short circuit and the protection circuits against the excess discharge current and excess charge current. Each of these ICs is composed of eighteen voltage detectors (fourteen for 3cell protection type, sixteen for 4cell protection type), a reference circuit, a delay circuit, a short detector circuit, an oscillator, a counter and a logic circuit. The output of COUT is P-channel open-drain type, and DOUT is CMOS type. If the overcharge voltage or overcharge current is detected by the R5432V, after the preset output delay time, the output of COUT becomes Hi-Z. While the overdischarge voltage or current is detected, after the preset output delay time, the output of DOUT becomes "L". After detecting overcharge voltage, when the cell voltage returns lower than the overcharge released voltage, then overcharge is released and the output of COUT becomes "H". After detecting overcharge current, by disconnecting a charger and connecting a load, then overcharge current is released and the output of COUT becomes "H". After detecting overdischarge voltage, when the cell voltage becomes the released voltage from overdischarge or more, then overdischarge is released and the output of DOUT becomes "H". After detecting overdischarge current and short circuit, by disconnecting the load, the function of the output of DRAIN pin, the external NMOSFET turns on, and VMP pin voltage is pulled down by the resistance connected to GND and released overdischarge current or short and the output of DOUT becomes "H". By forcing a certain voltage to SEL1 and SEL2 pins, the testing time of protection circuits can be short. Specifically, overcharge, discharge, over current delay time can be shortening into approximately 1/80. The R5432V can protect 6-cell or more by connecting 2 pieces of the R5432V in cascade. High side IC's COUT and DOUT must connect to CTLC and CTLD respectively of the low side IC. As a result, the signal of the high side of COUT and DOUT is transmit to the lower side IC, and control FETs for charge and discharge. The R5432V has cell-balance function to solve the unbalance condition of serially connected cells. If cell voltage is beyond the cell balance detector threshold, by the output of the cell balance control pin, the external NMOSFET turns on, and a current path is made, and during charge, charge current is bypassed, otherwise, cell is discharged until the cell voltage becomes the released voltage from cell-balance operation. If the connection between a cell and a protection board is broken, the open-wire condition is detected by the R5432V, and the output of COUT becomes Hi-Z. After detecting the open-wire, when the cell and the protection board is connected again, the open-wire detector is released and the output of COUT becomes "H". FEATURES * Absolute Maximum Rating ............................................... 30V * Supply Current ................................................................. Typ. 12.0A Detector thresholds range and accuracy * Overcharge detector threshold ......................................... 3.6V to 4.5V (5mV step) (n=1, 2, 3, 4, 5) (25mV) * Overdischarge detector threshold .................................... 2.0V to 3.0V (5mVstep) (n=1, 2, 3, 4, 5) (2.5%) * Excess discharge current threshold 1 .............................. 0.1V to 0.3V (10mVstep) (20mV) for BA/BB/BC ver. 0.1V to 0.2V (10mV step) (20mV) for AD/BD ver. * Excess discharge current threshold 2 .............................. 0.45V/0.60V for BA ver. 0.25V to 0.40V for BB/BC ver. 0.25V/0.3V(Vdet3-1+0.1V or more) for AD/BD ver. 1 R5432V NO.EA-263-160711 * Short detector threshold ..................................................... 1.00V for BA ver. 0.75V for BB/BC ver. Vdet3-2 x 1.67 for AD/BD ver. * Excess charge current threshold ........................................ -0.05V (30mV), -0.1V (30mV), -0.2V (30mV), -0.4V (40mV) * Overcharge released voltage.............................................. VDET1n-0.1V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5) * Overdischarge released voltage ......................................... VDET2n+0.2V to 0.7V (100mV steps) (n=1, 2, 3, 4, 5) up to 3.4V * Cell-balance detector threshold .......................................... 3.45V to 4.45V (5mV steps) (n=1, 2, 3, 4, 5) * Cell-balance released voltage ............................................ CBDETn-0.0V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5) Output delay time * * * * * Overcharge detector Output Delay ..................................... 1.0s Overdischarge detector Output Delay ................................ Settable by Ext.Capacitance1 Excess discharge current detector Output Delay 1/2.......... Settable by Ext.Capacitance2 Excess charge current detector Output Delay .................... 8ms Short detector Output Delay ............................................... 300s Functions * * * * 0V-battery charger ........................................... .................. acceptable/unacceptable options Cascade connection ........................................ .................. Available. Refer to the typical application. 3/4/5 cell protection ........................................ .................. Selectable Output Delay Time Shortening Function ............................. By forcing a certain voltage to SEL pin, overcharge, discharge voltage and current is reduced approximately 1/80. Overcharge delay time can be shorten into around 4ms for testing. * Cell-balance function .......................................................... Available * Cell-unbalance condition .................................................... If either of cells detects overcharge and either of cells detects overdischarge, the output of COUT becomes "Hi-Z", the output of DOUT becomes "L". * Overcharge/Overdischarge released condition................... By voltage condition. * Output of COUT/DOUT ...................................................... COUT: VDD source P-channel open drain output. Normal state "H"(VDD), Detected state "Hi-Z". DOUT: 12V regulator source CMOS output. Normal state "H"(12V), Detected state "L". * Open-wire detection ........................................................... Open-wire between VDD, VSS, VCx pin and the pack is supervised. * Small Package.................................................................... SSOP-24 2 R5432V NO.EA-263-160711 BLOCK DIAGRAMS R5432VxxxBA VDD VC1 CB1 VD1-1 CB Circuit-1 Vnochg1 Logic Circuit CTLD CTLC VD2-1 VD1-2 VC2 Regulator Regulator CB2 CB Circuit-2 Logic Circuit Vnochg2 Oscillatpr VD2-2 VD1-3 VC3 CB3 CB Circuit-3 Vnochg3 VD2-3 VD1-4 VC4 CB4 Counter CB Circuit-4 Logic Circuit Vnochg4 VD2-4 Delay VC5 CB5 VMP Short Circuit VD1-5 CB Circuit-5 Vnochg5 VD3-1 COUT VSS VD2-5 odd sw even sw DOUT VD3-2 Logic Circuit T Stop tVDET2 tVDET3 Logic Circuit VD4 Ds Circuit T Start CTLT SEL1 SEL2 SENS CT1 CT2 DRAIN 3 R5432V NO.EA-263-160711 SELECTION GUIDE Product Name R5432Vxxx$ Package Quantity per Reel Pb Free Halogen Free SSOP-24 3000 Yes Yes xxx :Serial Number for the R5432V designating voltages such as overcharge threshold, overcharge released voltage, Cell-balance threshold, Cell-balance released voltage, overdischarge threshold, overdischarge released voltage, overdischarge current1/2, overcharge current, short voltage. $ : Designation of Output delay option. Overcharge Delay time (s) Overdischarge Delay time (ms) Overdischarge Current Delay time1 (ms) A 1.0 3.64xCCT1 (nF) 3.05xCCT2 (nF) B 1.0 3.88xCCT1 (nF) 3.26xCCT2 (nF) *capacitor for CT1: CCT1, capacitor for CT2:CCT2. : Designation of Output delay option. Overcharge Overdischarge Released condition Released condition A Auto Release Auto Release B Auto Release Auto Release C Auto Release Auto Release Auto Release D with hysteresis Auto Release cancellation 4 Overdischarge Current Delay time2 (ms) Overcharge Current Delay time (ms) Short Delay time (s) tVDET31/ 100 tVDET31/ 6 8 8 300 300 0V battery Short detector Charge Threshold Acceptable 1.0V Unacceptable 0.75V Acceptable 0.75V Acceptable VDET32 x 1.67 Open-wire detection Available Available Available Cascade connection Available Available Available Available Available R5432V NO.EA-263-160711 1) Product Code List Code VDET1n VREL1n VCBDn VCBRn VDET2n VREL2n VDET31 VDET32 VSHORT VDET4 (V) *1 (V) *1 (V) *1 (V) *1 (V) *1 (V) *1 (V) (V) (V) (V) R5432V402BA 4.350 4.050 4.200 4.200 2.400 2.700 0.200 0.600 1.000 -0.100 R5432V403BA 3.900 3.800 3.500 3.500 2.500 3.000 0.100 0.600 1.000 -0.100 R5432V404BA 4.250 4.100 4.200 4.200 2.500 3.000 0.200 0.600 1.000 -0.200 R5432V405BA 3.900 3.800 3.650 3.650 2.000 2.300 0.100 0.600 1.000 -0.200 R5432V406BA 3.650 3.550 3.500 3.500 2.500 3.000 0.300 0.600 1.000 -0.200 R5432V407BA 4.200 4.000 3.900 3.900 2.700 2.850 0.200 0.450 1.000 -0.200 R5432V408BA 3.800 3.600 3.450 3.450 2.000 2.300 0.200 0.450 1.000 -0.100 R5432V409BA 4.100 4.000 3.900 3.900 3.000 3.100 0.200 0.600 1.000 -0.200 R5432V410BC 4.200 4.000 4.150 4.150 2.750 2.950 0.100 0.250 0.750 -0.050 R5432V412BA 4.300 4.050 4.200 4.200 2.700 3.000 0.200 0.600 1.000 -0.100 R5432V413BA 4.250 4.100 4.200 4.200 2.500 3.000 0.100 0.600 1.000 -0.100 R5432V416BA 4.200 4.100 4.170 4.170 2.500 3.000 0.200 0.450 1.000 -0.100 R5432V417BC 4.200 4.100 4.180 4.180 2.500 3.000 0.100 0.400 0.750 -0.050 R5432V418BC 4.180 4.080 4.180 4.180 2.500 3.000 0.100 0.400 0.750 -0.050 R5432V419BD 3.900 3.800 3.500 3.500 2.500 3.000 0.100 0.300 0.500 -0.100 R5432V420BD 4.350 4.050 4.200 4.200 2.400 2.700 0.100 0.250 0.418 -0.100 R5432V501BA 3.900 3.700 3.800 3.600 2.000 2.300 0.200 0.600 1.000 -0.200 R5432V502BA 4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.450 1.000 -0.050 R5432V503BB 4.250 4.150 4.150 4.140 2.700 3.000 0.150 0.300 0.750 -0.050 R5432V504BD 4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.250 0.418 -0.050 R5432V505BD 4.250 4.100 4.200 4.190 2.500 3.000 0.100 0.250 0.418 -0.050 R5432V506BD 3.900 3.800 3.650 3.640 2.000 2.300 0.100 0.250 0.418 -0.050 R5432V507BD 4.215 4.100 4.200 4.180 2.800 3.000 0.100 0.250 0.418 -0.100 R5432V508BA 3.800 3.700 3.600 3.580 2.800 2.900 0.200 0.600 1.000 -0.100 R5432V509BD 3.900 3.800 3.650 3.640 2.000 2.300 0.100 0.250 0.418 -0.100 R5432V510BD *1n1,2,3,4,5 3.900 3.800 3.475 3.465 2.000 2.300 0.100 0.250 0.418 -0.100 5 R5432V NO.EA-263-160711 PIN DESCRIPTIONS SSOP-24 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 6 Pin No Symbol Pin Description 1 CTLC COUT control pin 2 CTLD DOUT control pin 3 COUT Output pin of overcharge detection, Pch OPEN DRAIN output 4 VMP Pin for charger negative input 5 DRAIN 6 DOUT 7 SENS Current sense pin 8 CTLT Disconnection detection movement interval setting capacitance pin 9 VSS VSS pin. Ground pin for the IC 10 CT1 tVDET2 setting capacitance connection pin 11 CT2 tVDET3 setting capacitance connection pin 12 SEL1 3cell/4cell/5cell alternative pin1 13 SEL2 3cell/4cell/5cell alternative pin2 14 CB5 CELL5 Cell balance Control pin 15 VC5 Positive terminal pin for Cell5 16 CB4 CELL4 Cell balance Control pin 17 VC4 Positive terminal pin for Cell4 18 CB3 CELL3 Cell balance Control pin 19 VC3 Positive terminal pin for Cell3 20 CB2 CELL2 Cell balance Control pin 21 VC2 Positive terminal pin for Cell2 22 CB1 CELL1 Cell balance Control pin 23 VC1 Positive terminal pin for Cell1 24 VDD VDD pin Release from Excess discharge-current threshold Pin Output pin of overdischarge detection,CMOS output R5432V NO.EA-263-160711 ABSOLUTE MAXIMUM RATINGS Symbol Rating Unit -0.3 to 30 V Positive input pin for Cell1 VC2-0.3 to VC2+6.5 V VC2 Positive input pin for Cell2 VC3-0.3 to VC3+6.5 V VC3 Positive input pin for Cell3 VC4-0.3 to VC4+6.5 V VC4 Positive input pin for Cell4 VC5-0.3 to VC5+6.5 V -0.3 to 6.5 -0.3 to 30.0 V V VDD Input voltage VC1 Item Supply voltage VC5 VMP Positive input pin for Cell5 Charger negative terminal input pin VSEL1 3Cell/4Cell/5Cell alternative pin1 -0.3 to VDD+0.3 V VSEL2 3Cell/4Cell/5Cell alternative pin2 -0.3 to VDD+0.3 V VCTLC COUT control pin -0.3 to VDD+25 -0.3 to 48 V VCTLD DOUT control pin -0.3 to VDD+25 -0.3 to 48 V VSENSE Current sense pin Delay time setting pin1 Delay time setting pin2 Disconnection detection movement interval setting capacitance pin -0.3 to VDD+0.3 V -0.3 to 3.5 V -0.3 to 3.5 V -0.3 to 3.5 V VCT1 VCT2 VCTLT Output voltage VDD-30 to VDD+0.3 V Output pin of overdischarge detection,CMOS output -0.3 to VOH2+0.3 V Release from Excess discharge-current threshold Pin -0.3 to VOH3+0.3 V VCOUT Output pin of overcharge detection,CMOS output VDOUT VDRAIN VCB1 Cell balance Control pin for Cell1 VC2-0.3 to VC2+6.5 V VCB2 Cell balance Control pin for Cell2 VC3-0.3 to VC3+6.5 V VCB3 Cell balance Control pin for Cell3 Cell balance Control pin for Cell4 Cell balance Control pin for Cell5 VC4-0.3 to VC4+6.5 V VC5-0.3 to VC5+6.5 V -0.3 to 6.5 V VCB4 VCB5 dissipation(1) PD Power 770 mW Ta Operating temperature range -40 to 85 C Tstg Storage temperature range -55 to 125 C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safety for both device and system using the device in the field. The functional operations at or over these absolute maximum ratings are not assured. (1) Refer to POWER DISSIPATION for detailed information. 7 R5432V NO.EA-263-160711 ELECTRICAL CHARACTERISTICS * R5432VxxxBA Symbol VDD1 VDET1n VREL1n tVDET1 tVREL1 VCBDn Items Operating input voltage CELLn Overcharge threshold (n=1,2,3,4,5) CELLn Overcharge released Voltage (n=1,2,3,4,5) Output delay of overcharge Output delay of release from overcharge CELLn balance threshold (n=1,2,3,4,5) Conditions VDD-VSS Detect rising edge of supply voltage Detect falling edge of supply voltage VDD=VC1,VCELLn=3.5V (n=2,3,4,5), VCELL1=3.5V4.5V VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V3.5V Min. Typ. 2 VDET1n -0.025 VREL1n -0.050 Max. 25 VDET1n VREL1n VDET1n +0.025 VREL1n +0.050 Unit Circuit V - V A V A 0.7 1.0 1.3 s B 11 16 21 ms B Detect rising edge of supply voltage VCBDn -0.025 VCBDn V C V C V D VCBDn +0.025 Lower of VCBRn +0.050 or VCBDn +0.025 VDET2n x1.025 VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n x0.975 VDET2n VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n x0.975 VREL2n VREL2n x1.025 V D 350 500 650 nA E 1.48 1.85 2.22 V F 89 128 167 ms - 0.7 1.2 1.7 ms G VDET31 -0.020 VDET31 VDET31 +0.020 V H 0.500 0.600 0.700 V I VDET31 x0.50 VDET31 x0.75 VDET31 x.00 V H 350 500 650 nA I 2.0 3.0 4.0 A I 1.23 1.55 1.87 V J 7.3 10.8 14.7 ms - 1.25 1.8 2.4 ms - 0.7 1.2 1.7 ms H Output delay of Excess discharge-current threshold1 Output delay of Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V1.5V VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=1.5V tVDET2=CCT1xVDCT1/ICT1 CCT1=33nF VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V VCELL1=1.5V3.5V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.4V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.7V VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V tVDET31=CCT2xVDCT2/ICT231 CCT2=3.3nF tVDET32=CCT2xVDCT2/ICT232 CCT2=3.3nF Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V ICT1 CT1 charge Current VDCT1 CT1 detector voltage tVDET2 Output delay of overdischarge tVREL2 Output delay of release from overdischarge VDET31 Excess discharge-current threshold1 VDET32 Excess discharge-current Threshold2 VREL3 Output delay of release from Excess discharge-current threshold ICT231 CT2 Charge Current1 ICT232 CT2 Charge Current2 VDCT2 CT2 Charge voltage tVDET31 tVDET32 tVREL3 8 Unless otherwise specified, Ta=25C R5432V NO.EA-263-160711 Symbol Items Vshort Short protection voltage tshort Output Delay of Short protection VDET4 Excess charge-current threshold tVDET4 Output delay of Excess charge-current threshold Conditions VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V2.0V, VMP=4.0V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=-1.0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V-1.0V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V1.0V VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) Min. Typ. Max. Unit Circuit 0.7 1.0 1.7 V K 180 300 550 s K VDET4 -0.030 VDET4 VDET4 +0.030 V L 5 8 11 ms L 0.7 1.2 1.7 ms L VDD -0.3 VDD +0.3 V M tVrel4 Output delay of release from Excess charge-current threshold VIH1 SEL1 pin "H" input voltage VIM1 SEL1 pin "M" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 4.0 VDD/2 -0.5V V M VIL1 SEL1 pin "L" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +1.0 V M VIH2 SEL2 pin "H" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin "M" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 4.0 VDD/2 -0.5V V N VIL2 SEL2 pin "L" input voltage VSS +0.3 V N CTLC1H CTLC pin "H1" input voltage V O CTLC2H CTLC pin "H2" input voltage V O CTLC1L CTLC pin "L" input voltage V O CTLD1H CTLD pin "H1" input voltage V P CTLD2H CTLD pin "H2" input voltage V P CTLD1L CTLD pin "L" input voltage V P VOL2 DOUT Nch ON voltage VOL3 DRAIN Nch ON voltage VOL4 CB1 Nch ON voltage VOL5 VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +0.3 VSS +0.3 VDD +0.3 VSS +0.3 0.1 0.5 V Q 0.1 0.5 V R IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S CB2 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC4 +0.2 VC4 +0.5 V S VOL7 CB4 Nch ON voltage VC5 +0.2 VC5 +0.5 V S VOL8 CB5 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) 0.2 0.5 V S 9 R5432V NO.EA-263-160711 Symbol Items VOH1 COUT Pch ON voltage VVR12 VR 12V output voltage (*1) VOH2 DOUT Pch ON voltage (*1) VOH3 DRAIN Pch ON voltage (*1) Conditions IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS IOH=-5A, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V Min. Typ. VDD -0.5 VDD -0.1 10 12 VVR12 -0.5V Max. Unit Circuit V T V U VVR12 -0.1V V U VVR12 -0.5V VVR12 -0.1V V V 14 IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VC2 -0.5 VC2 -0.3 V W CB3 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W VOH7 CB4 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W VOH8 CB5 Pch ON voltage VC5 -0.5 VC5 -0.3 V W ILCOUT COUT pin off leak current A X VOH4 CB1 Pch ON voltage VOH5 CB2 Pch ON voltage VOH6 ICTLT CTLT Charge Current VDTLT CTLT detector threshold VRTLT CTLT released voltage tLT Disconnection detection Test Interval ISS1 Supply Currnt1 ISS2 Supply Currnt2 IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CCTLTx(VDTLT-VRTLT)/ICTLT CCTLT =3.3F VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) -0.1 145 205 264 nA Y 1.58 2.00 2.42 V Z 0.07 0.13 0.19 V Z 21 30 39 s - 12 30 A a 10 25 A a VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD. RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS) All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. The semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. 10 R5432V NO.EA-263-160711 * R5432VxxxBB/BC Symbol VDD1 VDET1n VREL1n tVDET1 tVREL1 VCBDn Items Operating input voltage CELLn Overcharge threshold (n=1,2,3,4,5) CELLn Overcharge released Voltage (n=1,2,3,4,5) Output delay of overcharge Output delay of release from overcharge CELLn balance threshold (n=1,2,3,4,5) Unless otherwise specified, Ta=25C Conditions Max. 25 VDET1n +0.025 VREL1n +0.050 Unit V Circuit - V A V A 1.0 1.3 s B 11 16 21 ms B Detect rising edge of supply voltage VCBDn -0.025 VCBDn V C V C V D VDD-VSS Detect rising edge of supply voltage Detect falling edge of supply voltage VDD=VC1,VCELLn=3.5V (n=2,3,4,5), VCELL1=3.5V4.5V VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V3.5V Min. 2 VDET1n -0.025 VREL1n -0.050 Typ. VDET1n 0.7 VREL1n VCBDn +0.025 Lower of VCBRn +0.050 or VCBDn +0.025 VDET2n x1.025 VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n x0.975 VDET2n VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n x0.975 VREL2n VREL2n x1.025 V D 350 500 650 nA E 1.48 1.85 2.22 V F 89 128 167 ms - 0.7 1.2 1.7 ms G VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 -0.070 VDET32 VDET32 +0.070 V I VDET31 x0.50 VDET31 x0.75 VDET31 x.00 V H 350 500 650 nA I 2.0 3.0 4.0 A I 1.23 1.55 1.87 V J 7.3 10.8 14.7 ms - 1.25 1.80 2.40 ms - 0.7 1.2 1.7 ms H Output delay of Excess discharge-current threshold1 Output delay of Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V1.5V VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=1.5V tVDET2=CCT1xVDCT1/ICT1 CCT1=33nF VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V VCELL1=1.5V3.5V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.4V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.7V VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V tVDET31=CCT2xVDCT2/ICT231 CCT2=3.3nF tVDET32=CCT2xVDCT2/ICT232 CCT2=3.3nF Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V ICT1 CT1 charge Current VDCT1 CT1 detector voltage tVDET2 Output delay of overdischarge tVREL2 Output delay of release from overdischarge VDET31 Excess discharge-current threshold1 VDET32 Excess discharge-current Threshold2 VREL3 Output delay of release from Excess discharge-current threshold ICT231 CT2 Charge Current1 ICT232 CT2 Charge Current2 VDCT2 CT2 Charge voltage tVDET31 tVDET32 tVREL3 11 R5432V NO.EA-263-160711 Symbol Items Vshort Short protection voltage tshort Output Delay of Short protection VDET4 Excess charge-current threshold tVDET4 Output delay of Excess charge-current threshold tVrel4 Output delay of release from Excess charge-current threshold VIH1 SEL1 pin "H" input voltage VIM1 SEL1 pin "M" input voltage VIL1 SEL1 pin "L" input voltage VIH2 SEL2 pin "H" input voltage VIM2 SEL2 pin "M" input voltage VIL2 SEL2 pin "L" input voltage CTLC1H CTLC pin "H1" input voltage CTLC2H CTLC pin "H2" input voltage CTLC1L CTLC pin "L" input voltage CTLD1H CTLD pin "H1" input voltage CTLD2H CTLD pin "H2" input voltage CTLD1L CTLD pin "L" input voltage 12 VOL2 DOUT Nch ON voltage VOL3 DRAIN Nch ON voltage VOL4 CB1 Nch ON voltage VOL5 Conditions VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V2.0V,VMP=4.0V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=-1.0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V-1.0V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V1.0V VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) Min. Typ. Max. Unit Circuit 0.7 1.0 1.7 V K 180 300 550 s K VDET4 -0.030 VDET4 VDET4 +0.030 V L 5 8 11 ms L 0.7 1.2 1.7 ms L VDD +0.3 V M V M V M V N V N V N V O V O V O V P V P V P VDD -0.3 VDD/2 -0.5V VSS +1.0 VDD +0.3 VDD/2 -0.5V VSS +0.3 4.0 VSS -0.3 VDD -0.3 4.0 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +0.3 VSS +0.3 VDD +0.3 VSS +0.3 0.1 0.5 V Q 0.1 0.5 V R IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S CB2 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) S CB4 Nch ON voltage VC4 +0.5 VC5 +0.5 V VOL7 VC4 +0.2 VC5 +0.2 V S VOL8 CB5 Nch ON voltage 0.2 0.5 V S VOH1 COUT Pch ON voltage V T IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VDD-0.5 VDD-0.1 R5432V NO.EA-263-160711 Symbol Items VVR12 VR 12V output voltage(*1) VOH2 DOUT Pch ON voltage(*1) VOH3 DRAIN Pch ON voltage(*1) Conditions IOH=-5A, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V IOH=-50A, VDD=VC1, VOH4 CB1 Pch ON voltage VOH5 CB2 Pch ON voltage VOH6 CB3 Pch ON voltage VOH7 CB4 Pch ON voltage VOH8 CB5 Pch ON voltage ILCOUT COUT pin off leak current VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) IOH=-50A, VDD=VC1, ICTLT CTLT Charge Current VDTLT CTLT detector threshold VRTLT CTLT released voltage tLT Vnochgn VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) Disconnection detection Test Interval CCTLTx(VDTLT-VRTLT)/ICTLT CCTLT =3.3F CELLn charge inhibit maximum voltage (n=1,2,3,4,5)-for R5432V4xxxB VDD=VC1 ISS1 Supply Currnt1 ISS2 Supply Currnt2 VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) Min. Typ. Max. Unit Circuit 10 12 14 V U VVR12 -0.5V VVR12 -0.1V V U VVR12 -0.5V VVR12 -0.1V V V VC1 -0.5 VC1 -0.3 V W VC2 -0.5 VC2 -0.3 V W VC3 -0.5 VC3 -0.3 V W VC4 -0.5 VC4 -0.3 V W VC5 -0.5 VC5 -0.3 V W A X -0.1 145 205 264 nA Y 1.58 2.00 2.42 V Z 0.07 0.13 0.19 V Z 21 30 39 s - 1.100 V A 12 30 A a 10 25 A a VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD. 13 R5432V NO.EA-263-160711 * R5432VxxxBD Symbol VDD1 VDET1n VREL1n tVDET1 tVREL1 VCBDn Unless otherwise specified, Ta=25C Items Operating input voltage CELLn Overcharge threshold (n=1,2,3,4,5) CELLn Overcharge released Voltage (n=1,2,3,4,5) Output delay of overcharge Output delay of release from overcharge CELLn balance threshold (n=1,2,3,4,5) Conditions VDD-VSS Detect rising edge of supply voltage Detect falling edge of supply voltage VDD=VC1,VCELLn=3.5V (n=2,3,4,5), VCELL1=3.5V4.5V VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V3.5V Min. Typ. Max. Unit Circuit 2 25 V - VDET1n -0.025 VREL1n -0.050 VDET1n +0.025 VREL1n +0.050 V A V A VDET1n VREL1n 0.7 1.0 1.3 s B 11 16 21 ms B Detect rising edge of supply voltage VCBDn -0.025 VCBDn V C V C V D VCBDn +0.025 Lower of VCBRn +0.050 or VCBDn +0.025 VDET2n x1.025 VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n x0.975 VDET2n VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n x0.975 VREL2n VREL2n x1.025 V D 350 500 650 nA E 1.48 1.85 2.22 V F 89 128 167 ms - 0.7 1.2 1.7 ms G VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 -0.055 VDET32 VDET32 +0.055 V I VDET31 x0.50 VDET31 x0.75 VDET31 x.00 V H 350 500 650 nA I 2.0 3.0 4.0 A I 1.23 1.55 1.87 V J 7.3 10.8 14.7 ms - 1.25 1.80 2.40 ms - 0.7 1.2 1.7 ms H Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V CT1 charge Current VDCT1 CT1 detector voltage tVDET2 Output delay of overdischarge tVREL2 Output delay of release from overdischarge VDET31 Excess discharge-current threshold1 VDET32 Excess discharge-current Threshold2 VREL3 Output delay of release from Excess discharge-current threshold ICT231 CT2 Charge Current1 ICT232 CT2 Charge Current2 VDCT2 CT2 Charge voltage tVDET31 tVDET32 tVREL3 14 Output delay of Excess discharge-current threshold1 Output delay of Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V1.5V VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=1.5V tVDET2=CCT1xVDCT1/ICT1 CCT1=33nF VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V VCELL1=1.5V3.5V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.4V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.7V VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V tVDET31=CCT2xVDCT2/ICT231 CCT2=3.3nF tVDET32=CCT2xVDCT2/ICT232 CCT2=3.3nF ICT1 R5432V NO.EA-263-160711 Symbol Items Conditions VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V2.0V, VMP=4.0V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=-1.0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V-1.0V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V1.0V VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) Min. Typ. Max. Unit Circuit Vshort -0.12 VDET32 x1.67 Vshort +0.17 V K 180 300 550 s K VDET4 -0.030 VDET4 VDET4 +0.030 V L 5 8 11 ms L 0.7 1.2 1.7 ms L VDD -0.3 VDD +0.3 V M Vshort Short protection voltage tshort Output Delay of Short protection VDET4 Excess charge-current threshold tVDET4 Output delay of Excess charge-current threshold tVrel4 Output delay of release from Excess charge-current threshold VIH1 SEL1 pin "H" input voltage VIM1 SEL1 pin "M" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 4.0 VDD/2 -0.5V V M VIL1 SEL1 pin "L" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +1.0 V M VIH2 SEL2 pin "H" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin "M" input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 4.0 VDD/2 -0.5V V N VIL2 SEL2 pin "L" input voltage VSS +0.3 V N CTLC1H CTLC pin "H1" input voltage V O CTLC2H CTLC pin "H2" input voltage V O CTLC1L CTLC pin "L" input voltage V O CTLD1H CTLD pin "H1" input voltage V P CTLD2H CTLD pin "H2" input voltage V P CTLD1L CTLD pin "L" input voltage V P VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VOL2 DOUT Nch ON voltage VOL3 DRAIN Nch ON voltage VOL4 CB1 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL5 CB2 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL6 CB3 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL7 CB4 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL8 CB5 Nch ON voltage VOH1 COUT Pch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD -0.5 VDD +0.3 VSS +0.3 VDD +0.3 VSS +0.3 0.1 0.5 V Q 0.1 0.5 V R VC2 +0.2 VC3 +0.2 VC4 +0.2 VC5 +0.2 VC2 +0.5 VC3 +0.5 VC4 +0.5 VC5 +0.5 V S V S V S V S 0.2 0.5 V S V T VDD -0.1 15 R5432V NO.EA-263-160711 Symbol Items VVR12 VR 12V output voltage(*1) VOH2 DOUT Pch ON voltage(*1) VOH3 DRAIN Pch ON voltage(*1) Conditions IOH=-5A, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V Min. Typ. Max. Unit Circuit 10 12 14 V U VVR12 -0.5V VVR12 -0.1V V U VVR12 -0.5V VVR12 -0.1V V V IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VC2 -0.5 VC2 -0.3 V W VOH4 CB1 Pch ON voltage VOH5 CB2 Pch ON voltage VOH6 CB3 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W VOH7 CB4 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W VOH8 CB5 Pch ON voltage VC5 -0.5 VC5 -0.3 V W ILCOUT COUT pin off leak current A X ICTLT CTLT Charge Current VDTLT CTLT detector threshold VRTLT CTLT released voltage tLT Disconnection detection Test Interval ISS1 Supply Currnt1 ISS2 Supply Currnt2 IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CCTLTx(VDTLT-VRTLT)/ICTLT CCTLT =3.3F VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) -0.1 145 205 264 nA Y 1.58 2.00 2.42 V Z 0.07 0.13 0.19 V Z 21 30 39 s - 12 30 A a 10 25 A a VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD. 16 R5432V NO.EA-263-160711 * R5432VxxxAD Symbol VDD1 VDET1n VREL1n tVDET1 tVREL1 VCBDn Unless otherwise specified, Ta=25C Items Operating input voltage CELLn Overcharge threshold (n=1,2,3,4,5) CELLn Overcharge released Voltage (n=1,2,3,4,5) Output delay of overcharge Output delay of release from overcharge CELLn balance threshold (n=1,2,3,4,5) Conditions VDD-VSS Detect rising edge of supply voltage Detect falling edge of supply voltage VDD=VC1,VCELLn=3.5V (n=2,3,4,5), VCELL1=3.5V4.5V VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V3.5V Min. Typ. Max. Unit Circuit 2 25 V - VDET1n -0.025 VREL1n -0.050 VDET1n +0.025 VREL1n +0.050 V A V A VDET1n VREL1n 0.7 1.0 1.3 S B 11 16 21 ms B Detect rising edge of supply voltage VCBDn -0.025 VCBDn V C V C V D VCBDn +0.025 Lower of VCBRn +0.050 or VCBDn +0.025 VDET2n x1.025 VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n x0.975 VDET2n VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n x0.975 VREL2n VREL2n x1.025 V D 350 500 650 nA E 1.48 1.85 2.22 V F 840 1200 1560 ms - 0.7 1.2 1.7 ms G VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 -0.055 VDET32 VDET32 +0.055 V I VDET31 x0.50 VDET31 x0.75 VDET31 x.00 V H 350 500 650 nA I 3.5 5.0 6.5 A I 1.23 1.55 1.87 V J 700 1000 1300 ms - 7 10 13 ms - 0.7 1.2 1.7 ms H Output delay of Excess discharge-current threshold1 Output delay of Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V1.5V VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=1.5V tVDET2=CCT1xVDCT1/ICT1 CCT1=330nF VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V VCELL1=1.5V3.5V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising edge of supply voltage VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.4V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS0.7V VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V tVDET31=CCT2xVDCT2/ICT231 CCT2=330nF tVDET32=CCT2xVDCT2/ICT232 CCT2=330nF Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V ICT1 CT1 charge Current VDCT1 CT1 detector voltage tVDET2 Output delay of overdischarge tVREL2 Output delay of release from overdischarge VDET31 Excess discharge-current threshold1 VDET32 Excess discharge-current Threshold2 VREL3 Output delay of release from Excess discharge-current threshold ICT231 CT2 Charge Current1 ICT232 CT2 Charge Current2 VDCT2 CT2 Charge voltage tVDET31 tVDET32 tVREL3 17 R5432V NO.EA-263-160711 Symbol Items Vshort Short protection voltage tshort Output Delay of Short protection VDET4 Excess charge-current threshold tVDET4 tVrel4 Output delay of Excess charge-current threshold Output delay of release from Excess chargecurrent threshold VIH1 SEL1 pin "H" input voltage VIM1 SEL1 pin "M" input voltage VIL1 SEL1 pin "L" input voltage VIH2 SEL2 pin "H" input voltage VIM2 SEL2 pin "M" input voltage VIL2 SEL2 pin "L" input voltage CTLC1H CTLC pin "H1" input voltage CTLC2H CTLC pin "H2" input voltage CTLC1L CTLC pin "L" input voltage CTLD1H CTLD pin "H1" input voltage CTLD2H CTLD pin "H2" input voltage CTLD1L CTLD pin "L" input voltage 18 Conditions VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=4.0V Detect rising of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V2.0V, VMP=4.0V VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), VMP=-1.0V Detect falling edge of supply voltage VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V-1.0V VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V1.0V VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL2 DOUT Nch ON voltage VOL3 DRAIN Nch ON voltage VOL4 CB1 Nch ON voltage VOL5 CB2 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL6 CB3 Nch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VOL7 CB4 Nch ON voltage VOL8 CB5 Nch ON voltage VOH1 COUT Pch ON voltage IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOL=50A, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS Min. Typ. Max. Unit Circuit Vshort -0.12 VDET32 x1.67 Vshort +0.17 V K 180 300 550 s K VDET4 -0.030 VDET4 VDET4 +0.030 V L 5 8 11 ms L 0.7 1.2 1.7 ms L V M V M V M V N V N V N V O V O V O V P V P V P VDD -0.3 VDD +0.3 VDD/2 -0.5V VSS +0.3 VDD +0.3 VDD/2 -0.5V VSS +0.3 4.0 VSS -0.3 VDD -0.3 4.0 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD +2.0 VDD -0.3 VSS -0.3 VDD -0.5 VDD +0.3 VSS +0.3 VDD +0.3 VSS +0.3 0.1 0.5 V Q 0.1 0.5 V R VC2 +0.2 VC2 +0.5 V S VC3 +0.2 VC4 +0.2 VC5 +0.2 VC3 +0.5 VC4 +0.5 VC5 +0.5 V S V S V S 0.2 0.5 V S V T VDD -0.1 R5432V NO.EA-263-160711 Symbol Items VVR12 VR 12V output voltage(*1) VOH2 DOUT Pch ON voltage(*1) VOH3 DRAIN Pch ON voltage(*1) Conditions IOH=-5A, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS IOH=-50A, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V Min. Typ. Max. Unit Circuit 10 12 14 V U VVR12 -0.5V VVR12 -0.1V V U VVR12 -0.5V VVR12 -0.1V V V IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VC2 -0.5 VC2 -0.3 V W VOH4 CB1 Pch ON voltage VOH5 CB2 Pch ON voltage VOH6 CB3 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W VOH7 CB4 Pch ON voltage IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W VOH8 CB5 Pch ON voltage VC5 -0.5 VC5 -0.3 V W ILCOUT COUT pin off leak current A X ICTLT CTLT Charge Current VDTLT CTLT detector threshold VRTLT CTLT released voltage tLT Disconnection detection Test Interval ISS1 Supply Currnt1 ISS2 Supply Currnt2 IOH=-50A, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CCTLTx(VDTLT-VRTLT)/ICTLT CCTLT =3.3F VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) -0.1 145 205 264 nA Y 1.58 2.00 2.42 V Z 0.07 0.13 0.19 V Z 21 30 39 s - 12 30 A a 10 25 A a VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD. 19 R5432V NO.EA-263-160711 OPERATION * VDET1n / Overcharge Detectors (n=1, 2, 3, 4, 5) While the cell is charged, the voltage between VC1 pin and VC2 pin (voltage of the Cell-1), the voltage between VC2 pin and VC3 pin (voltage of the Cell-2), the voltage between VC3 pin and VC4 pin (voltage of the Cell-3), the voltage of VC4 pin and VC5 pin (voltage of Cell-4), and the voltage between VC5 pin and VSS pin (voltage of the Cell-5) are supervised. If at least one of the cells' voltage becomes equal or more than the overcharge detector threshold, the overcharge is detected, and COUT pin connected to an external pull down resistance outputs "Hi-Z", and by turning off the external N-channel MOSFET by the pulldown resister, charge cycle stops. BA/BB/BC ver.: To reset the overcharge and make the COUT pin level to "H" again after detecting overcharge, in such condition that a time when all the cells' voltages become lower than the overcharge released voltage. Then, the output voltage of COUT pin becomes "H", and it makes an external N-channel MOSFET turn on, and charge cycle is available. The overcharge detectors have hysteresis. AD/BD ver.: To reset the overcharge, when all the cell voltage become lower than the released voltage from overcharge, COUT pin becomes "H", charge is acceptable. After detecting overcharge, by connecting a load, and when all the cell voltage becomes lower than the overcharge voltage detector threshold, COUT voltage becomes "H" and charge will be possible. Internal fixed output delay times for overcharge detection and release from overcharge exist. Even if one of cells' voltage keeps its level more than the overcharge detector threshold, and the output delay time passes, overcharge voltage is detected. Even if the voltage of each cell becomes equal or higher than VDET1 if these voltages would be back to be lower than the overcharge detector threshold within the output delay time, the overcharge is not detected. Besides, after detecting overcharge, each cell voltage is lower than the overcharge detector released voltage, even if just one of cells' voltage becomes equal or more than the overcharge released voltage within the released output delay time, overcharge is not released. The output type of the COUT pin is P-channel open drain and "H" level of COUT pin is VDD pin voltage. * VDET2n / Overdischarge Detectors (n=1, 2, 3, 4, 5) While the cells are discharged, the voltage between VC1 pin and VC2 pin (the voltage of Cell-1), the voltage between VC2 pin and VC3 pin (Cell-2 voltage), the voltage between VC3 pin and VC4 pin (Cell-3 voltage), the voltage between VC4 pin and VC5 pin (Cell-4 voltage), and the voltage between VC5 pin and Vss pin (Cell-5 voltage) are supervised. If at least one of the cells' voltage becomes equal or less than the overdischarge detector threshold, the overdischarge is detected and discharge stops by the external discharge control N-channel MOSFET turning off with the DOUT pin being at "L". The condition to release overdischarge voltage detector is that after detecting overdischarge voltage, all the cells' voltage becomes higher than the overdischarge released voltage, DOUT pin becomes "H" level, and by turning on the external N-channel MOSFET, discharge becomes possible. The overdischarge detectors have hysteresis. The output delay time for overdischarge detect is set with an external capacitor CCT1 connected to CT1 pin. If at least one of the cells' voltage becomes down to equal or lower than the overdischarge detector threshold, and the voltage of each cell would be back to higher than the overdischarge detector threshold within the output delay time, the overdischarge is not detected. The output delay time for release from overdischarge is also set internally. After detecting overdischarge, supply current would be reduced and be into standby by halting unnecessary circuits and consumption current of the IC itself is made as small as possible. When a cell voltage equals to zero, if the voltage of each cell is lower than the charge inhibit maximum voltage, charge is not acceptable. All the cell voltages are higher than the charge inhibit maximum voltage, COUT pin becomes "H" and the IC allows the system to charge. The output type of DOUT pin is CMOS having "H" level around 12V of the internal regulator and "L" level of VSS. 20 R5432V NO.EA-263-160711 * VDET3-n (n=1, 2) /Excess discharge-current Detector, Short Circuit Protector When the charge and discharge is acceptable, SENS pin voltage is supervised, if the load is short and SENS pin voltage becomes equal or more than excess discharge current threshold, and equal or less than the short detector threshold, the status becomes excess discharge current detected condition. If SENS pin voltage becomes equal or more than the short circuit detector threshold, the status becomes short circuit detected, then DOUT pin outputs "L" and by turning off the external MOSFET, the IC prevents the circuit from flowing large current. The excess discharge current detector has two thresholds, and each threshold has the output delay time. In terms of the output delay times, the delay time for the excess discharge current detector 2 is set shorter than the excess discharge current 1. The output delay times for the excess discharge-current detectors are set by an external capacitor CCT2 connected to CT2 pin. A quick recovery of SENS pin level from a value between the excess discharge current detector and the short circuit detector threshold within the delay time, may keep the status as before excess discharge current detected. Output delay time for the release from excess discharge-current detection is also set internally. When the short circuit protector is enabled, the delay time exists as well as other protection circuits. Between the drain of the external FET connected to DRAIN pin, and the drain of an external FET connected to COUT and DOUT, an external resistor should be mounted to release from overdischarge. After an excess discharge-current or short circuit protection is detected, an external FET connected to DRAIN pin turns on and the resistance of release from the excess-discharge current is connected to VSS. After detecting the excess discharge current or short circuit, load is removed and opened, VMP pin level is connected to the VSS pin level, through the pulled down resistor for release from excess discharge, and when the VMP pin becomes equal or less than VREL3, the circuit is released from excess discharge or short automatically. When the excess-discharge current is released, the external FET connected to DRAIN pin turns off and resisters for the release from excess-discharge current status is separated from VSS. * VDET4/ Excess charge-current detector When the battery pack is chargeable and discharge is also possible, VDET4 senses SENS pin voltage. For example, in case that a battery pack is charged by an inappropriate charger, excess current flows, then the voltage of SENS pin becomes equal or less than the excess charge-current detector threshold, then the output of COUT pin becomes "Hi-Z", and by turning off the external N-channel MOSFET with the pull-down resister, flowing excess current in the circuit is prevented. Output delay of the excess charge current is internally fixed. Even the voltage level of SENS pin becomes equal or lower than the excess charge-current detector threshold, if the voltage becomes higher than the excess charge current threshold within the delay time, the excess charge current is not detected. Output delay for the release from excess charge current exists as well as other protection circuits. VDET4 can be released by disconnecting a charger and connecting a load and when the VMP pin voltage becomes equal or more than VREL3. * Operation against cell unbalance If one of the cells detects overcharge and either of the cells detects overdischarge, both outputs of COUT and DOUT become "L". * CTLC/CTLD pin If the ICs are stacked and function with two chips, by connecting COUT and CTLC, and connecting DOUT and CTLD shown as in the example circuit (10-cell protection), overcharge, overdischarge, open-wire state can be transferred. If stacked connection is unnecessary, CTLC/CTLD pins must be set at VSS voltage level. If CTLC/CTLD pins are in the range of VSS 0.3V, or larger than VDD+2.0V, the IC operates in normal way. By forcing VDD voltage level (between VDD-0.3V and VDD+0.3V) to CTLC pin, the output of COUT connected an external pulldown resister can be forcibly set to "L". However, if short circuit is detected, the output of COUT cannot be made "L". By forcing VDD voltage level (between VDD-1.0V and VDD+3.0V) to CTLD pin, the output of DOUT can be forcibly set to "L". 21 R5432V NO.EA-263-160711 If the voltage in the range from Vss+0.3V to VDD-0.3V is forced to the CTLC/CTLD pin, the operation may change by the voltage between VDD and VSS. The voltage in the range from VSS + 0.3V to VDD-0.3V should not be forced to CTLC/CTLD continuously. CTL pin input and outputs of COUT and DOUT * CTLC/CTLD pin input COUT/DOUT external FET equal or more than VDD+2.0 Normal Operation VDD-0.3V to VDD+0.3V Forced off VSS-0.3 to VSS+0.3 Normal Operation Open, other than the above Indefinite SEL1, SEL2 pin SEL1 and SEL2 pins are used as switch over 3-cell protector, 4-cell protector and 5-cell protector. If 4-cell protection is selected, by forcing VSS voltage level to SEL1 pin and forcing VDD voltage level to SEL2 pin, the operation of 5th cell's protection circuit, the signal is shut down, therefore, even if the VC5 is shortened to GND, overdischarge is not detected and operates as a 4-cell protector IC. To select 3-cell protection mode, by forcing VDD voltage level to SEL1 pin, VSS voltage level to SEL2 pin, the operation of 5th cell and 4th cell stop, and the signal is cut off. Therefore, if VC4, VC5 and VSS are shorted, overdischarge is not detected and operates as a 3-cell protector IC. SELn pins must be set as VDD voltage or VSS voltage level. Depending on the combination of SEL1 pin and SEL2 pin input, delay time shortening function mode 1 (down to 1/100 delay) or delay time shortening function mode 2 (overcharge detector threshold delay time is shortened into 4ms) is realized. Middle voltage of the table below means in the range from 4.0V to VDD/2-0.5V. SEL1 and SEL2 pin input combination, and the operation mode * SEL1 pin input SEL2 pin input Operation Mode High High 5-cell protector Low High 4-cell protector High Low 3-cell protector Low Low Delay shortening mode 1 for 5-cell protector Low Middle Delay shortening mode 1 for 4-cell protector Middle Low Delay shortening mode 1 for 3-cell protector Middle Middle Delay shortening mode 2 for 5-cell protector Middle High Delay shortening mode 2 for 4-cell protector High Middle Delay shortening mode 2 for 3-cell protector CT1, CT2 pin CT1 and CT2 pins are used for setting the output delay time of overdischarge (tVDET2), the excess discharge current 1 (tVDET31), and the excess discharge current 2 (tVDET32) by connecting external capacitors CCT1 and CCT2. tVDET2 can be set with CT1 pin. tVDET31 and tVDET32 can be set with CT2 pin. (1) tVDET2 external capacitor CCT1 setting tVDET2 can be set as in the next formula. 22 Delay time code : A tVDET2(msec) = 3.64 x CCT1(nF) Delay time code : B tVDET2(msec) = 3.88 x CCT1(nF) R5432V NO.EA-263-160711 (2) tVDET31 and tVDET32 external capacitor CCT2 setting tVDET31 and tVDET32 can be set as in the next formulas. Delay time code : A tVDET31(msec) = 3.05 x CCT2(nF) tVDET32(msec) = tVDET31/100 Delay time code : B tVDET31(msec) = 3.26 x CCT2(nF) tVDET32(msec) = tVDET31/6 * Cell balance function CB circuit-n (n=1,2,3,4,5) While a battery is being charged, and the cell voltage is beyond the cell balance voltage VCBDn (n=1,2,3,4,5) , against the cell which becomes equal or more than the cell balance voltage VCBDn, the output of CBn pin (n=1,2,3,4,5) becomes "H" and an external N-channel transistor for cell balance turns on, and discharge path is connected in parallel with the cell and charge current is reduced. When the cell voltage becomes equal or less than the cell balance released voltage VCBRn (n=1,2,3,4,5), then cell balance function is released and the output of CBn pin (n=1,2,3,4,5) becomes "L". The resister used for the discharge path, absolute ratings must be cared. If the cell balance function is unnecessary, CBn pin must be left open. Open-wire Detector Function Open-wire detect of VDD (VC1) and VSS for 5-cell protector If VDD line is cut, the voltage between VC1 and VC2 is less than 0V. If VSS line is cut, the voltage between VC5 and VSS is less than 0V. The voltage is detected by the 0V-detector circuit. If open-wire is detected, the P-channel open drain of the COUT turns off. * Open-wire detector for VC2, VC3, VC4, VC5 for 5-cell protection When using the 5-cell protection, the voltage of VDD (= VC1) becomes lower than VC2 voltage if the connection between the battery and VDD (= VC1) is open. And, the voltage of VSS becomes higher than VC5 voltage if the connection between the battery and VSS is open. The voltage variation is detected as "Open-wire". When the open-wire is detected, the P-channel open drain of the COUT turns off. In case of the 3.3F capacitor is attached to the CTLT pin, open-wire detector operates every 30 seconds. The built in switch of VC1, VC3, VC5 cell, and the switch attached to the VC2 and VC4 turn on alternatively by the even_sw and the odd_sw signal. The internal impedance of the cell whose switch turns on becomes low for about 1.2 seconds by the low resistance connected to the switch. If the wire is not broken, the capacitor of the CTLT is discharged and the next cycle starts for checking. While the wire is broken, the difference of the internal impedance of the IC generated by the switch's tuning on makes VC shift and detected by the comparator for VDET1. If the open-wire is detected and the condition continues for about 4ms, then even_sw and odd_sw turn off and the capacitor of CTLT is discharged and the P-channel open drain of the COUT turns off. While the overdischarge voltage is detected, the open-wire of VC2, VC3, VC4 and VC5 does not operate. * Open-wire detector for VDD (VC1) and VSS for 10-cell protection If the ICs are connected in cascade, the VDD of the high side IC and VSS (VSS2) of the low side IC, the open-wire detector is able to work as well as 5-cell protection type. As for the VSS (VSS1) of high side IC and VDD (VDD2) of low side IC, if they are connected with common one wire from the battery, and if the wire is broken, two lines, VSS1 and VDD2's wire are broken, as a result, open-wire may not be able to be detected correctly. As for the VSS1 and VDD2, connect with two wires so that either VSS1 or VDD2 is connected to the battery, and by the pull-down 23 R5432V NO.EA-263-160711 resistance of COUT of high side is connected to the VDD2 of the low side IC, if either of VSS1 or VDD2 breaks the wire, the openwire detector is able to operate. Refer to the typical application circuit. (10-cell, cell-balance, open-wire detector are in use.) *Limitation of the open-wire detector for VC2, VC3, VC4, VC5. If the open-wire detecting function is necessary, confirm the limitations below; External components must be CCTLT=3.3F CCT1 range: from 0.47F to 1.0F CVCx=0.1F Even if the protection IC does not detect overdischarge, if the cell voltage is low, depending on the distribution of the ICs, cell balance state, the operating environment, the characteristics of the external components, open-wire function may not operate correctly. During the delay time of the overcharge voltage, if the open-wire is detected, the overcharge detect operation is once cancelled, and the open-wire operation will be dominant. During the open-wire detection, even if the cell voltage becomes equal or more than the overcharge detector threshold, overcharge is not detected. In this case, after detecting open-wire operation, if the cell voltage is still equal or more than the overcharge detector threshold, overcharge detector operation starts again. For this reason, overcharge detector output delay time may longer than 1s. (Refer to the timing chart.) During the overdischarge delay time, if the open-wire detector's operation starts, the overdischarge detector's operation is once cancelled and the open-wire operation will be dominant. During the open-wire, detector's operation is active, even if the cell voltage becomes equal or less than the overdischarge detector threshold, the overdischarge detector does not start. In this case, after detecting open-wire operation, if the cell voltage is still equal or less than the overdischarge detector threshold, overdischarge detector operation starts again. For this reason, the output delay time of overdischarge detector may be longer than the preset value. (Refer to the timing chart.) Charge Inhibit Detector Circuit Vnochg-n (n-1,2,3,4,5) In the R5432VxxxBB, for each cell, charge inhibit detector is built-in. If either of cells' voltage is lower than the charge inhibit voltage, when a charger is connected to the battery pack, charge inhibit is detected and COUT with external pull-down becomes "Hi-Z" and an external MOSFET turns off by the pull-down resistance and charge stops. When the charge inhibit is detected, the cell voltage which is inhibit charge is equal or lower than the overdischarge detector threshold, therefore the output of COUT becomes "Hi-Z", and the output of DOUT becomes "L", and both external FETs turn off. 24 R5432V NO.EA-263-160711 TIMING CHART * Overcharge, Excess charge current V C1-V C2 VDET11 VREL11 t V C2-V C3 VDET12 VREL12 t V C3-V C4 VDET13 VREL13 t V C4-V C5 VDET14 VREL14 t V C5-V s s VDET14 VREL14 t SENS VDET31 VSS VDET4 t VM P VDET31 VSS VDET4 C OUT t VDD tVDET1 tVDET1 tVDET4 tVREL1 tVREL1 tVREL4 VMP t Cha rg e/ D i s cha rg e current charge 0 t discharge connect charger connect load connect charger connect load open connect charger charger open & connect load 25 R5432V NO.EA-263-160711 * Overdischarge, Excess discharge current1/2, Short detector V C1-V C2 VREL21 VDET21 t V C2-V C3 VREL22 VDET22 t V C3-V C4 VREL23 VDET23 t V C4-VC5 VREL24 VDET24 t V C5-Vss VREL24 VDET24 t SENS Vshort VDET3-2 VDET3-1 VSS VDET4 t VM P VSS DOUT VR12V tVDET31 tVDET21 t tshort tVDET32 tVDET21 tVREL21 tVREL21 tVREL3 tVREL3 tVREL3 VSS t Cha rg e/ D i s cha rg e current charge 0 discharge t connect load 26 connect charger connect load connect open charger connect connect connect open load open load load open R5432V NO.EA-263-160711 CELL BALANCE OPERATION In the case that CELL1 operates CELL balance V C1-V C2 VDET11 CBDET1 CBREL1 VREL11 t C B1 - VC 2 (Vo lt age diffe r e n c e ) Cell balance operation t C OUT VDD tVDET1 Over charge state Cha rg e/ D i s cha rg e current t Charge current 0 t Discharge current charge current charge current bypass current bypass current discharge discharge current + current bypass current idle 27 R5432V NO.EA-263-160711 Balance operation with CELL1 and CELL2 C e llx vo lt age VDET1x CBDETx CBRELx C e ll1 VREL1x C e ll2 t C Bx o u t pu t C B1 o pe r at in g C B2 o pe r at in g t C OUT o u t pu t VDD tVDET1 Over charge state C h ar ge / Disc h ar ge current t Charge current 0 t Discharge current C e ll1 C e ll2 28 charger charger charger - bypass charger - bypass bypass bypass idle idle R5432V NO.EA-263-160711 * Open-wire Detection Open-wire detector's operation of VC2, VC3, VC4, and VC5 for 5-cell protector In case of the 3.3F capacitor is attached to the CTLT pin, open-wire detection operates every 30 seconds. The built in switch of VC1, VC3, VC5 cell, and the switch attached to the VC2 and VC4 turn on alternatively by the even_sw and the odd_sw signal. The internal impedance of the cell whose switch turns on becomes low for about 1.2 seconds by the low resistance connected to the switch in serial. If the wire is not open, the capacitor of the CTLT is discharged and the next cycle starts for checking. While the wire is open, the difference of the internal impedance of the IC generated by the switch's tuning on makes VC shift and detected by the comparator for VDET1. If the open-wire is detected and the condition continues for about 4ms, then even_sw and odd_sw turn off and the capacitor of CTLT is discharged and the Pchannel open drain of the COUT turns off. While the overdischarge voltage is detected, the open-wire of VC2, VC3, VC4 and VC5 does not operate. The timing chart of open-wire of VC2, VC3, VC4, VC5 is shown below: 30seconds (CTLT = 3.3F) CTLT Pin 0V 1.2seconds (CTLT = 3.3F) odd_sw (IC Internal signal) even_sw (IC Internal signal VC3, VC5 open-wire VC2, VC4 open-wire VC3, VC5 open-wire COUT Output (VC3 at open-wire At VC3 at Open-wire VDET1detection level 1) 0V VC3 Voltage Open-wire 1) The change of VC is not always increasing. Depending on the cell balance or the internal impedance, the VC increases or decreases. 29 R5432V NO.EA-263-160711 * Overcharge detector operation and Open-wire detector operation The output delay time of overcharge is normally set at 1s, however, the effect of the open-wire detector, the output delay time may be longer than 1s. Case 1: During the operation of detecting overcharge, if the open-wire is detected, once the operation of the overcharge detector is cancelled, and after detecting the open-wire, the operation of the overcharge detector starts again. Case 2: During the operation of the open-wire detector, if the cell voltage becomes more than the overcharge detector threshold, after detecting the open-wire, the operation of the overcharge detector starts. The timing chart shown below is for the operation of the case 1. When the overcharge is detected, internal node "vd1" becomes "H", then, if the open-wire is detected, the internal node "It_en" becomes "H", then "vd1" signal returns to "L". After the openwire detector is released, then "It_en" returns to "L", then the "vd1" becomes "H", and overcharge detector's function restar. CTLT tLT t VCELLn (n=1,2,3,4, 5) VDET1n t lt_en (internal signal) Check Open-wire t vd1 (internal signal) BtVDET1 A B C tVDET1 t COUT H L t Open-wire test operation starts, overcharge detector's operation is cancelled. Overcharge detector's maximum output delay : Max_tVDET1 = BCtVDET1. 30 R5432V NO.EA-263-160711 * Overdischarge operation and disconnection detector operation The output delay time of the overcharge detector can be set by an external capacitor, but the delay time might be longer than the present value due to the open-wire detector's operation. 1. During the operation of detecting overdischarge, if the open-wire is detected, once the operation of the over discharge detector is cancelled, and after detecting the open-wire is detected, once the operation of the 2. Overdischarge can not be detected during disconnection detection. It can operate after disconnection detect. The timing chart which start to detect disconnect during overdischarge is displayed as follows. The internal signal "vd1" become "H" after it is equal or less than overdischarge threshold. It comes back "L" after which is the detecting disconnection internal signal become "H". "vd1" become "H" after "It_en" comes back "L". . Overdischarge can be detected. CTLT tLT t VCELLn (n=1, 2, 3, 4, 5) VDET2n t lt_en (internal signal) Check Open-wire t vd2 (internal signal) BtVDET2 A B C tVDET2 t DOUT H L t Overcharge detecting is cancelled, after operating disconnection test. So max output of overcharge delay : Max_tVDET2 = BCtVDET2 31 R5432V NO.EA-263-160711 TYPICAL APPLICATION AND TECHNICAL NOTES (R5432VxxxBA) * Circuit example (for -5cell protection, detecting disconnection, at operating cell-balance function) RVDD RVC1 CVDD VDD VC1 Cell1 RCB1 CB1 RVC2 CVC1 VC2 Cell2 RCB2 RVC3 ZD1 Cell3 CB2 CVC2 VC3 RCB3 CB3 RVC4 CVC3 RCB4 SEL2 SEL1 CB4 RVC5 CVC4 VMP VC5 Cell5 VSS CTLC VC4 Cell4 VSS CTLD Protect IC Cout DRAIN RCB5 CB5 CCT1 RVMP SENS VSS CT1 RCO1 Dout CVC5 RSE CT2 CCT2 RCO2 CTLT CCTLT RSENS RDRAIN When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. 32 R5432V NO.EA-263-160711 * Circuit example (for 4cell protection, detecting disconnection, at not operating cell-balance function) RVDD RVC1 CVDD VDD VC1 Cell1 RCB1 CB1 RVC2 CVC1 VC2 Cell2 RCB2 RVC3 ZD1 Cell3 CB2 CVC2 VC3 RCB3 CB3 RVC4 CVC3 RCB4 VSS CTLC VC4 Cell4 VSS CTLD Protect IC SEL2 VSS SEL1 CB4 CVC4 VMP VC5 Cout DRAIN CB5 CCT1 RVMP SENS VSS CT1 RCO1 Dout RSE CT2 RCO2 CTLT CCT2 RSENS RDRAIN When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. 33 R5432V NO.EA-263-160711 * Circuit example (for 3cell, detecting disconnection, at not operating cell-balance function) RVDD RVC1 CVDD VDD VC1 Cell1 CB1 RVC2 CVC1 VC2 Cell2 ZD1 CB2 RVC3 CVC2 VC3 Cell3 CB3 CVC3 VSS CTLD Protect IC VC4 CTLC VSS SEL2 VSS SEL1 CB4 VMP VC5 Cout DRAIN CB5 CCT1 RVMP SENS VSS CT1 RCO1 Dout RSE CT2 CCT2 RCO2 CTLT CCTLT RSENS RDRAIN When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. 34 R5432V NO.EA-263-160711 * Circuit example (for 7cell, detecting disconnection, at operating cell-balance function) RVDD1 RVC1 CVDD1 VDD VC1 Cell1 RCB1 CB1 RVC2 CVC1 VC2 Cell2 RCB2 ZD1 Cell3 CB2 RVC3 CVC2 VC3 RCB3 CB3 RVC4 CVC3 CTLD Protect IC CTLC VC4 SEL2 VSS SEL1 CB4 VMP VC5 Cout DRAIN CB5 Dout SENS VSS CT1 CT2 CTLT CCT11 CCTLT1 RUCO RVDD2 RVC6 CVDD2 VDD VC1 Cell4 RCB6 CB1 RVC7 CVC6 VC2 Cell5 RCB7 CB2 RVC8 ZD2 CVC7 VC3 RCTLD Cell6 RCB8 CB3 RVC9 CVC8 CTLD Protect IC CTLC RCTLC VC4 Cell7 RCB9 SEL2 VSS SEL1 CB4 CVC9 VMP VC5 Cout DRAIN CB5 RVMP SENS VSS RSE CT1 CCT12 RCO1 Dout CT2 CCT22 RCO2 CTLT CCTLT2 RSENS RDRAIN If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. 35 R5432V NO.EA-263-160711 Circuit example (for 10cell, detecting open-wire, with cell-balance function) RVDD1 RVC1 CVDD1 VDD VC1 Cell1 RCB1 CB1 RVC2 CVC1 VC2 Cell2 RCB2 ZD1 Cell3 CB2 RVC3 CVC2 VC3 RCB3 CB3 RVC4 CVC3 CTLD Protect IC CTLC VC4 Cell4 RCB4 SEL2 SEL1 CB4 RVC5 CVC4 VMP VC5 Cell5 Cout DRAIN RCB5 CB5 Dout CVC5 SENS VSS CT1 CT2 CTLT CCT11 CCTLT1 RUCO RVDD2 RVC6 CVDD2 VDD VC1 Cell1 RCB6 CB1 RVC7 CVC6 VC2 Cell2 RCB7 CB2 RVC8 ZD2 CVC7 VC3 RCTLD Cell3 RCB8 CB3 RVC9 CVC8 CTLD Protect IC CTLC RCTLC VC4 Cell4 RCB9 SEL2 SEL1 CB4 RVC10 CVC9 VMP VC5 Cell5 Cout DRAIN RCB10 CB5 RVMP SENS VSS RSE CT1 CCT12 RCO1 Dout CVC10 CT2 CCT22 RCO2 CTLT CCTLT2 RSENS RDRAIN If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. 36 R5432V NO.EA-263-160711 * Circuit example (for 10-cell protection with cell-balance, open-wire, overcharge hysteresis cancellation: AD/BD ver.) RVDD1 RVC1 CVDD1 VDD VC1 Cell1 RCB1 CB1 RVC2 CVC1 VC2 Cell2 RCB2 RVC3 ZD1 Cell3 ROP MOP CB2 CVC2 VC3 RCB3 CB3 RVC4 CVC3 CTLC VC4 Cell4 RCB4 SEL2 SEL1 CB4 RVC5 CVC4 VMP VC5 Cell5 ROP CTLD Protect IC Cout DRAIN RCB5 CB5 Dout CVC5 SENS VSS ROP CT1 CT2 CTLT CCT11 CCTLT1 RVDD2 RVC6 RUCO CVDD2 VDD VC1 Cell1 RCB6 ROP MOP CB1 RVC7 CVC6 VC2 ROP Cell2 RCB7 RVC8 ZD2 CVC7 VC3 RCTLD Cell3 RCB8 CB3 RVC9 CVC8 RCB9 CTLC RCTLC MOP1 SEL2 ROP1 SEL1 CVC9 VMP VC5 Cell5 QOP1 Protect IC CB4 RVC10 ROP CTLD VC4 Cell4 ROP MOP CB2 Cout DRAIN RCB10 CB5 RVMP SENS VSS RSE CT1 CCT12 RCO1 Dout CVC10 CT2 CCT22 RCO2 CTLT CCTLT2 RSENS RDRAIN If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. 37 R5432V NO.EA-263-160711 * External parts ratings Symbol RVDD RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 RSENS RSE RDRAIN RCO1 RCO2 RVMP RCTLC RCTLD RUCO CVDD CVC1 CVC2 CVC3 CVC4 CVC5 CCT1 CCT2 CCTLT ZD1 ROP1 ROP2 ROP3 ROP4 ROP5 ROP6 ROP7 MOP1 MOP2 MOP3 MOP4 QOP1 Typ. 330 330 330 330 330 330 100 100 100 100 100 100 10 5 1 2 10 1 1 3 1 0.1 0.1 0.1 0.1 0.1 0.47 0.0033 3.3 30 10 10 10 10 10 20 10 Unit m k M M M M k k M F F F F F F F F F V k M M M M M M Range 330 to 1000 330 to 1000 330 to 1000 330 to 1000 330 to 1000 330 to 1000 40 or more 40 or more 40 or more 40 or more 40 or more 1.0 or more 1 to 10 5 5 5 0.01 to 10 1 to 10 1 to 10 0.1 to 10 0.1 to 1 0.1 0.1 0.1 0.1 0.1 0.01 to 1.0 0.0022 or more 3.3 30 or less 10 or more 5 or more 5 or more 5 or more 5 or more 10 or more 5 or more Remarks 1 2 2 2 2 2 3 3 3 3 3 It is determined by the value of over current 4 5 RDRAIN<VDET31x(RCO1+RCO2)/50 5 5 6 7 1 2 2 2 2 2 8 9 10 11 Input resistance of QOP1 Consider the Voltage rating of VGS and VDS Consider the Voltage rating of VGS and VDS Consider the Voltage rating of VGS and VDS Consider the Voltage rating of VGS and VDS Consider the Voltage rating of VGS and VDS Please refer to the external circuits of next page for "" of remarks Please confirm "Precautions before Use". 38 R5432V NO.EA-263-160711 Technical Notes on External Circuits and Components *1) The voltage fluctuation is stabilized with RVDD and CVDD. If a small RVDD is set, in the case of the large transient may happen to the cell voltage, by the flowing current, the IC may be unstable. If a large RVDD is set, by the consumption current of the IC itself, the voltage difference between VDD pin and VC1 pin is generated, and unexpected operation may result. Therefore, the appropriate value range of RVDD is from 330 to 1k. To make a stable operation of the IC, the appropriate value range of CVDD is from 0.1F to 1.0F. *2) RVC1 to RVC10, CVC1 to CVC10 stabilize the voltage fluctuation. If large RVC1 to RVC10 is set, the detector threshold will be high because of the internal conduction current of the IC. The operation error of open-wire detector function may happen easily by the distribution of the ICs or environment. If small RVC1 to RVC10 is set, the effect by noise will be large. Therefore the appropriate value range of RVC1 to RVC10 is from 330 to 1k. To make stable operation, use 0.1F as CVC1 to CVC10. *3) When the cell balance function is necessary, RCB1 to RCB10 must be chosen carefully with considering the bypass current, and consumption power by the bypass current, and the external MOSFET. Especially, if a small resistance (to set the large bypass current) is set, fully evaluation is necessary. If a large resistance (to set the small bypass current) is set, the time for cell balance will be long. *4) When the cascade connection is used, if short circuit is happened, by the short current and the RSENS enlarges the voltage, and as a result, if the voltage of SENS pin becomes larger than the VDD of the IC, during the short circuit output delay time, the current flows into SENS pin. Therefore, if a small RSE is set, a large current may flow into SENS pin. If a large RSE is set, the overcurrent detector threshold may shift. Therefore the appropriate value is around 10k. *5) Choose appropriate values for RDRAIN, RCO1, and RCO2 to satisfy the next formula, otherwise, the release from excess discharge current and short may be impossible. RDRAIN<VDET31x(RCO1+RCO2)/50 If small RCO1 or RCO2 is set, when the output of COUT is "H", the consumption current of protection circuit board increases. If large RCO1 or RCO2 is set, when the output of COUT is "Hi-Z", the speed for pull-down the gate of the charge FET becomes slow and turning off the FET will be slow. Not only that, by dividing between the "Hi-Z" output and the resistance, turning off the charge FET may be difficult. If a small RDRAIN is set, when the excess discharge current and short circuit is detected, the large current may flow until the load is removed. *6) In terms of RVMP, when the cascade connection is made, if DOUT turns off, VMP pin is pulled up via RVMP to the top cell. In this case, the current flows via RVMP and the internal diode, therefore, appropriate value must be chosen. If the cascade connection is not used, around 10k is acceptable. *7) Set RUCO to satisfy RUCO=RCO1+RCO2. If a extremely large resistance is set, when the output of COUT is "Hi-Z", by the dividing resistance, CTLC pin may not be pulled down. If a small resistance is used, when the output of COUT is "H", the consumption current via RUCO increases. *8) If the open-wire detector function of VC2 to VC5 is used, use 0.47F to 1F as CCT1. If the open-wire detector function is unnecessary, use a capacitor of 0.01F or more. *9) If a too small CCT2 is set, excess discharge current detector output delay time 2 becomes shorter than the short circuit output delay time. Therefore, use a capacitor with 0.0022F or more. 39 R5432V NO.EA-263-160711 *10) If the open-wire detector of VC2 to VC5 is used, use 3.3F as CCTLT. If the open-wire detector of VC2 to VC5 is not necessary, pull down to VSS. *11) Considering the break down of the resistors and capacitors to stabilize the fluctuation of the voltage, to avoid that the high voltage is directly forced to the IC, adding a zener diode is our recommendation. Connect the zener diode between VDD pin of the IC and VSS pin directly. (Refer to the typical application circuits.) To set the number of connecting cells, SEL1/SEL2 pin must be connected to VDD level. In these cases, connect the pin inside the filter for stabilizing VDD pin voltage. If SEL1/SEL2 is connected outside the filter, during the operation, the voltage difference between SEL1/SEL2 and VDD may be generated, and unstable operation or excess current flow may result. The typical application circuit diagrams are just examples. This circuit performance largely depends on the PCB layout and external components. In the actual application, fully evaluation is necessary. Overvoltage and the over current beyond the absolute maximum rating should not be forced to the protection IC and external components. Especially, if the pack+ and Pack- are short, although the short protection circuit is built-in the IC, but during the output delay time, large current may flow through the FET. By the current during the output delay, in order not to destruct the FET, choose the FET with enough current rating. Ricoh cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ricoh product. If technical notes are not complied with the circuit which is used Ricoh product, Ricoh is not responsible for any damages and any accidents. To connect the protection IC and cells, connect VSS pin first. If the connect order is wrong, by flowing unexpected current, the IC may be damaged. If charge control FET and discharge control FET are connected in serial, if the control FET for charge turns off and discharge big current, or when the FET for discharge turns off and if charge with big current is done without discharge control FET turning off, big current flows through the parasitic diode of the FET, the FET may be burnt. To avoid this, separate the charge and discharge current path and when the FET turns off, in order not to flow large current through parasitic diode, choose an FET with large current capacity. 40 R5432V NO.EA-263-160711 TEST CIRCUITS A B VC1 VDD VDD SEL2 VC1 SEL2 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 Cout VSS V V V V OSCILLOSCOPE V VSS CTLT Cout CTLT C D VC1 VDD SEL2 V VC1 VDD SEL2 V CB1 SEL1 VC2 CTLD V CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 V CB2 CTLC VC3 VMP V V CB3 DRAIN VC4 Dout V V CB4 SENS VC5 CT1 V V CB5 CT2 CB5 CT2 VSS Cout VSS Cout CTLT CTLT 41 R5432V NO.EA-263-160711 E F VC1 VDD VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout A CTLT SEL2 V CTLT H G VC1 VDD SEL2 CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 CB5 CT2 VSS Cout CTLT 42 VDD SEL2 VC1 VDD SEL2 CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 CB5 CT2 VSS Cout V CTLT V R5432V NO.EA-263-160711 I J VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout VC1 A V CTLT SEL2 V CTLT L K VC1 VDD CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 CB5 CT2 VSS Cout CTLT VC1 SEL2 V VDD SEL2 CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 CB5 CT2 VSS Cout V CTLT 43 R5432V NO.EA-263-160711 M N VC1 VDD VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout V CTLT SEL2 V CTLT O P VC1 VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 Cout VSS VSS CTLT 44 VDD SEL2 V SEL2 Cout CTLT V R5432V NO.EA-263-160711 Q R VC1 VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout V CTLT SEL2 V CTLT S T VC1 V V V V V V VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout CTLT CTLT SEL2 V 45 R5432V NO.EA-263-160711 U V VDD VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 Cout VSS VSS V CTLT SEL2 V Cout CTLT X W VC1 V V V V V V 46 VDD SEL2 VC1 VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout CTLT CTLT SEL2 A R5432V NO.EA-263-160711 Y Z VDD VDD SEL2 VC1 CB1 SEL1 CB1 SEL1 VC2 CTLD VC2 CTLD CB2 CTLC CB2 CTLC VC3 VMP VC3 VMP CB3 DRAIN CB3 DRAIN VC4 Dout VC4 Dout CB4 SENS CB4 SENS VC5 CT1 VC5 CT1 CB5 CT2 CB5 CT2 VSS Cout VSS Cout VC1 A CTLT SEL2 CTLT A V a VC1 A VDD SEL2 CB1 SEL1 VC2 CTLD CB2 CTLC VC3 VMP CB3 DRAIN VC4 Dout CB4 SENS VC5 CT1 CB5 CT2 VSS Cout CTLT 47 R5432V NO.EA-263-160711 TYPICAL CHRACTERSTICS Part1. Temperature Characteristics 1) Overcharge voltage threshold (CELLn) R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 4.28 4.27 4.12 4.26 4.11 4.25 4.24 4.23 0 20 40 Ta (C) 60 80 4.09 100 3) Overcharge Detector Delay -60 -40 -20 20 40 Ta (C) 60 R5 4 3 2 V4 0 4 BA n=2, 3, 4, 5 VCELLn =3.2V, VCELL1 =3.2V->4.5V 1.6 0 80 100 4) Released from Overcharged Delay time Temperature R5 4 3 2 V4 0 4 BA n=2, 3, 4, 5 VCELLn =3.2V, VCELL1 =4.5V->3.2V 22 20 tVREL1(msec) 1.4 tVDET1(sec) 4.10 4.07 -60 -40 -20 1.2 1.0 0.8 0.6 18 16 14 12 0.4 10 -60 -40 -20 0 20 40 Ta (C) 60 80 100 5) CELL balance detector (CELLn) threshold R5 4 3 2 V4 0 4 BA -60 -40 -20 0 20 40 Ta (C) 60 80 100 6) CELL balance released Voltage (CELLn) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 4.23 4.22 4.22 4.21 4.21 4.20 4.19 4.18 n=1, 2, 3, 4, 5 VCELLn =3.2V 4.23 CBRELn(V) CBDETn(V) VCELLn =3.2V 4.08 4.22 4.20 4.19 4.18 4.17 4.17 -60 -40 -20 48 n=1, 2, 3, 4, 5 4.13 VREL1n(V) VDET1n(V) 2) Overcharge Released Voltage (CELLn) 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 R5432V NO.EA-263-160711 7) Overdischarge Detector Threshold (CELLn) R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 2.53 2.52 3.02 2.51 3.01 2.50 2.49 2.48 0 20 40 Ta (C) 60 80 100 9) Output Delay time of Overdischarge (CELLn) R5 4 3 2 V4 0 4 BA -60 -40 -20 0 20 40 Ta (C) 60 80 100 10) Output Delay Time of Released from Overdischarge (CELLn) R5 4 3 2 V4 0 4 BA n=2, 3, 4, 5 VCELLn =3.2V, VCELL1 =3.2V->1.5V, C1=33nF n=2, 3, 4, 5 VCELLn =3.2V, VCELL1 =1.5V->3.2V 1.8 1.6 tVREL2(msec) 160 tVDET2(msec) 2.99 2.97 -60 -40 -20 140 120 100 80 1.4 1.2 1.0 0.8 60 0.6 -60 -40 -20 0 20 40 Ta (C) 60 80 100 11) Excess Discharge Current Detector Thershold1 R5 4 3 2 V4 0 4 BA -60 -40 -20 0.21 0.62 VDET32(V) 0.64 0.18 60 80 100 n=1, 2, 3, 4, 5 VCELLn =3.2V 0.66 0.22 0.19 20 40 Ta (C) R5 4 3 2 V4 0 4 BA VCELLn =3.2V 0.20 0 12) Excess Discharge Current Detector Thershold2 n=1, 2, 3, 4, 5 0.23 VDET31(V) 3.00 2.98 2.47 180 n=1, 2, 3, 4, 5 VCELLn =3.2V 3.03 VREL2n(V) VDET2n(V) 8) Released Voltage from overdischarge (CELLn) 0.60 0.58 0.56 0.17 0.54 -60 -40 -20 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 49 R5432V NO.EA-263-160711 13) Short Detector Threshold 14) Excess discharge Current Detector Output Delay Time 1 R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 1.30 16 14 tVDET31(msec) Vshort(V) 1.20 1.10 1.00 0.90 0.80 0 20 40 Ta (C) 60 80 100 15) Excess discharge Current detector Output Delay Time2 R5 4 3 2 V4 0 4 BA 0 20 40 Ta (C) 60 80 100 16) Short Detector Output Delay Time R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, SENS=VSS->0.7V, C2=3.3nF n=1, 2, 3, 4, 5 VCELLn =3.2V, SENS=VSS->1.5V 0.6 0.5 tshort(msec) tVDET32(msec) 8 -60 -40 -20 2.2 2.0 1.8 1.6 1.4 0.4 0.3 0.2 0.1 1.2 0.0 -60 -40 -20 0 20 40 Ta (C) 60 80 100 17) Excess discharge Current released delay time R5 4 3 2 V4 0 4 BA -60 -40 -20 1.4 -0.19 VDET4(V) -0.18 0.8 60 80 100 n=1, 2, 3, 4, 5 VCELLn =3.2V -0.17 1.6 1.0 20 40 Ta (C) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 1.2 0 18) Excess charge Current Detector Threshold VCELLn =3.2V, VMP=0.4V->VSS 1.8 tVREL3(msec) 10 4 -60 -40 -20 -0.20 -0.21 -0.22 0.6 -0.23 -60 -40 -20 50 12 6 0.70 2.4 n=1, 2, 3, 4, 5 VCELLn=3.2V, SENS=VSS->0.4V, C2=3.3nF 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 R5432V NO.EA-263-160711 19) Excess Charge Current Output Delay Time R5 4 3 2 V4 0 4 BA 20) Excess Charge Current Delay Time of Released R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V, SENS=VSS->-0.4V 12 1.8 1.6 tVREL4(msec) tVDET4(msec) 10 8 6 4 1.2 1.0 0.8 0 0.6 0 20 40 Ta (C) 60 80 100 21) CTLC Pin "H" Input Voltage -60 -40 -20 18.4 17.6 15.2 CTLC2H(V) 15.6 17.2 16.8 16.0 13.6 60 80 100 23) CTLD Pin "H1" Input Voltage -60 -40 -20 0 20 40 Ta (C) 60 R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 18.4 80 100 17.6 15.2 CTLD2H(V) 15.6 17.2 16.8 14.8 14.4 16.4 14.0 16.0 13.6 60 80 100 n=1, 2, 3, 4, 5 VCELLn =3.2V 16.0 18.0 20 40 Ta (C) n=1, 2, 3, 4, 5 VCELLn =3.2V 24) CTLD Pin "H2" Input Voltage R5 4 3 2 V4 0 4 BA 0 100 14.4 14.0 -60 -40 -20 80 14.8 16.4 20 40 Ta (C) 60 16.0 18.0 0 20 40 Ta (C) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V -60 -40 -20 0 22) CTLC Pin "H2" Input Voltage R5 4 3 2 V4 0 4 BA CTLC1H(V) 1.4 2 -60 -40 -20 CTLD1H(V) n=1, 2, 3, 4, 5 VCELLn =3.2V, VMP=-1.0V->1.0V -60 -40 -20 0 20 40 Ta (C) 60 80 100 51 R5432V NO.EA-263-160711 25) DOUT Nch ON Voltage 26) DRAIN Nch ON Voltage R5 4 3 2 V4 0 4 BA 0.12 0.10 0.10 0.08 0.08 0.06 0.04 0.02 0 20 40 Ta (C) 60 80 100 27) CB1 Nch ON Voltage -60 -40 -20 0 20 40 Ta (C) 60 80 100 28) CB2 Nch ON Voltage R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0.30 n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0.30 0.25 VOL5-VC3(V) 0.25 VOL4-VC2(V) 0.04 0.00 -60 -40 -20 0.20 0.15 0.10 0.05 0.20 0.15 0.10 0.05 0.00 0.00 -60 -40 -20 0 20 40 Ta (C) 60 80 100 29) CB3 Nch ON Voltage -60 -40 -20 0 20 40 Ta (C) 60 80 100 30) CB4 Nch ON Voltage R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0.30 n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0.30 0.25 0.25 VOL7-VC5(V) VOL6-VC4(V) 0.06 0.02 0.00 0.20 0.15 0.10 0.05 0.20 0.15 0.10 0.05 0.00 0.00 -60 -40 -20 52 n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0.12 VOL3(V) VOL2(V) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 R5432V NO.EA-263-160711 31) CB5 Nch ON Voltage 32) VR12V Output Voltage R5 4 3 2 V4 0 4 BA 0.30 0.25 13.0 0.20 12.5 0.15 0.10 0.00 10.5 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 34) DOUT Pch ON Voltage R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOH=-50uA 0.00 n=1, 2, 3, 4, 5 VCELLn=3.2V, IOH=-50uA 0.00 -0.05 VOH2-VVR12(V) -0.05 VOH1-VDD(V) 11.5 11.0 33) COUT Pch ON Voltage -0.10 -0.15 -0.20 -0.25 -0.10 -0.15 -0.20 -0.25 -0.30 -0.30 -60 -40 -20 0 20 40 Ta (C) 60 80 100 35) DRAIN Pch ON Voltage -60 -40 -20 20 40 Ta (C) 60 R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOH=-50uA 0.00 0 80 100 36) CB1 Pch ON Voltage R5 4 3 2 V4 0 4 BA 0.0 n=2, 3, 4, 5 VCELLn=3.2VVCELL1=4.5V, IOH=-50uA -0.1 VOH4-VC1(V) -0.05 VOH3-VVR12(V) 12.0 0.05 -60 -40 -20 n=1, 2, 3, 4, 5 VCELLn=3.2V 13.5 VVR12(V) VOL8(V) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn=3.2V, IOL=-50uA -0.10 -0.15 -0.20 -0.25 -0.2 -0.3 -0.4 -0.5 -0.30 -0.6 -60 -40 -20 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 53 R5432V NO.EA-263-160711 37) CB2 Pch ON Voltage 38) CB3 Pch ON Voltage R5 4 3 2 V4 0 4 BA 0.0 R5 4 3 2 V4 0 4 BA n=1, 3, 4, 5 VCELLn=3.2V, VCELL2=4.5V, IOH=-50uA 0.0 -0.2 -0.3 -0.4 -0.5 0 20 40 Ta (C) 60 80 -60 -40 -20 0 20 40 Ta (C) 60 80 100 40) CB4 Pch ON Voltage R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 5 VCELLn=3.2V, VCELL4=4.5V, IOH=-50uA 0.0 n=1, 2, 3, 4 VCELLn=3.2V, VCELL5=4.5V, IOH=-50uA -0.1 VOH8-VC5(V) -0.1 VOH7-VC4(V) -0.4 100 39) CB4 Pch ON Voltage -0.2 -0.3 -0.4 -0.5 -0.2 -0.3 -0.4 -0.5 -0.6 -0.6 -60 -40 -20 0 20 40 Ta (C) 60 80 -60 -40 -20 100 41) CTLT Detector threshold 0 20 40 Ta (C) 60 80 100 42) CTLT release Voltage R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 3.0 2.5 0.25 2.0 0.20 1.5 1.0 0.5 n=1, 2, 3, 4, 5 VCELLn =3.2V 0.30 VRTLT(V) VDTLT(V) -0.3 -0.6 -60 -40 -20 0.15 0.10 0.05 0.0 0.00 -60 -40 -20 54 -0.2 -0.5 -0.6 0.0 VCELLn=3.2V, VCELL3=4.5V, IOH=-50uA -0.1 VOH6-VC3(V) VOH5-VC2(V) -0.1 n=1, 2, 4, 5 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 R5432V NO.EA-263-160711 43) CTLT Excess charge Current 44) Open-wire test interval time R5 4 3 2 V4 0 4 BA 0.6 0.5 34 0.4 32 0.3 0.2 0.1 28 24 -60 -40 -20 0 20 40 Ta (C) 60 80 100 45) COUT Off leak current -60 -40 -20 0 20 40 Ta (C) 60 80 100 46) Supply Current1 R5 4 3 2 V4 0 4 BA R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2VCTLC=VDDCOUT=-14V 1.0 20 0.8 16 0.6 0.4 0.2 n=1, 2, 3, 4, 5 VCELLn =3.2V 24 Iss1(uA) ILCOUT(uA) 30 26 0.0 1.2 n=1, 2, 3, 4, 5 VCELLn =3.2V, C3=3.3uF 36 tLT(sec) ICTLT(uA) R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =3.2V 12 8 4 0.0 0 -60 -40 -20 0 20 40 Ta (C) 60 80 100 -60 -40 -20 0 20 40 Ta (C) 60 80 100 47) Supply Current2 R5 4 3 2 V4 0 4 BA n=1, 2, 3, 4, 5 VCELLn =1.5V 24 Iss2(uA) 20 16 12 8 4 0 -60 -40 -20 0 20 40 Ta (C) 60 80 100 55 R5432V NO.EA-263-160711 Part2.Output Delay Time VDD dependence 1) Overcharge detector output Delay Time 2) Overcharge Released Delay Time R5 4 3 2 V4 0 4 BA VCELL1 =4.5V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD 1.6 24 1.4 20 tVREL1 (msec) tVDET1 (sec) R5 4 3 2 V4 0 4 BA VCELL1 =3.2V, 3.6V, 4.0V->4.5V, SEL1=SEL2=VDD 1.2 1 0.8 0.6 12 8 4 0.4 0 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 3.0 3.6 3.8 VCELLn (V) 4.0 4.2 n=2, 3, 4, 5 R5 4 3 2 V4 0 4 BA VCELL1 =2.0V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD 1.8 160 1.6 tVREL2 (msec) R5 4 3 2 V4 0 4 BA VCELL1 =3.2V, 3.6V, 4.0V->2.0V, SEL1=SEL2=VDD 180 140 120 100 1.4 1.2 1 0.8 60 0.6 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 3.0 3.2 3.4 n=2, 3, 4, 5 5) Excess discharge current detector Delay Time 1 14 2.2 tVDET32 (msec) 2.4 10 8 6 4.0 4.2 n=2, 3, 4, 5 R5 4 3 2 V4 0 4 BA SENS=Vss->Vss+0.7V, SEL1=SEL2=VDD 16 12 3.6 3.8 VCELLn (V) 6) Excess discharge current detector Delay Time 2 R5 4 3 2 V4 0 4 BA SENS=Vss->Vss+0.4V, SEL1=SEL2=VDD tVDET31 (msec) 3.4 4) Overdischarge Released Delay Time 80 2 1.8 1.6 1.4 4 1.2 3.0 56 3.2 n=2, 3, 4, 5 3) Overdischarge detector output Delay Time tVDET2 (msec) 16 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 n=1, 2, 3, 4, 5 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 n=1, 2, 3, 4, 5 R5432V NO.EA-263-160711 7) Short detector output delay time1 8) Excess discharge current released delay time2 R5 4 3 2 V4 0 4 BA V-=Vss+0.4V->Vss, SEL1=SEL2=VDD 0.6 1.8 0.5 1.6 tVREL3 (msec) tshort (msec) R5 4 3 2 V4 0 4 BA SENS=Vss->Vss+1.5V, SEL1=SEL2=VDD 0.4 0.3 0.2 0.1 1.4 1.2 1 0.8 0 0.6 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 3.0 9) Excess charge current detector output Delay Time 3.4 10 1.6 tVREL4 (msec) 1.8 6 4 2 4.0 4.2 n=1, 2, 3, 4, 5 R5 4 3 2 V4 0 4 BA V-=Vss-0.4V->Vss+0.4V, SEL1=SEL2=VDD 12 8 3.6 3.8 VCELLn (V) 10) Excess charge current released delay time R5 4 3 2 V4 0 4 BA V-=Vss->Vss-0.4V, SEL1=SEL2=VDD tVDET4 (msec) 3.2 n=1, 2, 3, 4, 5 1.4 1.2 1 0.8 0 0.6 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 n=1, 2, 3, 4, 5 3.0 3.2 3.4 3.6 3.8 VCELLn (V) 4.0 4.2 n=1, 2, 3, 4, 5 57 R5432V NO.EA-263-160711 * Part3. Supply Current VDD dependence (R5432V404BA) 330 1uF 330 VC1 Cell1 VDD CB1 0.1uF 330 VC2 Cell2 CB2 0.1uF 330 VC3 Cell3 CB3 0.1uF 330 VC4 Cell4 CTLD VSS CTLC VSS SEL2 SEL1 CB4 0.1uF VMP 330 VC5 Cout DRAIN Cell5 CB5 A 0.47uF 10k CT2 2M CTLT 3.3nF 100m 10k Supply Current for 5-cell protection 14 12 Supply Current Iss(A) 10 8 6 4 2 0 0 5 10 15 VDD(V) 58 10M SENS VSS CT1 1M Dout 0.1uF 20 25 R5432V NO.EA-263-160711 Part4. External resistance dependence (R5432V404BA) 330 1uF R1 VC1 Cell1 VDD CB1 0.1uF 330 VC2 Cell2 CB2 0.1uF 330 VC3 Cell3 CB3 0.1uF 330 VC4 Cell4 CTLD VSS CTLC VSS SEL2 SEL1 CB4 0.1uF VMP 330 VC5 Cout DRAIN Cell5 CB5 1M Dout 0.1uF 10k VSS CT1 10M SENS CT2 0.47uF 2M CTLT 3.3nF 100m 10k VREL11 VDET21 VREL21 4.120 4.260 4.115 2.510 3.005 4.255 4.110 2.505 3.000 4.250 4.105 2.500 2.995 4.245 4.100 2.495 2.990 4.240 4.095 2.490 2.985 4.090 2000 2.485 4.235 0 500 1000 R1() 1500 VDET21(V) 4.265 2.515 VREL11(V) VDET11(V) VDET11 Overdischarge Detector/Released Voltage from Overdischarge vs. R1 (CELL1) 0 500 1000 R1() 1500 3.010 VREL21(V) Overcharge Detector/Released Voltage from Overcharge vs. R1 (CELL1) 2.980 2000 59 R5432V NO.EA-263-160711 CELL balance detector / Released Voltage from CELL balance vs. R1 (CELL1) CBDET1(V) 4.215 4.210 4.210 4.205 4.205 4.200 4.200 4.195 4.195 4.190 4.190 4.185 0 60 500 1000 R1() 1500 4.185 2000 CBREL1(V) CBREL1 CBDET1 4.215 POWER DISSIPATION SSOP-24 Ver. A The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following conditions are used in this measurement. Measurement Conditions Standard Test Land Pattern Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Double-Sided Board) Board Dimensions 40 mm x 40 mm x 1.6 mm Copper Ratio Top Side: Approx. 50% Bottom Side: Approx. 50% Through-holes 0.5 mm x 44 pcs Measurement Result (Ta = 25C, Tjmax = 125C) Standard Test Land Pattern Power Dissipation 770 mW Thermal Resistance ja = (125 - 25C) / 0.770 W = 130C/W 40 800 770 Standard Test Land Pattern 600 40 Power Dissipation (mW) 1000 400 200 0 0 25 50 75 85 100 125 150 Ambient Temperature (C) Power Dissipation vs. Ambient Temperature IC Mount Area (mm) Measurement Board Pattern i PACKAGE DIMENSIONS SSOP-24 Ver. A 0.65 0.10 +0.1 0.220.05 0.15 M +0.1 0.150.05 1.4Max. 0.375 TYP. 0.10.05 1.150.1 7.90.2 7.60.2 5.60.2 0 to 10 0.50.2 SSOP-24 Package Dimensions (Unit: mm) i 1. The products and the product specifications described in this document are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. The materials in this document may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise taking out of your country the products or the technical information described herein. 4. The technical information described in this document shows typical characteristics of and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, telecommunication equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order to prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. Anti-radiation design is not implemented in the products described in this document. 8. The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and characteristics in the evaluation stage. 9. WLCSP products should be used in light shielded environments. The light exposure can influence functions and characteristics of the products under operation or storage. 10. There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the case of recognizing the marking characteristic with AOI, please contact Ricoh sales or our distributor before attempting to use AOI. 11. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or the technical information. Halogen Free Ricoh is committed to reducing the environmental loading materials in electrical devices with a view to contributing to the protection of human health and the environment. Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since April 1, 2012. https://www.e-devices.ricoh.co.jp/en/ Sales & Support Offices Ricoh Electronic Devices Co., Ltd. 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