R5432V SERIES
3 to 5 Cells Li-ion Batt ery Protector IC
NO.EA-263-1600711
1
OUTLINE
The R5432V is a h igh vo ltage CMOS-based prot ection IC for overcharge /dis charge of r ech argeable three-cell / four-cell / five-
cell Lithium-ion / Lit hium- polymer battery, further inc lude a short circuit a nd the pr otectio n circuit s again st the ex cess dis charge
current and ex cess charge current.
Each of these ICs is composed of eighteen voltage detectors (fourteen for 3cell protection type, sixteen for 4cell protection
type), a reference circuit, a delay circuit, a short detector circuit, an oscillator, a counter and a logic circuit.
The output of COUT is P-channel open-drain type, and DOUT is CMOS type.
If the overcharge voltage or overcharge current is detected by the R5432V, after the preset output delay time, the output of
COUT becomes Hi-Z.
While the overdischarge voltage or current is detected, after the preset output delay time, the output of DOUT becomes ”L”.
After det ectin g overc harge v oltage, when the cell vol tage retur ns low er than the overcharge relea sed v oltage, t hen overcharge
is released and the output of COUT becomes “H”. After detecting overcharge current, by disconnecting a charger and
connecting a load, then overcharge current is released and the output of COUT becomes “H”.
After detecting overdischarge voltage, when the cell voltage becomes the released voltage from overdischarge or more,
then overdischarge is released and the output of DOUT bec omes “H”. After detecting overdischarge current and short circuit,
by disconnecting the load, the function of the output of DRAIN pin, the external NMOSFET turns on, and VMP pin voltage is
pulled dow n by the resistance connected to GND and released overdischarge current or short and the o utput of DOUT becomes
“H”.
By forcing a certain voltage to SEL1 and SEL2 pins, the testing time of protection circuits can be short. Specifically,
overcharge, discharge, over current delay time can be shortening into approximately 1/80.
The R5432V can prote ct 6-cell or more by connecting 2 pieces of the R5432V in cascade. H igh side ICs COUT and
DOUT must connect to CTLC and CTLD respectively of the low side IC. As a result, the signal of the high side of COUT and
DOUT is transmit to the lower side IC, and control FETs for charge and discharge.
The R5432V has cell-balance function to solve the unbalance condition of serially connected cells. If ce ll volt age is
beyond the cell balance detector threshold, by the output of the cell balance control pin, the external NMOSFET turns on, and
a current path is made, and during charge, charge current is bypassed, otherwise, cell is discharged until the cell voltage
becomes the released voltage from cell-balance operation.
If the connection between a cell and a protection board is broken, the open-wire condition is detected by the R5432V, and t he
output of COUT bec omes Hi-Z. After detecting the open-wire, when the cell and the protection board is connected again, the
open-wire detector is released and the output of COUT becomes “H”.
FEATURES
Absolute Maximum Rating ............................................... 30V
Supply Current ................................................................. Typ. 12.0µA
Detector thresholds range and accuracy
Overcharge detector threshold ......................................... 3.6V to 4.5V (5mV step) (n=1, 2, 3, 4, 5) (±25mV)
Overdischarge detector threshold .................................... 2.0V to 3.0V (5mVstep) (n=1, 2, 3, 4, 5) (±2.5%)
Excess disch arge current threshold 1 .............................. 0.1V to 0.3V (10mVstep) (±20mV) for BA/BB/BC ver.
0.1V to 0.2V (10mV step) (±20mV) for AD/BD ver .
Excess discharge current threshold 2 .............................. 0.45V/0.60V for BA ver.
0.25V to 0.40V for BB/BC ver.
0.25V/0.3V(Vdet3-1+ 0.1V or more) for AD/BD ver.
R5432V
NO.EA-263-160711
2
Short detector threshold ..................................................... 1.00V for BA ver.
0.75V for BB/BC ver.
Vdet3-2 x 1.67 for AD/BD ver.
Excess charge current threshold ........................................
-0. 05V (
±
30mV), -0.1V (
±
30mV), -0.2V (
±
30mV), -0.4V (
±
40mV)
Overcharge released voltage.............................................. VDET1n-0.1V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5)
Overdischarge released voltage ......................................... VDET2n+0.2V to 0.7V (100mV steps) (n=1, 2, 3, 4, 5)
up to 3.4V
Cell-balance detector thre sho l d .......................................... 3.45V to 4.45V (5mV steps) (n=1, 2, 3, 4, 5)
Cell-balance released voltage ............................................ CBDETn-0.0V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5)
Output delay time
Overcharge detector Output Delay ..................................... 1.0s
Overdischarge detector Output Delay ................................ Settable by Ext.Capacitance1
Excess disch arge current detector Output Delay 1/2 .......... Settable by Ext.Capacitance2
Excess charge curr e nt detector Output Delay .................... 8ms
Short detector Output Delay ............................................... 300µs
Functions
0V-battery charger ........................................... .................. accepta ble/ una cce pta ble options
Cascade connection ........................................ .................. Available. Refer to the typical application.
3/4/5 cell protec tio n ........................................ .................. Selectable
Output Delay Time Shortening Function ............................. By forcing a certain voltage to SEL pin, overcharge,
discharge v ol tage and curr ent is re duc ed approx imately 1/80.
Overcharge delay time can be shorten into around 4ms for
testing.
Cell-balance function .......................................................... Available
Cell-unbalance condition .................................................... If e ither of c ell s dete ct s overchar ge and ei ther of cells dete cts
overdischarge, the output of COUT becomes Hi-Z”, the output of DOUT becomes “L”.
Overcharge/Overdischarge released condition................... By voltage condition.
Output of COUT/DOUT ...................................................... COUT: VDD source P-channel open drain output. Normal
state “H”(VDD) , Detected state Hi-Z”.
DOUT: 12V regulator source CMOS output. Normal state
“H”(12V), Detected state L”.
Open-wire detection ........................................................... Open-wire between VDD, VSS, VCx pin and the pack is
supervised.
Small Package .................................................................... SSOP-24
R5432V
NO.EA-263-160711
3
BLOCK DIAGR AMS
R5432VxxxBA
V
C2
V
C1
VD2-1
VD1-1
VD2-2
VD1-2
VD2-3
VD1-3
VD2-4
VD1-4
V
C3
V
C4
V
C5
SEL1
V
DD
VD2-5
VD1-5
V
SS
Logic
Circuit
SEL2
Logic
Circuit
CB
2
CB
1
CB
3
CB
4
CTLT
CB
5
CB
Circuit-1
CB
Circuit-2
CB
Circuit-3
CB
Circuit-4
CB
Circuit-5
Delay
Short
Circuit
SENS
Ds
Circuit
Logic
Circuit
Logic
Circuit
Regulator
Regulator
CT1
CT2
DRAIN
VMP
CTLD
CTLC
Logic
Circuit
D
OUT
C
OUT
tV
DET2
VD3-2
VD3-1
VD4
T Stop
T Start
odd sw
even sw
tV
DET3
Counter
Oscillatpr
R5432V
NO.EA-263-160711
4
SELECTION GUIDE
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R5432Vxxx$
SSOP-24 3000 Yes Yes
xxx :Serial Number for the R5432V designating voltages such as overcharge threshold, overcharge
released vol tag e, Cell-balance threshold, Cell-balance released voltage, overdischarge threshold,
overd isc harge rel eased vo lt age, ov er discharge current1/2, overcharge current, short voltage.
$ : Designation of Output delay option.
Overcharge
Delay time
(s)
Overdischarge
Delay time
(ms)
Overdischarge
Current Delay time1
(ms)
Overdischarge
Current Delay time2
(ms)
Overcharge
Current Delay time
(ms)
Short
Delay time
(µs)
A
1.0
3.64×C
CT1
(nF)
3.05×C
CT2
(nF)
tV
DET
31/ 100
8
300
B
1.0
3.88×CCT1 (nF)
3.26×CCT2 (nF)
tVDET31/ 6
8
300
*capacitor for CT1: CCT1, capacitor for CT2:CCT2.
: Designation of Output delay option.
Overcharge
Released condition
Overdischarge
Released condition
0V battery
Charge
Short detect or
Threshold
Open-wire
detection
Cascade
connection
A
Auto Release
Auto Release
Acceptable
1.0V
Available
Available
B
Auto Release
Auto Release
Unacceptable
0.75V
Available
Available
C
Auto Release
Auto Release
Acceptable
0.75V
Available
Available
D
Auto Release
with hysteres is
cancellation
Auto Release Acceptable VDET32 x 1.67
Available Available
R5432V
NO.EA-263-160711
5
1) Product Code List
Code
VDET1n
(V) *1
VREL1n
(V) *1
VCBDn
(V) *1
VCBRn
(V) *1
VDET2n
(V) *1
VREL2n
(V) *1
VDET31
(V)
VDET32
(V)
VSHORT
(V)
VDET4
(V)
R5432V402BA
4.350
4.050
4.200
4.200
2.400
2.700
0.200
0.600
1.000
-0.100
R5432V403BA
3.900 3.800 3.500 3.500 2.500 3.000 0.100 0.600 1.000 -0.100
R5432V404BA
4.250
4.100
4.200
4.200
2.500
3.000
0.200
0.600
1.000
-0.200
R5432V405BA
3.900 3.800 3.650 3.650 2.000 2.300 0.100 0.600 1.000 -0.200
R5432V406BA
3.650
3.550
3.500
3.500
2.500
3.000
0.300
0.600
1.000
-0.200
R5432V407BA
4.200 4.000 3.900 3.900 2.700 2.850 0.200 0.450 1.000 -0.200
R5432V408BA
3.800
3.600
3.450
3.450
2.000
2.300
0.200
0.450
1.000
-0.100
R5432V409BA
4.100 4.000 3.900 3.900 3.000 3.100 0.200 0.600 1.000 -0.200
R5432V410BC
4.200
4.000
4.150
4.150
2.750
2.950
0.100
0.250
0.750
-0.050
R5432V412BA
4.300 4.050 4.200 4.200 2.700 3.000 0.200 0.600 1.000 -0.100
R5432V413BA
4.250
4.100
4.200
4.200
2.500
3.000
0.100
0.600
1.000
-0.100
R5432V416BA
4.200 4.100 4.170 4.170 2.500 3.000 0.200 0.450 1.000 -0.100
R5432V417BC
4.200
4.100
4.180
4.180
2.500
3.000
0.100
0.400
0.750
-0.050
R5432V418BC
4.180 4.080 4.180 4.180 2.500 3.000 0.100 0.400 0.750 -0.050
R5432V419BD
3.900
3.800
3.500
3.500
2.500
3.000
0.100
0.300
0.500
-0.100
R5432V420BD
4.350 4.050 4.200 4.200 2.400 2.700 0.100 0.250 0.418 -0.100
R5432V501BA
3.900
3.700
3.800
3.600
2.000
2.300
0.200
0.600
1.000
-0.200
R5432V502BA
4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.450 1.000 -0.050
R5432V503BB
4.250
4.150
4.150
4.140
2.700
3.000
0.150
0.300
0.750
-0.050
R5432V504BD
4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.250 0.418 -0.050
R5432V505BD
4.250
4.100
4.200
4.190
2.500
3.000
0.100
0.250
0.418
-0.050
R5432V506BD
3.900 3.800 3.650 3.640 2.000 2.300 0.100 0.250 0.418 -0.050
R5432V507BD
4.215
4.100
4.200
4.180
2.800
3.000
0.100
0.250
0.418
-0.100
R5432V508BA
3.800 3.700 3.600 3.580 2.800 2.900 0.200 0.600 1.000 -0.100
R5432V509BD
3.900
3.800
3.650
3.640
2.000
2.300
0.100
0.250
0.418
-0.100
R5432V510BD
3.900 3.800 3.475 3.465 2.000 2.300 0.100 0.250 0.418 -0.100
*1n1,2,3,4,5
R5432V
NO.EA-263-160711
6
PIN DESCR IPTIO NS
SSOP-24
1
5
2
3
4
6
7
8
16
15
14
13
9
10
11
12
17
18
19
20
21
22
23
24
Pin No Symbol Pin Description
1
CTLC
C
OUT
control pin
2 CTLD DOUT control pin
3
C
OUT
Output pin of overcharge d et ecti on, Pch OPEN DRAIN output
4 VMP Pin for charger negative input
5
DRAIN
Release from Excess discharge-current threshold Pin
6
D
OUT
Output pin of overdischarge detection,CMOS output
7
SENS
Current sense pin
8
CTLT
Disconnection detection movement interval setting capacitance pin
9
V
SS
V
SS
pin. Ground pin for the IC
10
CT1
tV
DET2
setting capacitance connection pin
11
CT2
tV
DET3
setting capacitance connection pin
12
SEL1
3cell/4cell/5cell alternative pin1
13 SEL2 3cell/4cell/5cell alternative pin2
14
CB5
CELL5 Cell balance Control pin
15 VC5 Positive terminal pin for Cell5
16
CB4
CELL4 Cell balance Control pin
17
V
C4
Positive terminal pin for Cell4
18
CB3
CELL3 Cell balance Control pin
19
V
C3
Positive terminal pin for Cell3
20
CB2
CELL2 Cell balance Control pin
21
V
C2
Positive terminal pin for Cell2
22 CB1 CELL1 Cell balance Control pin
23
V
C1
Positive terminal pin for Cell1
24 VDD VDD
pin
R5432V
NO.EA-263-160711
7
ABSOLUTE MAXIMUM R ATINGS
Symbol
Item
Rating
Unit
VDD
Supply voltage
-0.3 to 30
V
Input voltage
VC1
Positive input pin for Cell1
VC2-0.3 to VC2+6.5
V
V
C2
Positive input pin for Cell2
VC3-0.3 to VC3+6.5
V
V
C3
Positive input pin for Cell3
V
C4
-0.3 to V
C4
+6.5
V
VC4 Positive input pin for Cell4 VC5-0.3 to VC5+6.5 V
VC5
Positive input pin for Cell5
-0.3 to 6.5
V
VMP
Charger negative terminal input pin
-0.3 to 30.0
V
VSEL1 3Cell/4Cell/5Cell alternative pin1 -0.3 to VDD+0.3 V
V
SEL2
3Cell/4Cell/5Cell alternative pin2
-0.3 to VDD+0.3
V
VCTLC COUT c ontrol pin
-0.3 to VDD+25
V
-0.3 to 48
VCTLD DOUT c ontrol pin
-0.3 to VDD+25
V
-0.3 to 48
V
SENSE
Current sense pin
-0.3 to VDD+0.3
V
V
CT1
Delay time setting pin1
-0.3 to 3.5
V
VCT2
Delay time setting pin2
-0.3 to 3.5
V
VCTLT
Disconnection detection movement interval setting
capacitance pin
-0.3 to 3.5 V
Output voltage
VCOUT
Output pin of overcharge d et ecti on,CMOS outp ut
VDD-30 to VDD+0.3 V
V
DOUT
Output pin of overdischarge detection,CMOS output
-0.3 to VOH2+0.3
V
VDRAIN Release from Excess discharge-current threshold Pin -0.3 to VOH3+0.3 V
VCB1
Cell balance Control pin for Cell1
V
C2
-0.3 to V
C2+
6.5
V
VCB2
Cell balance Control pin for Cell2
VC3-0.3 to VC3+6.5 V
V
CB3
Cell balance Control pin for Cell3
VC4-0.3 to VC4+6.5
V
VCB4
Cell balance Control pin for Cell4
VC5-0.3 to VC5+6.5
V
V
CB5
Cell balance Control pin for Cell5
-0.3 to 6.5
V
PD
Power dissipation(1)
770
mW
Ta
Operating temperature range
-40 to 85
°C
Tstg
Storage temperature range
-55 to 125
°
C
ABSOLUTE MAXIMUM RATINGS
Electroni c and mechani cal stre ss momentarily exceeded ab solute maximu m ratings may cause the permanent da mages
and may degrade the life ti me and safety f or both devi ce and system using the de v ice in the field.
The functional operations at or over these absolute maximum ratings are not assured.
(1) Refer to POWER DISSIPATION for detailed information.
R5432V
NO.EA-263-160711
8
ELEC TRICAL CHAR ACTERIS TICS
R5432VxxxBA Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1 Operating input voltage VDD-VSS 2 25 V -
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect fa l l i ng edge of supply voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V (n=2,3,4,5),
VCELL1=3.5V→4.5V
0.7 1.0 1.3 s B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VCBRn
-0.050 VCBRn
Lower of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Detect rising ed ge of supply voltage
VREL2n
×0.975 VREL2n
VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n
=
2, 3, 4, 5), V
CELL1=
1.5V
1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=33nF
89 128 167 ms -
tVREL2 Output delay of
release from overdischarge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
0.500 0.600 0.700 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Detect falling edge of supply voltage
VDET31
×0.50 VDET31
×0.75 VDET31
×.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENSE=VSS0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V
(n=1,2,3,4,5) SENSE
=
V
SS
0.7V
2.0 3.0 4.0 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V (n=2,3,4,5)
SENSE=0.4V, VMP=4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=3.3nF
7.3 10.8 14.7 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=3.3nF
1.25 1.8 2.4 ms -
tVREL3
Output delay of release from
Excess
discharge-current
Threshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
9
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply voltage
0.7 1.0 1.7 V K
tshort
Output Delay of Sh o rt pr otection
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENS=0.0V2.0V,
VMP=4.0V
180 300 550 µs K
VDET4 Excess char ge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld
V
DD
=V
C1,
V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→-1.0V
5 8 11 ms L
tVrel4
Output delay
of release from
Excess
charge-current threshold
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3 V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) 4.0 VDD/2
-0.5V V M
VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
VSS
-0.3
VSS
+1.0
V M
VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) VDD
-0.3 VDD
+0.3 V N
VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
4.0 VDD/2
-0.5V
V N
VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+0.3 V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
, C
TLD
=V
DD
VCELLn =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age IOL=50μA, VDD=VC1,
VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
R5432V
NO.EA-263-160711
10
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
C
TLC
=V
SS
VDD
-0.5 VDD
-0.1 V T
VVR12 VR 12V output voltage (*1)
I
OH
=-5µA, V
DD
=V
C1
, C
TLD
=V
SS
,
VCELL=3.2V (n=1, 2, 3, 4, 5)
Measured to draw the current
through DOUT
10 12 14 V U
VOH2 DOUT Pch ON voltage (*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLD= VSS
VVR12
-0.5V VVR12
-0.1V V U
VOH3 DRAIN Pch ON volta ge (*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
SENS =VMP =4.0V
VVR12
-0.5V VVR12
-0.1V V V
VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
VCELLn=3.2V (n =2, 3, 4, 5)
VC1
-0.5 VC1
-0.3 V W
VOH5 CB2 Pch ON voltage
I
OH
=-50µA, V
DD
=V
C1
, V
C1
=4.5V,
V
CELL
n
=
3.2V (n
=
1, 3, 4, 5)
V
C2
-0.5
V
C2
-0.3
V W
VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
V
CELL
n
=
3.2V (n
=
1, 2, 4, 5)
VC3
-0.5 VC3
-0.3 V W
VOH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 5)
VC4
-0.5 VC4
-0.3 V W
VOH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 4)
VC5
-0.5 VC5
-0.3 V W
ILCOUT COUT pin off leak current
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
CTLC=VDD, COUT=-14V
-0.1 µA X
ICTLT CTLT Charge Current VDD=VC1, VCELLn=3.2V
(n
=
1, 2, 3, 4, 5)
145 205 264 nA Y
VDTLT CTLT detector threshold
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 4, 5)
VC3=VD1+0.2V
1.58 2.00 2.42 V Z
VRTLT CTLT released voltage
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
0.07 0.13 0.19 V Z
tLT Disconnection detec tion
Test Interval
CCTLT×(VDTLT-VRTLT)/ICTLT
CCTLT =3.3µF 21 30 39 s -
ISS1 Supply Currnt1
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=VDET1n-0.4V
(n=1, 2, 3, 4, 5)
12 30 µA a
ISS2 Supply Currnt2
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=1.5V
(n=1, 2, 3, 4, 5)
10 25 µA a
VCELLn=CELLn voltage n=1, 2, 3, 4, 5
(*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. The
semiconductor devices may receive serious damage when they continue to operate over the recommended operating
conditions.
R5432V
NO.EA-263-160711
11
R5432VxxxBB/BC Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1
Operating input voltage
VDD-VSS
2
25
V
-
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect falling edge of supply
voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=3.5V→4.5V
0.7 1.0 1.3 s B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect falling edge of supply
voltage
VCBRn
-0.050 VCBRn
Lower
of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply
voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
VREL2n
×0.975 VREL2n VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n=2, 3, 4, 5), VCELL1=1.5V 1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=33nF
89 128 167 ms -
tVREL2 Output delay of
release from overdischarge
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Det ect ri sing e dge of s upp ly volt age
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Det ect ri sing e dge of s upp ly volt age
VDET32
-0.070 VDET32 VDET32
+0.070 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Det ect f alli ng edge of su pply volt age
VDET31
×0.50 VDET31
×0.75 VDET31
×.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS0.7V
2.0 3.0 4.0 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V
(n=2,3,4,5)
SENSE=0.4V, VMP=4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=3.3nF
7.3 10.8 14.7 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=3.3nF
1.25 1.80 2.40 ms -
tVREL3
Output delay of release from
Excess
discharge-cur rent T hreshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
12
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply vol t age
0.7 1.0 1.7 V K
tshort
Output Delay of Sh o rt pr otection
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V2.0V,VMP=4.0V
180 300 550 μs K
VDET4 Excess charge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld
V
DD
=V
C1,
V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→-1.0V
5 8 11 ms L
tVrel4
Output delay
of release from
Excess charge-current
threshold
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
4.0 VDD/2
-0.5V
V M
VIL1 SEL1 pin “L” input voltage
V
DD
=V
C1,
V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+1.0
V M
VIH2 SEL2 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V N
VIM2 SEL2 pin “M” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
4.0
V
DD
/2
-0.5V
V N
VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+0.3 V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50μA, V
DD
=V
C1
, C
TLD
=V
DD
V
CELL
n =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age IOL=50μA, VDD=VC1,
VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50μA, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLC=VSS
VDD-0.5 VDD-0.1 V T
R5432V
NO.EA-263-160711
13
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VVR12 VR 12V output voltage(*1)
I
OH
=-5µA, V
DD
=V
C1
, C
TLD
=V
SS
,
VCELL=3.2V (n=1, 2, 3, 4, 5)
Measured to draw the current
through DOUT
10 12 14 V U
VOH2 DOUT Pch ON voltage(*1)
I
OH
=-50μA, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
C
TLD
= V
SS
VVR12
-0.5V VVR12
-0.1V V U
VOH3 DRAIN Pch ON volta ge(*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
SENS =VMP =4.0V
VVR12
-0.5V VVR12
-0.1V V V
VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V,
VCELLn=3.2V (n =2, 3, 4, 5)
VC1
-0.5 VC1
-0.3 V W
VOH5 CB2 Pch ON voltage
I
OH
=-50µA, V
DD
=V
C1
, V
C1
=4.5V,
VCELLn=3.2V (n =1, 3, 4, 5)
V
C2
-0.5
V
C2
-0.3
V W
VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V,
VCELLn=3.2V (n =1, 2, 4, 5)
VC3
-0.5 VC3
-0.3 V W
VOH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 5)
VC4
-0.5 VC4
-0.3 V W
VOH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 4)
VC5
-0.5 VC5
-0.3 V W
ILCOUT COUT pin off leak current
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
CTLC=VDD, COUT=-14V
-0.1 µA X
ICTLT CTLT Charge Current VDD=VC1, VCELLn=3.2V
(n=1, 2, 3, 4, 5) 145 205 264 nA Y
VDTLT CTLT detector threshold
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 4, 5)
VC3=VD1+0.2V
1.58 2.00 2.42 V Z
VRTLT CTLT released voltage
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
0.07 0.13 0.19 V Z
tLT Dis connection detection
Test Interval
CCTLT×(VDTLT-VRTLT)/ICTLT
CCTLT =3.3µF 21 30 39 s -
Vnochgn
CELLn charge inhibit
maximum voltage
(n=1,2,3,4,5)-for
R5432V4xxxB
VDD=VC1 1.100 V A
ISS1 Supply Currnt1
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=VDET1n-0.4V
(n=1, 2, 3, 4, 5)
12 30 µA a
ISS2 Supply Currnt2 VDD=VC1,COUT=OPEN
V
CELL
n
=
1.5V (n
=
1, 2, 3, 4, 5)
10 25 µA a
VCELLn=CELLn voltage n=1, 2, 3, 4, 5
(*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.
R5432V
NO.EA-263-160711
14
R5432VxxxBD Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1 Operating input voltage VDD-VSS 2 25 V -
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect falling edge of supply voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=3.5V→4.5V
0.7 1.0 1.3 s B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VCBRn
-0.050 VCBRn
Lower of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Detect rising edge of supply voltage
VREL2n
×0.975 VREL2n VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n
=
2, 3, 4, 5), V
CELL1=
1.5V
1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=33nF
89 128 167 ms -
tVREL2 Output delay of
release from overdischarge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising ed ge of supply voltage
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
VDET32
-0.055 VDET32 VDET32
+0.055 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Detect falling edge of supply voltage
VDET31
×0.50 VDET31
×0.75 VDET31
×.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS0.7V
2.0 3.0 4.0 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V
(n=2,3,4,5)
SENSE
=
0.4V, VMP
=
4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=3.3nF
7.3 10.8 14.7 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=3.3nF
1.25 1.80 2.40 ms -
tVREL3
Output delay of release from
Excess
discharge-cur rent T hreshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
15
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply v ol tage
Vshort
-0.12 VDET32
x1.67 Vshort
+0.17 V K
tshort
Output Delay of Sh o rt pr otection
VDD=VC1, VCELL
n =3.5V (n=1, 2,3,4,5)
SENS=0.0V2.0V, VMP=4.0V 180 300 550 μs K
VDET4 Excess char ge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld
V
DD
=V
C1,
V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→-1.0V
5 8 11 ms L
tVrel4
Output delay
of release from
Excess
charge-cur rent thr e sho ld
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
VDD
-0.3
VDD
+0.3
V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) 4.0 VDD/2
-0.5V V M
VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+1.0 V M
VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
VDD
-0.3
VDD
+0.3
V N
VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) 4.0 VDD/2
-0.5V V N
VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+0.3 V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50μA, V
DD
=V
C1
, C
TLD
=V
DD
VCELLn =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age IOL=50μA, VDD=VC1,
V
CELL
n =3.2V (n=1,2,3,4,5)
0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLC=VSS
VDD
-0.5 VDD
-0.1 V T
R5432V
NO.EA-263-160711
16
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VVR12 VR 12V output voltage(*1)
I
OH
=-5µA, V
DD
=V
C1
, C
TLD
=V
SS
,
VCELL=3.2V (n=1, 2, 3, 4, 5)
Measured to draw the current
through D
OUT
10 12 14 V U
VOH2 DOUT Pch ON voltage(*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLD= VSS
VVR12
-0.5V VVR12
-0.1V V U
VOH3 DRAIN Pch ON volta ge(*1)
I
OH
=-50μA, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
SENS =VMP =4.0V
VVR12
-0.5V VVR12
-0.1V V V
VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
VCELLn=3.2V (n =2, 3, 4, 5)
VC1
-0.5 VC1
-0.3 V W
VOH5 CB2 Pch ON voltage
I
OH
=-50µA, V
DD
=V
C1
, V
C1
=4.5V,
VCELLn=3.2V (n =1, 3, 4, 5)
V
C2
-0.5
V
C2
-0.3
V W
VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
VCELLn=3.2V (n =1, 2, 4, 5) VC3
-0.5 VC3
-0.3 V W
VOH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 5)
VC4
-0.5 VC4
-0.3 V W
VOH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 4)
VC5
-0.5 VC5
-0.3 V W
ILCOUT COUT pin off leak current
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
CTLC=VDD, COUT=-14V
-0.1 µA X
ICTLT CTLT Charge Current VDD=VC1, VCELLn=3.2V
(n=1, 2, 3, 4, 5) 145 205 264 nA Y
VDTLT CTLT detector threshold
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 4, 5)
VC3=VD1+0.2V
1.58 2.00 2.42 V Z
VRTLT CTLT released voltage
V
DD
=V
C1
, V
CELL
n=3.2V
(n
=
1, 2, 3, 4, 5)
0.07 0.13 0.19 V Z
tLT Dis connection detection
Test Interval
CCTLT×(VDTLT-VRTLT)/ICTLT
CCTLT =3.3µF 21 30 39 s -
ISS1 Supply Currnt1
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=VDET1n-0.4V
(n=1, 2, 3, 4, 5)
12 30 µA a
ISS2 Supply Currnt2
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=1.5V
(n=1, 2, 3, 4, 5)
10 25 µA a
VCELLn=CELLn voltage n=1, 2, 3, 4, 5
(*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.
R5432V
NO.EA-263-160711
17
R5432VxxxAD Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1 Operating input voltage VDD-VSS 2 25 V -
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect falling edge of supply voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=3.5V→4.5V
0.7 1.0 1.3 S B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect fa l l i ng edge of supply vol tage
VCBRn
-0.050 VCBRn
Lower of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Detect rising edge of supply voltage
VREL2n
×0.975 VREL2n VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n=2, 3, 4, 5), VCELL1=1.5V 1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=330nF
840 1200 1560 ms -
tVREL2 Output delay of release
from overdischarge
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
VDET32
-0.055 VDET32 VDET32
+0.055 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Detect falling edge of supply voltage
VDET31
×0.50 VDET31
×0.75 VDET31
×.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENSE=VSS0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V
(n=1,2,3,4,5) SENSE
=
V
SS
0.7V
3.5 5.0 6.5 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V
(n=2,3,4,5)
SENSE=0.4V, VMP=4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=330nF
700 1000 1300 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=330nF
7 10 13 ms -
tVREL3
Output delay of release from
Excess
discharge-cur rent T hreshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
18
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply vol t age
Vshort
-0.12 VDET32
x1.67 Vshort
+0.17 V K
tshort
Output Delay of Sh o rt pr otection
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENS=0.0V2.0V,
VMP=4.0V
180 300 550 μs K
VDET4 Excess char ge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld VDD=VC1, VCELLn =3.5V
(n=1,2,3,4,5) SENS=0.0V→-1.0V 5 8 11 ms L
tVrel4
Output delay
of release
from Excess charge-
current threshold
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
4.0 VDD/2
-0.5V
V M
VIL1 SEL1 pin “L” input voltage
V
DD
=V
C1,
V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V M
VIH2 SEL2 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V N
VIM2 SEL2 pin “M” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
4.0
V
DD
/2
-0.5V
V N
VIL2 SEL2 pin “L” input voltage
V
DD
=V
C,
V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
, C
TLD
=V
DD
VCELLn =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age
I
OL
=50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLC=VSS
VDD
-0.5 VDD
-0.1 V T
R5432V
NO.EA-263-160711
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Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VVR12 VR 12V output voltage(*1)
I
OH
=-5µA, V
DD
=V
C1
, C
TLD
=V
SS
,
VCELL=3.2V (n=1, 2, 3, 4, 5)
Measured to draw the current
through DOUT
10 12 14 V U
VOH2 DOUT Pch ON voltage(*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLD= VSS
VVR12
-0.5V VVR12
-0.1V V U
VOH3 DRAIN Pch ON volta ge(*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
SENS =VMP =4.0V
VVR12
-0.5V VVR12
-0.1V V V
VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
VCELLn=3.2V (n =2, 3, 4, 5)
VC1
-0.5 VC1
-0.3 V W
VOH5 CB2 Pch ON voltage
I
OH
=-50µA, V
DD
=V
C1
, V
C1
=4.5V,
VCELLn=3.2V (n =1, 3, 4, 5)
V
C2
-0.5
V
C2
-0.3
V W
VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
V
CELL
n
=
3.2V (n
=
1, 2, 4, 5)
VC3
-0.5 VC3
-0.3 V W
VOH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 5)
VC4
-0.5 VC4
-0.3 V W
VOH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 4)
VC5
-0.5 VC5
-0.3 V W
ILCOUT COUT pin off leak current
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
CTLC=VDD, COUT=-14V
-0.1 µA X
ICTLT CTLT Charge Current VDD=VC1, VCELLn=3.2V
(n
=
1, 2, 3, 4, 5)
145 205 264 nA Y
VDTLT CTLT detector threshold
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 4, 5)
VC3=VD1+0.2V
1.58 2.00 2.42 V Z
VRTLT CTLT released voltage
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
0.07 0.13 0.19 V Z
tLT Dis connection detection
Test Interval
CCTLT×(VDTLT-VRTLT)/ICTLT
CCTLT =3.3µF 21 30 39 s -
ISS1 Supply Currnt1
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=VDET1n-0.4V
(n=1, 2, 3, 4, 5)
12 30 µA a
ISS2 Supply Currnt2
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=1.5V
(n=1, 2, 3, 4, 5)
10 25 µA a
VCELLn=CELLn voltage n=1, 2, 3, 4, 5
(*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.
R5432V
NO.EA-263-160711
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OPERATION
VDET1n / Overcharge Detectors (n=1, 2, 3, 4, 5)
While the ce ll is char ged, the voltag e be tween VC1 pi n an d V C2 pin (v olt ag e of the Cell-1), the voltag e be tween VC2 pin and VC3
pin (voltage of the Cell-2), the voltage between VC3 pin and VC4 pin (voltage of the Cell-3), the voltage of VC4 pin and VC5 pin
(voltage of Cell-4), and the voltage between VC5 pin and VSS pin (voltage of the Cell-5) are super vised. If at least on e of the
cells’ voltage becomes equal or more than the overcharge detector threshold, the overcharge is detected, and COUT pin
connected to an external pull down resistance outputs "Hi-Z", and by turning off the external N-channel MOSFET by the pull-
down resister, charge cy cle stops.
BA/BB/BC ver.:
To reset the overcharge and make the COUT pin level to "H" again after detecting overcharge, in such condition that a time
when all the cells’ voltag es be come low er t han the overcharg e relea sed v oltage. T hen, th e output volta ge of COUT pin becomes
"H", and it makes an external N-channel MOSFET turn on, and charge cycle is available. The overcharge detectors have
hysteresis.
AD/BD ver.:
To reset the overcharge, when all the cell voltage b ecome low er than the released voltage from overcharge, COUT pin becomes
“H”, charge is acce ptable. Afte r detecting overcharge, by con nect ing a lo ad, and w hen all th e cell v olt age b eco me s lower than
the overcharge voltage detector threshold, COUT voltage becomes “H” and charge will be possib le.
Internal fixed out put delay times f or overcharge det ection an d relea se from overcharge exist. Ev en if one of cells' voltag e keeps
its level more than t he overc harge dete ctor thre shold, and the output delay time pas ses, overcharge voltage is de tec t ed. Even
if the voltage of ea ch cel l bec omes equal or higher than VDET1 if the se v ol tage s would be back to be lower than the overcharge
detector threshold within the output delay time, the overcharge is not detected. Besides, after detecting overchar g e, ea c h c e ll
voltage is lower than the overcharge detector released voltage, even if just one of cells' voltage becomes equal or more than
the overcharge released voltage within the released output delay time, overcharge is not released.
The output type of the COUT pin is P-channel open drain and "H" level of COUT pin is VDD pin voltage.
VDET2n / O ver di scharge Detectors (n=1, 2, 3, 4, 5)
While the cells are discharged, the voltage between VC1 pin and VC2 pin (the voltage of Cell-1), the voltage between VC2 pin
and VC3 pin (Cell-2 voltage), the voltage between VC3 pin and VC4 pin (Cel l-3 voltage), the voltage between VC4 pin and VC5
pin (Cell-4 voltage), and the voltage between VC5 pin and Vss pin (Cell-5 voltage) are supervised. If at least one of the cells’
voltage becomes equal or less than the overdischarge detector threshold, the overdischarge is detected and discharge stops
by the external discharge control N-channel MOSFET turning off with the DOUT pin being at "L".
The condition to release overdischarge voltage detector is that after detecting overdischarge voltage, all the cells' voltage
becomes higher than the overdischarge release d voltage, DOUT pin becomes “H” level, and by turning on the ex ternal N-channel
MOSFET, discharge becomes possible. The overdischarge detectors have hysteresis.
The output delay time for overdischarge detect is set with an external capacitor CCT1 connected to CT1 pin. If at least one of
the cells' voltage becomes down to equal or lower than the overdischarge detector threshold, and the voltage of each cell
would be back to higher than the overdischarge detector threshold within the output delay time, the overdischarge is not
detected. The output delay time for release from overdi scharge is also set internally.
After detecting overdischarge, supply current would be reduced and be into standby by halting unnecessary circuits and
consumption current of the IC itself is made as small as possible.
When a cell voltage equals to zero, if the voltage of each cell is lower than the charge inhibit maxim um voltage, charge is not
acceptable. All the cell voltages are higher than the charge inhibit maximum voltage, COUT pin becomes "H" and the IC allows
the system to charge.
The output type of DOUT pin is CMOS having "H" level around 12V of the internal regulator and "L" level of VSS.
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VDET3-n (n=1, 2) /Excess discharge-current Detector, Short Circuit Protector
When the charge and discharge is acceptable, SENS pin voltage is supervised, if the load is short and SENS pin voltage
becomes equ al or more than e xcess dischar ge current thre shold, and equal or less than the short detector t hreshold, the status
becomes excess discharge current detected condition. If SENS pin voltage becomes equal or more than the short circuit
detector threshold, the status becomes short circuit detected, then DOUT pin outputs "L" and by turning off the external
MOSFE T, the IC prevents the circ uit from flow ing large curr ent. The ex cess discharg e current dete ctor has tw o thresholds, and
each threshold has the output delay time. In terms of the output delay times, the delay time for the excess discharge current
detector 2 is set shorter than the excess discharge current 1.
The outp ut d elay t im es for the excess d is char ge-c urr ent de t e ctors are set by an external capacitor C CT2 connected to CT2 pin.
A quick recovery of SENS pin level from a value between the excess discharge current detector and the short circuit detector
threshold within the delay time, may keep the status as before excess discharge current detected. Output delay time for the
release from excess dischar ge -curr en t detect ion is al so set in ter nal ly.
When the short circuit protector is enabled, the delay time exists as well as other protection circuits.
Between the drain of the ex ternal FE T connected to D R AIN p in, a nd the drain of an external FET connected to COUT a nd DOUT,
an external resistor should be mounted to release from overdischarge.
After an ex cess d ischar ge-curr ent or short circu it protec tio n is detected , an ex ter nal FET co nnect ed to D RAIN pin t urn s on and
the resistance of release from the excess-discharge current is connected to VSS. After detecting the excess discharge current
or short circuit, load is removed and opened, VMP pin level is connected to the VSS pin level, through the pulled down resistor
for release fr om excess disc harge, and w hen the VMP pin becomes equal or les s than VREL3, the circu it is released fro m excess
discharge or short automatically. When the excess-discharge current is released, the external FET connected to DRAIN pin
turns off and resisters for the release from excess-discharge current status is separated from VSS.
VDET4/ Excess charge-current detector
When the battery pack is chargeable and discharge is also possible, VDET4 senses SENS pin voltage. For example, in case
that a b attery pack is c har ge d by an ina ppr opr iate charg er, e xcess current fl ows, then t he voltage of SENS pin becomes e qual
or less than the excess charge-current detector threshold, then the output of COUT pin becomes "Hi-Z", and by turning off the
external N-channel MOSFET with the pull-down resister, flowing excess current in the circuit is prevented.
Output delay of the excess charge current is internally fixed. Even the voltage level of SENS pin becomes equal or low er t han
the excess charge-current detector threshold, if the voltage becomes higher than the excess charge current threshold within
the delay time, the excess charge current is not detected. Output delay for the release from exces s charge current exists as
well as other protection circuits.
VDET4 can be released by disconnecting a charger and connecting a load and when the VMP pin voltage becomes equal or
more than VREL3.
Operation against cell unbalance
If one of the cells detects overcharge and eit her of the c ell s detects overdischarge, b ot h out puts of COUT and DOUT bec ome "L ".
CTLC/CTLD pin
If the ICs are stacked and function with two chips, by connecting COUT and CTLC, and connecting DOUT and CTLD shown as
in the ex ample circuit (10-cell protection), overcharge, overdischarge, open-wire state can be trans ferred. If stacked connect ion
is unnecessary, CTLC/CTLD pins must be set at VSS volta ge lev el.
If CTLC/CTLD pins are in the range of VSS ± 0.3V, or larger than VDD+2.0V, the IC operates in normal way.
By forcing VDD voltage level (between VDD-0.3V and VDD+0.3V) to CTLC pin, the output of COUT connected an external pull-
down resister can be forcibly set to "L". However, if short circuit is detected, the output of COUT cannot be made "L".
By forcing VDD voltage level (between VDD-1.0V and VDD+3.0V) to CTLD pin, the output of DOUT can be forcibly set to "L".
R5432V
NO.EA-263-160711
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If the volt age in the range fr om Vss+0.3V to V DD-0.3V is for ced to the CTLC/C TLD pin, the op eration may chan ge by the volt age
between VDD and VSS.
The voltage in the range from VSS + 0.3V to VDD-0.3V should not be forced to CTLC/CTLD continuously.
CTL pin input and outputs of COUT and DOUT
CTLC/CTLD pin input
C
OUT
/D
OUT
external FET
equal or more than V
DD
+2.0
Normal Operation
V
DD
-0.3V to V
DD
+0.3V
Forced off
VSS-0.3 to VSS+0.3
Normal Operation
Open, other than the above
Indefinite
SEL1, SEL2 pin
SEL1 and SEL2 pins are used as switch over 3-cell protector , 4-cell protector and 5-cell protector . If 4-cell protection is selected,
by forcing VSS voltage level to SEL1 pin and forcing VDD voltage
level to SEL2 pin, the operation of 5th cell's protection circuit, the signal is shut down, therefore, even if the VC5 is shortened
to GND, overdischarge is not det e cted and oper ates as a 4-cell protector IC.
To select 3-cell protection mode, by forcing VDD voltage level to SEL1 pin, VSS voltage level to SEL2 pin, the operation of 5th
cell and 4th cell stop, and the signal is cut off. Therefore, if VC4, VC5 and VSS are shorted, overdischarge is not detected and
operates as a 3-cell protector IC.
SELn pins must be set as VDD v oltage or VSS volt age level.
Depending on the combination of SEL1 pin and SEL2 pin input, delay time shortening function mode 1 (down to 1/100 delay)
or delay time shortening function mode 2 (overcharge detector threshold delay time is shortened into 4ms) is realized.
Middle voltage of the table below means in the range from 4.0V to VDD/2-0.5V.
SEL1 and SEL2 pin input combination, and the operation mode
SEL1 pin input
SEL2 pin input
Operation Mode
High
High
5-cell protector
Low
High
4-cell protector
High
Low
3-cell protector
Low
Low
Delay shortening mode 1 for 5-cell protector
Low
Middle
Delay shortening mode 1 for 4-cell protector
Middle
Low
Delay shortening mode 1 for 3-cell protector
Middle
Middle
Delay shortening mode 2 for 5-cell protector
Middle
High
Delay shortening mode 2 for 4-cell protector
High
Middle
Delay shortening mode 2 for 3-cell protector
CT1, CT2 pin
CT1 and CT 2 pin s are use d for set ting the output delay time of overdischarge (tVDET2), the excess discharge current 1 (tVDET31),
and the excess discharge current 2 (tVDET32) by connecting external capacitors CCT1 and CCT2.
tVDET2 can be set with CT1 pin. tVDET31 and tVDET32 can be set with CT2 pin.
(1) tVDET2 external capacitor CCT1 setting
tVDET2 can be set as in the next formula.
Delay time code : A tVDET2(msec) = 3.64 × CCT1(nF)
Delay time code : B tVDET2(msec) = 3.88 × CCT1(nF)
R5432V
NO.EA-263-160711
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(2) tVDET31 and tVDET32 external capacitor CCT2 setting
tVDET31 and tVDET32 can be set as in the next formulas.
Delay time code : A tVDET31(msec) = 3.05 × CCT2(nF)
tVDET32(msec) = tVDET31/100
Delay time code : B tVDET31(msec) = 3.26 × CCT2(nF)
tVDET32(msec) = tVDET31/6
Cell balance function CB circuit-n (n=1,2,3,4,5)
While a battery is being charged, and the cell voltage is beyond the cell balance voltage
VCBDn (n=1,2,3,4,5) , aga inst the ce ll w hich be com es e qua l o r more t han t he cel l ba lan ce v o ltage V CBDn, t he o utpu t of CB n pin
(n=1,2,3,4,5) becomes "H" and an external N-channel transistor for cell balance turns on, and discharge path is connected in
parallel with the cell and charge c urrent i s reduced . When t he ce ll volta ge becomes equal or less t han th e cell bala nce re leased
voltage VCBRn (n=1,2,3,4,5), then cell balance function is released and the output of CBn pin (n=1,2,3,4,5) becomes "L".
The resister used for the discharge path, absolute ratings must be cared.
If the cell balance function is unnecessary, CBn pin must be left open.
Open-wire Detec tor Function
Open-wire detect of VDD (VC1) and VSS for 5-cell protector
If VDD line is cut, the voltage between VC1 and VC2 is less than 0V.
If VSS line is cut, the voltage between VC5 and VSS is less than 0V.
The voltage is detected by the 0V-detector circuit.
If open-wire is detected, the P-channel open drain of the COUT turns off.
Open-wire detector for VC2, VC3, VC4, VC5 for 5 -cell protecti on
When using the 5-cell protection, the voltage of VDD (= VC1) becomes lower than VC2 voltage if the connection between the
battery and VDD (= VC1) i s open. And, the voltage of VSS becomes higher than VC5 voltage if the connection between the
battery and VSS is open. The voltage variation is detected as “Open-wire”. When the open-wire is detected, the P-channel
open drain of the COUT turns of f.
In case of the 3.3µF capacitor is attached to the CTLT pin, open-wire detector operates every 30 seconds. The built in switch
of VC1, VC3, VC5 cell, and the switch attached to the VC2 and VC4 turn on alternatively by the even_sw and the odd_sw
signal.
The inter nal i mped an ce of t he cell whose sw itch turn s on become s l ow for about 1.2 s ec ond s by t he low res ista nc e connected
to the switch. If the wire is not broken, the capacitor of the CTLT is discharged and the next cycle starts for checking.
While th e w ir e is bro ken , the differe nce of t h e internal i mpe da nce of the IC gen er ate d by the sw itch' s tuni ng on m ake s V C s hi ft
and dete cted by the compar ator for VDET1. If the open-wire is detected a nd the conditio n continues for a bout 4ms, then even_sw
and odd_sw turn off and the capacitor of CTLT is discharged and the P-channel open drain of the COUT turns off . While t he
overdischar ge voltage is detected, the open-wire of VC2, VC3, VC4 and VC5 does not operate.
Open-wire detector for VDD (VC1) and VSS f or 10-cell protection
If the ICs are connected in cascade, the VDD of the high side IC and VSS (VSS2) of the low side IC, the open-wire detecto r is
able to work as well as 5-cell prot ect ion ty pe.
As for the VSS (VSS1) of high side IC and VDD (VDD2) of low side IC, if they are co nnected w ith common one w ire from the batt ery,
and if the wire is broken, two lines, VSS1 and VDD2's wire are broken, as a result, open-wire may not be able to be detected
correctly.
As for the VSS1 and VDD2, connect with two wires so that either VSS1 or VDD2 is connected to the battery, and by the pull-down
R5432V
NO.EA-263-160711
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resistance of COUT of high side is connected to the VDD2 of the low s ide IC, if either of VSS1 or VDD2 breaks the wire, the open-
wire detector is able to operate.
Refer to the typical application circuit. (10-cell, cell-balance, open-wire detector are in use.)
*Limitation of the open-wire detec to r for VC2, VC3, VC4, VC5.
If the open-wire detecting function is necessary, confirm the limitations below;
External components must be
CCTLT=3.3µF
CCT1 range: from 0.47µF to 1.0µF
CVCx=0.1µF
Even if the protection IC does not detect overdischarge, if the cell voltage is low, depending on the distribution of the ICs, cell
balance state, the operating environment, the characteristics of the external components, open-wire function may not operate
correctly.
During the delay time of the overcharge voltage, if the open-wire is detected, the overcharge detect operatio n is once cancelled,
and the open-wire operat ion will b e dominant. During the open-wire detecti on, even if the cell v oltage be comes equal or more
than the overcharge det ector threshold, overcharge is not de tecte d. In this ca se, after detecting open-wire operation, i f the cell
voltage is still equal or more than the overcharge detector threshold, overcharge detector op eration starts again. For this re ason,
overcharge detector output delay time may longer than 1s. (Refer to the timing chart.)
During the overdischar ge delay time, if the open-wire detector's opera tion starts, the overdischarge detector's operation is once
cancelled and the open-wire operation will be dominant. During the open-wire, detector's operation is active, even if the cell
voltage becomes equal or less than the overdischarge detector threshold, the overdischarge detector does not start. In this
case, after detecting open-wire operation, if the cell voltage is still equal or less than the overdischarge detector threshold,
overdischarge detector operation starts again. For this reason, the output delay time of overdischarge detector may be longer
than the preset value. (Refer to the timing chart.)
Charge Inhibit Detector Circui t Vnochg-n (n-1,2,3,4,5)
In the R5432VxxxBB, for each cell, charge inhibit detector is built-in. If either of cellsvoltage is lower than the
charge inhibit voltage, when a charger is connected to the battery pack, charge inhibit is detec ted and C OUT
with external pull-down becomes Hi-Z” and an external MOSFET turns off by the pull-down resistance and
charge stops.
When the charge inhibit is detected, the cell voltage which is inhibit charge is equal or lower than the
overdischarge detector threshold, therefore the output of COUT becomes Hi-Z”, and the output of DOUT
becomes “L”, and both external FETs turn off.
R5432V
NO.EA-263-160711
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TIMING CHART
Overchar ge, Excess charge current
V
DET1 1
V
REL11
VC1-VC2
t
tV
REL1
tV
DET1
tV
DET1
tV
REL1
tV
DET4
V
DD
VMP
COUT
tV
REL4
t
V
DET1 2
V
REL12
VC2-VC3
t
V
DET1 3
V
REL13
VC3-VC4
t
V
DET1 4
V
REL14
VC4-VC5
t
0
Charge/
Discharge
current
t
charge
discharge
connect charger
connect
load
connect
charger
charger open
& connect load
V
SS
SENS
V
DET3 1
V
DET4
t
V
DET1 4
V
REL14
VC5-Vss
t
V
SS
VMP
V
DET3 1
V
DET4
t
open
connect charger
connect load
R5432V
NO.EA-263-160711
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Overdischarge, Excess discharge current1/2, Short detector
VR12V
DOUT
VSS
t
VDET2 1
t
VDET2 1
t
VREL21
t
VDET3 1
tshort
t
VDET3 2
t
VREL3
t
VREL21
t
VREL3
t
VREL3
t
VREL21
VDET2 1
V
C1-VC2
t
0
t
VREL22
VDET2 2
V
C2-VC3
t
VREL23
VDET2 3
V
C3-VC4
t
VREL24
VDET2 4
V
C4-VC5
t
VREL24
VDET2 4
V
C5-Vss
t
connect
charger
connect
load
open
open
open
connect
load
connect
load
connect
load
connect
charger
connect
load
open
VSS
VDET4
SENS
VDET3-1
VDET3-2
Vshort
t
VSS
VMP
t
Charge/
Discharge
current
charge
discharge
R5432V
NO.EA-263-160711
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CELL BALANCE OPERATION
In the case that CELL1 operates CELL balance
V
DET11
V
REL11
・VC1-VC2
t
・CB1-VC2
 (Voltage
difference)
t
VDD
COUT
0
・Charge/
Discharge
current
t
Charge
current
Discharge
current
charge current
bypass
current
charge current -
bypass current
CB
REL1
CB
DET1
discharge
current +
bypass current
idle
tV
DET1
discharge
current
Cell balance operation
Over charge state
t
R5432V
NO.EA-263-160711
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Balance operation with CELL1 and CELL2
VDET1x
VREL1x
Cellx
voltage
t
CBx
output
t
VDD
COUT
output
0
Charge/
Discharge
current
t
Charge
current
Discharge
current
charger
CBRELx
CBDETx
idle
t
VDET1
Over charge state
charger - bypass
charger - bypass
idle
bypass
bypass
charger
Cell1
Cell2
CB1 operating
CB2 operating
Cell1
Cell2
t
R5432V
NO.EA-263-160711
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Open-wire Detection
Open-wire detector's operation of VC2, VC3, VC4, and VC5 for 5-cell protector
In case of the 3.3µF capaci tor is attached t o the CTLT pin, open-wire detec tion oper ates ever y 30 seconds. The
built in switch of VC1, VC3, VC5 cell, and the switch attached to the VC2 and VC4 turn on alternatively by the
even_sw and the odd_sw signal.
The internal impedance of the cell whose switch turns on becomes low for about 1.2 seconds by the low resistance
connected to the switch in serial. If the wire is not open, the capacitor of the CTLT is discharged and the next cycle
starts for checking.
While the wire is open, the difference of the internal impedance of the IC generated by the switch's tuning on
makes VC shift and detected by the comparator for VDET1. If the open-wire is detected and the condition
continues for ab out 4m s, then e ven_s w and o dd_s w tu rn off and t he capac itor of CTLT is disc harged an d th e P-
channel open drain of the COUT turns off. While the overdischarge voltage is detected, the open-wire of VC2,
VC3, VC4 and VC5 does not operate.
The timing chart of open-wire of VC2, VC3, VC4, VC5 is shown below:
1) The change of VC is not always increasing. Depending on the cell balance or the internal impedance, the VC incre as es or
decreases.
CTLT Pin
COUT Output
(VC3 at open-wire
1.2seconds (CTLT = 3.3 µF)
At V
C3
at
Open-wire
V
C3
Voltage
odd_sw
(IC Internal signal)
even_sw
(IC Internal signal
Open-wire
VDET1det ect i on level
30seconds (CTLT = 3.3µF)
1)
0V
0V
V
C3
, V
C5
open-wire
VC2, VC4 open-wire
VC3, VC5 open-wire
R5432V
NO.EA-263-160711
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Overchar ge det ector operation and Open-wire detector operation
The output delay time of overcharge is normally set at 1s, however, the effect of the open-wire detector, the output delay time
may be longer than 1s.
Case 1: During the operation of detecting overcharge, if the open-wire is detected, once the operation of the overcharge
detector is cancelled, and after detecting the open-wire, the operation of the overcharge detector starts again.
Case 2: During the operation of the open-wire detector , if the c ell voltage becomes more than the overcharge detector thre shold,
after detecting the open-wire, the operation of the overcharge detector starts.
The timing chart shown below is for the operation of t he case 1. When th e overcharge is det ected, internal n ode "vd1" becomes
"H", then, if the open-wire is detected, the internal node "It_en" becomes "H", then "vd1" signal returns to "L". After the open-
wire detector is released, then "It_en" returns to "L", then the "vd1" becomes "H", and overcharge detector's function restar.
Open-wire test operation starts, overcharge detector's operation is cancelled.
Overcharge detector's maximum output delay : Max_tVDET1 = BCtVDET1.
COUT
vd1
(internal signal)
lt_en
(internal s i gnal )
V
CELL
n
CTLT
tV
DET
1
BtVDET1
Check
Open-wire
tLT
t
t
t
t
t
H
L
B
C
VDET1n
A
(n=1,2,3,4, 5)
R5432V
NO.EA-263-160711
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Overdischarge operation and disconnection detector operation
The output delay time of the overcharge detector can be set by an external capacitor, but the delay time might be longer than
the present value due to the open-wire detector's operation.
1. During the operation of detecting overdischarge, if the open-wire is detected, once the operation of the over
discharge detector is cancelled, and after detecting the open-wire is detected, once the operation of the
2. Overdischarge can not be detected during disconnection detection. It can operate after disconnection detect.
The timing chart which start to detect disconnect during overdischarge is displayed as follows.
The interna l s ign al "vd1" become "H" after it is equal or less t han overdischarg e thresh old. It comes bac k "L" after which is the
detecting disconnection internal signal become "H". "vd1" become "H" after "It_en" comes back "L". . Overd ischar ge can b e
detected.
Check
Open-wire
V
DET2
n
DOUT
vd2
(internal si gnal )
lt_en
(internal s i gnal )
VCELLn
(n=1, 2, 3, 4, 5)
C
TLT
tVDET2
Bt
VDET2
tLT
t
t
t
t
t
H
L
B
C
A
Overcharge detecting is cancelled, after operating disconnection test.
So max output of overcharge delay : Max_tVDET2 = BCtVDET2
R5432V
NO.EA-263-160711
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TYPICAL APPLIC ATION AND TECHNICAL NOTES (R5432VxxxBA)
Circuit example
(for -5cell protection, detecting disconnection, at operating cell-balance function)
When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows
through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between
Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those
current enough.
C
VC1
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
VSS
VSS
CT1
CT2
CTLT
R
VC1
R
VC2
R
VC3
R
VC4
R
VC5
R
CB1
R
CB2
R
CB3
R
CB4
R
CB5
C
VC2
C
VC3
C
VC4
C
VC5
C
VDD
R
VDD
C
CT1
C
CT2
C
CTLT
R
SENS
R
DRAIN
R
CO1
R
CO2
R
VMP
R
SE
ZD
1
R5432V
NO.EA-263-160711
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Circuit example
(for 4cell protection, detecting disconnection, at not operating cell-bal a n ce fun ct ion)
When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows
through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between
Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those
current enough.
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
VSS
VSS
CT1
CT2
VSS
CTLT
C
VC1
R
VC1
R
VC2
R
VC3
R
VC4
R
CB1
R
CB2
R
CB3
R
CB4
C
VC2
C
VC3
C
VC4
C
VDD
R
VDD
R
SENS
R
DRAIN
R
CO1
R
VMP
R
SE
R
CO2
C
CT1
C
CT2
ZD
1
R5432V
NO.EA-263-160711
34
Circuit example (for 3cell, detecting disconnection, at not operating cell-balance function)
When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows
through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between
Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those
current enough.
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
VSS
VSS
CT1
CT2
VSS
CTLT
C
VC1
R
VC1
R
VC2
R
VC3
C
VC2
C
VC3
C
VDD
R
VDD
C
CT1
C
CT2
C
CTLT
R
SENS
R
DRAIN
R
CO1
R
CO2
R
VMP
R
SE
ZD
1
R5432V
NO.EA-263-160711
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Circuit example (for 7cell, detecting disconnection, at operating cell-balance function)
If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If
they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. When the FET con n ec ted
to Cout is OFF and the load is connected between Pack + and Pac k-, the discharge current flows through the parasitic diode
of that FET, and when t he FET connected to Dout is OFF a nd the charger is conn ect ed b etween Pack+ and Pa ck-, the charge
current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough.
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
Protect IC
VC1
VC2
VDD
Cell4
CB1
Cell5
Cell6
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
CTLT
C
VC1
R
VC1
R
VC2
R
VC3
R
VC4
R
CB1
R
CB2
R
CB3
C
VC2
C
VC3
C
VDD1
R
VDD1
C
CT11
C
CTLT1
C
VC6
R
VC6
R
VC7
R
VC8
R
CB6
R
CB7
R
CB8
C
VC7
C
VC8
C
VDD2
R
VDD2
C
CT12
C
CTLT2
C
CT22
R
SENS
R
DRAIN
R
CO1
R
CO2
R
VMP
R
SE
R
CTLD
R
CTLC
R
UCO
ZD
1
ZD
2
VSS
VSS
Cell7
R
CB9
C
VC9
R
VC9
R5432V
NO.EA-263-160711
36
Circuit example (for 10cell, detecting open-wire, with cell-balance function)
If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If
they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation.
When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack-, the discharge current flows
through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between
Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those
current enough.
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
Protect IC
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
CTLT
CVC1
RVC1
RVC2
RVC3
RVC4
RVC5
RCB1
RCB2
RCB3
RCB4
RCB5
CVC2
CVC3
CVC4
CVC5
CVDD1
RVDD1
CCT11
CCTLT1
CVC6
RVC6
RVC7
RVC8
RVC9
RVC10
RCB6
RCB7
RCB8
RCB9
RCB10
CVC7
CVC8
CVC9
CVC10
CVDD2
RVDD2
CCT12
CCTLT2
CCT22
RSENS
RDRAIN
RCO1
RCO2
RVMP
RSE
RCTLD
RCTLC
RUCO
ZD1
ZD2
R5432V
NO.EA-263-160711
37
Circuit example (for 10-cell protection with cell-balance, open-wire, overcharge hysteresis
cancellation: AD/BD ver.)
If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If
they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation.
Protect IC
Protect IC
C
CT22
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
CTLT
C
VC1
R
VC1
R
VC2
R
VC3
R
VC4
R
VC5
R
CB1
R
CB2
R
CB3
R
CB4
R
CB5
C
VC2
C
VC3
C
VC4
C
VC5
C
VDD1
R
VDD1
C
CT11
C
CTLT1
C
VC6
R
VC6
R
VC7
R
VC8
R
VC9
R
VC10
R
CB6
R
CB7
R
CB8
R
CB9
R
CB10
C
VC7
C
VC8
C
VC9
C
VC10
C
VDD2
R
VDD2
C
CT12
C
CTLT2
R
SENS
R
DRAIN
R
CO1
R
CO2
R
VMP
R
SE
R
CTLD
R
CTLC
R
UCO
ZD
1
ZD
2
R
OP1
R
OP2
R
OP3
R
OP5
R
OP4
R
OP7
R
OP6
R
OP8
Q
OP1
M
OP1
M
OP2
M
OP3
M
OP4
R5432V
NO.EA-263-160711
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External parts ratings
Symbol
Typ.
Unit
Range
Remarks
RVDD
330
Ω
330 to 1000
1
RVC1
330
Ω
330 to 1000
2
RVC2
330
Ω
330 to 1000
2
R
VC3
330
Ω
330 to 1000
2
RVC4
330
Ω
330 to 1000
2
RVC5
330
Ω
330 to 1000
2
RCB1
100
Ω
40 or more
3
R
CB2
100
Ω
40 or more
3
RCB3
100
Ω
40 or more
3
RCB4
100
Ω
40 or more
3
RCB5
100
Ω
40 or more
3
RSENS
100
1.0 or more
It is determined by the value of over current
R
SE
10
1 to 10
4
RDRAIN
5
5
5 RDRAIN<VDET31x(RCO1+RCO2)/50
RCO1
1
5
5
RCO2
2
5
5
R
VMP
10
0.01 to 10
6
R
CTLC
1
1 to 10
R
CTLD
1
1 to 10
RUCO
3
0.1 to 10
7
CVDD
1
µF
0.1 to 1
1
CVC1
0.1
µF
0.1
2
C
VC2
0.1
µF
0.1
2
CVC3
0.1
µF
0.1
2
CVC4
0.1
µF
0.1
2
CVC5
0.1
µF
0.1
2
CCT1
0.47
µF
0.01 to 1.0
8
CCT2
0.0033
µF
0.0022 or more
9
CCTLT
3.3
µF
3.3
10
ZD1
30
V
30 or less
11
ROP1
10
k
10 or more
Input resistance of QOP1
ROP2
10
M
5 or more
ROP3
10
M
5 or more
ROP4
10
M
5 or more
ROP5
10
M
5 or more
ROP6
20
M
10 or more
ROP7
10
M
5 or more
MOP1
Consider the Voltage rating of VGS and VDS
MOP2
Consider the Voltage rating of VGS and VDS
MOP3
Consider the Voltage rating of VGS and VDS
MOP4
Consider the Voltage rating of VGS and VDS
QOP1
Consider the Voltage rating of VGS and VDS
Please refer to the external circuits of next page for "" of remarks
Please confirm "Precautions before Use".
R5432V
NO.EA-263-160711
39
Technical Notes on External Circuits and Components
*1) T he voltage flu ctuation is st abiliz ed w ith RVDD and CVDD. If a small RVDD is set, in the case of the large transi ent may happen
to the cell voltage, by the flowing current, the IC may be unstable. If a large RVDD is set, by the consumption current of the IC
itself, the voltage difference between VDD pin and VC1 pin is generated, and unexpected operation may result. Therefore, the
appropriat e value range o f RVDD is from 330 to 1k. To make a stable operat ion of the IC , the appropr iate valu e range of C VDD
is from 0.1µF to 1.0µF.
*2) RVC1 to RVC10, CVC1 to CVC10 stabilize the voltage fluctuation. If large RVC1 to RVC10 is set, the detector threshold will be high
because of the internal conduction current of the IC. The operation error of open-wire detector function may happen easily by
the distr ibution of the IC s or environme nt. If small RVC1 to RVC10 is set, the ef fect by no ise will be lar ge. Therefor e the approp riate
value range of RVC1 to RVC10 is from 330 to 1k. To make stable oper atio n, use 0.1µF as CVC1 to CVC10.
*3) When the c ell balance func tion is nec essary, RC B1 to RCB10 must be chosen carefully w ith considering the bypass current,
and consumption power by the bypass current, and the external MOSFET. Especially, if a small resistance (to set the large
bypass current) is set, fully evaluation is necessary. If a large resistance (to set the small bypass current) is set, the time for
cell balance will be long.
*4) When the cascade co nnect ion is use d, if shor t circu it is ha ppened, by the shor t current and the R SENS enlar ges the v oltage,
and as a r e sult, i f t he v oltag e of SE NS pin be co mes larger tha n t h e V DD of the IC , during the short c ircu it output de lay ti me, the
current flows into SENS pin. Therefore, if a small RSE is set, a large current may flow into SENS pin. If a large RSE is s e t, t he
overcurrent detector threshold may shift. Therefore the appropriate value is around 10k.
*5) Choose appropriate values for RDRAIN, RCO1, and RCO2 to satisfy the next formula, otherwise, the release from excess
discharge current and short may be impossible.
RDRAIN<VDET31x(RCO1+RCO2)/50
If small RCO1 or RCO2 is set, when the output of COUT is "H", the consumption current of protection circuit board increases. If
large RCO1 or RCO2 is set, when th e outp ut of COUT is "Hi-Z", the speed f or pul l-down the gate of the charge FET becomes slow
and turning off the FET will be slow. Not only that, by dividing between the "Hi-Z" output and the resistance, turning off the
charge FET may be diffi c ult.
If a small RDRAIN is set, when the excess discharge current and short circuit is detected, the large current may flow until the
load is removed.
*6) In terms of RVMP, when the cascade connection is made, if DOUT turns off, VMP pin is pulled up via RVMP to the top cell. In
this case, the current flows via RVMP and the internal diode, therefore, appropriate value must be chosen. If the cascade
connection is not use d, around 10k is ac ceptable.
*7) Set RUCO to satisfy RUCO=RCO1+RCO2. If a extremely lar ge resistan ce is set, w hen the output of COUT is "Hi-Z", by the divi ding
resistance, CTLC pin may not be pulled down. If a small resistance is used, when the output of COUT is "H" , t h e c on sum pt i on
current via RUCO increases.
*8) If the open-wire detector function of VC2 to VC5 is used, use 0.47µF to 1µF as CCT1. If the open-wire detector function is
unnecessary, use a capacitor of 0.01µF or more.
*9) If a too small CCT2 is set, excess discharge current detector output delay time 2 becomes shorter than the short circuit
output delay time. Therefore, use a capacitor with 0.0022µF or more.
R5432V
NO.EA-263-160711
40
*10) If the open-wire dete ctor o f VC2 to VC5 is used, use 3.3µF as CCTLT. If the open-wire dete ctor of VC2 to VC5 is not ne cess ary,
pull down to VSS.
*11) Consid ering t he break do w n of the resistor s and ca pacit ors to stabi lize the f luctuat ion o f the voltag e, to av oid that th e hig h
voltage is directly forc ed to the IC, adding a zener diode is our recommendation. Connect the zener diode between VDD pin of
the IC and VSS pin directly. (Refer to the typical application circuits.)
To set the number of connecting cells, SEL1/SEL2 pin must be connected to VDD level. In these cases, connect the pin inside
the filter for stabilizing VDD pin voltage. If SEL1/SEL2 is connected outside the filter, during the operation, the voltage
difference between SEL1/SEL2 and VDD may be generated, and unstable operation or excess current flow may result.
The typical application circuit diagrams are just examples. This circuit performance largely depends on the PCB layout and
external components. In the actual application, fully evaluation is necessary.
Overvoltage and the over current beyond the absolute maximum rating should not be forced to the protection IC and external
components. Especially, if the pack+ and Pack- are short, although the short protection circuit is built-in the IC, but during the
output delay time, large current may flow through the FET. By the current during the output delay, in order not to destruct the
FET, choose the FET with enough current rating.
Ricoh cannot assume r esponsi bility for u se of a ny circuitr y other tha n circuitr y entire ly embod ied in a Ric oh product. If technical
notes are not complied with the circuit which is u sed Ricoh product, Ricoh is not responsible for any da mages and any accidents.
To connect the protection IC and cells, connect VSS pin first. If the connect order is wrong, by flowing unexpected current, the
IC may be damaged.
If charge control FET and discharge control FET are connected in serial, if the control FET for charge turns off and discharge
big current, or w hen the FET for disc harge turns of f and if ch arge w ith big current is done w ithout dischar ge control FET turning
off, big current flows through the parasitic diode of the FET, the FET may be burnt. To avoid this, separate the charge and
discharge current path and when the FET turns off, in order not to flow large current through parasitic diode, choose an FET
with large current capacity.
R5432V
NO.EA-263-160711
41
TEST CIRCUITS
A
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
V
V
V
B
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
Cout
C
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
V
V
V
D
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
V
V
V
OSCILLOSCOPE
R5432V
NO.EA-263-160711
42
E
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
A
F
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
G
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
H
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
R5432V
NO.EA-263-160711
43
I
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
A
K
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
L
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
J
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
R5432V
NO.EA-263-160711
44
O
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
M
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
P
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
N
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
R5432V
NO.EA-263-160711
45
Q
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
S
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
T
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
R
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
V
V
V
V
R5432V
NO.EA-263-160711
46
U
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
V
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
W
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
V
X
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
A
V
V
V
V
V
R5432V
NO.EA-263-160711
47
Y
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
Cout
A
Z
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
Cout
V
VC1
VC2
VDD
CB1
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
DRAIN
SEL1
SEL2
CTLD
CT1
CT2
CTLT
A
a
A
R5432V
NO.EA-263-160711
48
TYPICAL CHRACTERSTICS
Part1. Temperature Characteristics
1) Overcharge voltage threshold (CELLn) 2) Overcharge Released Voltage (CELLn)
3) Overcharge Detector Delay 4) Released from Overcharged Delay time Temperature
5) CELL balance detector (CELLn) threshold 6) CELL balance released Voltage (CELLn)
R5432V404BA
4.22
4.23
4.24
4.25
4.26
4.27
4.28
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDET1n(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
4.07
4.08
4.09
4.10
4.11
4.12
4.13
-60 -40 -20 020 40 60 80 100
Ta (°C)
VREL1n(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVDET1(sec)
V
CELLn
=3.2V, V
CELL1
=3.2V->4.5V
n=2, 3, 4, 5
R5432V404BA
10
12
14
16
18
20
22
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVREL1(msec)
V
CELLn
=3.2V, V
CELL1
=4.5V->3.2V
n=2, 3, 4, 5
R5432V404BA
4.17
4.18
4.19
4.20
4.21
4.22
4.23
-60 -40 -20 020 40 60 80 100
Ta (°C)
CBDETn(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
4.17
4.18
4.19
4.20
4.21
4.22
4.23
-60 -40 -20 020 40 60 80 100
Ta (°C)
CBRELn(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
49
7) Overdischarge Detector Threshold (CELLn) 8) Released Voltage from overdischarge (CELLn)
9) Output Dela y time of Overdischarge (CELLn) 10) Output Delay Time of Released from
Overdischarge (CELLn)
11) Excess Discharge Current Detector Thershold1 12) Excess Discharge Current Detector Thershold2
R5432V404BA
2.47
2.48
2.49
2.50
2.51
2.52
2.53
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDET2n(V)
VCELLn=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
2.97
2.98
2.99
3.00
3.01
3.02
3.03
-60 -40 -20 020 40 60 80 100
Ta (°C)
VREL2n(V)
VCELLn=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
60
80
100
120
140
160
180
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVDET2(msec)
V
CELLn
=3.2V, V
CELL1
=3.2V->1.5V, C1=33nF
n=2, 3, 4, 5
R5432V404BA
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVREL2(msec)
V
CELLn
=3.2V, V
CELL1
=1.5V->3.2V
n=2, 3, 4, 5
R5432V404BA
0.17
0.18
0.19
0.20
0.21
0.22
0.23
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDET31(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
0.54
0.56
0.58
0.60
0.62
0.64
0.66
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDET32(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
50
13) Short Detector Threshold 14) Excess discharge Current Detector Output Delay Ti me 1
15) Excess discharge Current detector Output Delay Time2 16) Short Detector Output Delay Time
17) Excess discharge Current released delay time 18) Excess charge Current Detector Threshold
R5432V404BA
0.70
0.80
0.90
1.00
1.10
1.20
1.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
Vshort(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
4
6
8
10
12
14
16
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVDET31(msec)
VCELLn=3.2V, SENS=VSS->0.4V, C2=3.3nF
n=1, 2, 3, 4, 5
R5432V404BA
1.2
1.4
1.6
1.8
2.0
2.2
2.4
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVDET32(msec)
VCELLn=3.2V, SENS=VSS->0.7V, C2=3.3nF
n=1, 2, 3, 4, 5
R5432V404BA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-60 -40 -20 020 40 60 80 100
Ta (°C)
tshort(msec)
V
CELLn
=3.2V, SENS=VSS->1.5V
n=1, 2, 3, 4, 5
R5432V404BA
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVREL3(msec)
V
CELLn
=3.2V, VMP=0.4V->VSS
n=1, 2, 3, 4, 5
R5432V404BA
-0.23
-0.22
-0.21
-0.20
-0.19
-0.18
-0.17
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDET4(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
51
19) Excess Charge Current Output Delay Time 20) Excess Charge Current Delay Time of Released
21
) CTLC Pin "H" Input Voltage
22) CTLC Pin "H2"
Input Voltage
23) CTLD
Pin "H1" Input Voltage
24) CTLD
Pin "H2"
Input Voltage
R5432V404BA
0
2
4
6
8
10
12
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVDET4(msec)
V
CELLn
=3.2V, SENS=VSS->-0.4V
n=1, 2, 3, 4, 5
R5432V404BA
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-60 -40 -20 020 40 60 80 100
Ta (°C)
tVREL4(msec)
V
CELLn
=3.2V, VMP=-1.0V->1.0V
n=1, 2, 3, 4, 5
R5432V404BA
16.0
16.4
16.8
17.2
17.6
18.0
18.4
-60 -40 -20 020 40 60 80 100
Ta (°C)
CTLC1H(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
13.6
14.0
14.4
14.8
15.2
15.6
16.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
CTLC2H(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
16.0
16.4
16.8
17.2
17.6
18.0
18.4
-60 -40 -20 020 40 60 80 100
Ta (°C)
CTLD1H(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
13.6
14.0
14.4
14.8
15.2
15.6
16.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
CTLD2H(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
52
25) DOUT Nch ON Voltage 26) DRAIN Nch ON Voltage
27) CB1 Nch ON Voltage 28) CB2 Nch ON Voltage
29)
CB3 Nch ON Voltage
30) CB4 Nch ON
Voltage
R5432V404BA
0.00
0.02
0.04
0.06
0.08
0.10
0.12
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL2(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.02
0.04
0.06
0.08
0.10
0.12
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL3(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL4-VC2(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL5-VC3(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL6-VC4(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL7-VC5(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
53
31) CB5 Nch ON
Voltage
32) VR12V Output Voltage
33)
COUT
Pch ON Voltage
34)
DOUT Pch ON Voltage
35) DRAIN Pch ON Voltage 36) CB1 Pch ON Voltage
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOL8(V)
VCELLn=3.2V, I
OL
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
10.5
11.0
11.5
12.0
12.5
13.0
13.5
-60 -40 -20 020 40 60 80 100
Ta (°C)
VVR12(V)
VCELLn=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH1-VDD(V)
VCELLn=3.2V, I
OH
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH2-VVR12(V)
VCELLn=3.2V, I
OH
=-50uA
n=1, 2, 3, 4, 5
R5432V404BA
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH4-VC1(V)
VCELLn=3.2V、VCELL1=4.5V, I
OH
=-50uA
n=2, 3, 4, 5
R5432V404BA
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH3-VVR12(V)
VCELLn=3.2V, I
OH
=-50uA
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
54
37) CB2 Pch ON Voltage 38) CB3 Pch ON Voltage
39) CB4 Pch ON Voltage 40) CB4 Pch ON Voltage
41) CTLT Detector threshold 42) CTLT release Voltage
R5432V404BA
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH5-VC2(V)
VCELLn=3.2V, VCELL2=4.5V, I
OH
=-50uA
n=1, 3, 4, 5
R5432V404BA
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH6-VC3(V)
VCELLn=3.2V, VCELL3=4.5V, I
OH
=-50uA
n=1, 2, 4, 5
R5432V404BA
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH7-VC4(V)
VCELLn=3.2V, VCELL4=4.5V, I
OH
=-50uA
n=1, 2, 3, 5
R5432V404BA
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VOH8-VC5(V)
VCELLn=3.2V, VCELL5=4.5V, I
OH
=-50uA
n=1, 2, 3, 4
R5432V404BA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 020 40 60 80 100
Ta (°C)
VDTLT(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-60 -40 -20 020 40 60 80 100
Ta (°C)
VRTLT(V)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
55
43) CTLT Excess charge Curr ent 44) Open-wire test interval time
4
5) COUT Off leak current
46) Supply Current1
47) Supply Current2
R5432V404BA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-60 -40 -20 020 40 60 80 100
Ta (°C)
ICTLT(uA)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
24
26
28
30
32
34
36
-60 -40 -20 020 40 60 80 100
Ta (°C)
tLT(sec)
V
CELLn
=3.2V, C3=3.3uF
n=1, 2, 3, 4, 5
R5432V404BA
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-60 -40 -20 020 40 60 80 100
Ta (°C)
ILCOUT(uA)
V
CELLn
=3.2V、CTLC=VDD、COUT=-14V
n=1, 2, 3, 4, 5
R5432V404BA
0
4
8
12
16
20
24
-60 -40 -20 020 40 60 80 100
Ta (°C)
Iss1(uA)
V
CELLn
=3.2V
n=1, 2, 3, 4, 5
R5432V404BA
0
4
8
12
16
20
24
-60 -40 -20 020 40 60 80 100
Ta (°C)
Iss2(uA)
V
CELLn
=1.5V
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
56
Part2.Output Delay Time VDD dependence
1) Overcharge detector output Delay Time 2) Overcharge Released Delay Time
3) Overdischarge detect or output Delay Time 4) Overdischarge Released Delay Time
5) Excess discharge curr ent det ector Delay Time 1 6) Excess discharge curr ent det ector Delay Time 2
R5432V404BA
0.4
0.6
0.8
1
1.2
1.4
1.6
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVDET1 (sec)
V
CELL1
=3.2V, 3.6V, 4.0V->4.5V, SEL1=SEL2=VDD
n=2, 3, 4, 5
R5432V404BA
0
4
8
12
16
20
24
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVREL1 (msec)
V
CELL1
=4.5V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD
n=2, 3, 4, 5
R5432V404BA
60
80
100
120
140
160
180
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVDET2 (msec)
V
CELL1
=3.2V, 3.6V, 4.0V->2.0V, SEL1=SEL2=VDD
n=2, 3, 4, 5
R5432V404BA
0.6
0.8
1
1.2
1.4
1.6
1.8
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVREL2 (msec)
V
CELL1
=2.0V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD
n=2, 3, 4, 5
R5432V404BA
4
6
8
10
12
14
16
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVDET31 (msec)
SENS=Vss->Vss+0.4V, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V404BA
1.2
1.4
1.6
1.8
2
2.2
2.4
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVDET32 (msec)
SENS=Vss->Vss+0.7V, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
57
7) Short detector output delay time1 8) Excess discharge current released delay time2
9) Excess char ge cur rent detector output Delay Time 10) Excess charge current
released delay time
R5432V404BA
0
0.1
0.2
0.3
0.4
0.5
0.6
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tshort (msec)
SENS=Vss->Vss+1.5V, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V404BA
0.6
0.8
1
1.2
1.4
1.6
1.8
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVREL3 (msec)
V-=Vss+0.4V->Vss, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V404BA
0
2
4
6
8
10
12
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVDET4 (msec)
V-=Vss->Vss-0.4V, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V404BA
0.6
0.8
1
1.2
1.4
1.6
1.8
3.0 3.2 3.4 3.6 3.8 4.0 4.2
V
CELL
n (V)
tVREL4 (msec)
V-=Vss-0.4V->Vss+0.4V, SEL1=SEL2=VDD
n=1, 2, 3, 4, 5
R5432V
NO.EA-263-160711
58
Part3. Supply Current VDD dependence (R5432V404BA)
Supply Current for 5-cell protection
0.1uF
330
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
10M
DRAIN
2M
SEL1
SEL2
CTLD
10k
VSS
VSS
CT1
CT2
10k
1M
0.1uF
0.1uF
0.1uF
0.1uF
1uF
0.47uF
3.3nF
CTLT
A
330
330
330
330
330
100m
0
2
4
6
8
10
12
14
0 5 10 15 20 25
VDD(V)
Supply Current
Iss(μA)
R5432V
NO.EA-263-160711
59
Part4. External resistance dependence (R5432V404BA)
Overcharge Detector/Released Voltage from Overcharge
Overdi scharge De tect or/Released Voltage from Overdischarge
vs. R1 (CELL1) vs. R1 (CELL1)
0.1uF
VC1
VC2
VDD
Cell1
CB1
Cell2
Cell3
Cell4
Cell5
VC3
VC4
VC5
VSS
CB2
CB3
CB4
CB5
SENS
VMP
Cout
Dout
CTLC
10M
DRAIN
2M
SEL1
SEL2
CTLD
100m
10k
VSS
VSS
CT1
CT2
10k
1M
0.1uF
0.1uF
0.1uF
0.1uF
1uF
0.47uF
3.3nF
CTLT
R1
330
330
330
330
330
2.485
2.490
2.495
2.500
2.505
2.510
2.515
0 500 1000 1500 2000
R1()
VDET21(V)
2.980
2.985
2.990
2.995
3.000
3.005
3.010
VREL21(V)
VDET21 VREL21
4.235
4.240
4.245
4.250
4.255
4.260
4.265
0 500 1000 1500 2000
R1()
VDET11(V)
4.090
4.095
4.100
4.105
4.110
4.115
4.120
VREL11(V)
VDET11 VREL11
R5432V
NO.EA-263-160711
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CELL balance detector / Released Voltage from CELL balance vs. R1 (CELL1)
4.185
4.190
4.195
4.200
4.205
4.210
4.215
0 500 1000 1500 2000
R1()
CBDET1(V)
4.185
4.190
4.195
4.200
4.205
4.210
4.215
CBREL1(V)
CBDET1 CBREL1
POWER DISSIPATION SSOP-24
Ver. A
i
The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following conditions are used in this measurement.
Measurement Conditions
Standard Test Land Pattern
Environment Mounting on Board (Wind Velocity = 0 m/s)
Board Material Glass Cloth Epoxy Plastic (Double-Sided Board)
Board Dimensions 40 mm × 40 mm × 1.6 mm
Copper Ratio Top Side: Approx. 50%
Bottom Side: Approx. 50%
Through-holes φ 0.5 mm × 44 pcs
Measurement Result (Ta = 25°C, Tjmax = 125°C)
Standard Test Land Pattern
Power Dissipation 770 mW
Thermal Resistance
θja = (125 25°C) / 0.770 W = 130°C/W
IC Mount Area (mm)
Power Dissipation vs. Ambient Temperature
Measurement Board Pattern
40
40
0
25
50
75 100 125
150
Ambient Temperature (°C)
Power Dissip ati on (mW)
1000
800
600
400
200
0
85
770
Standard Test Land Pattern
PACKAGE DIMENSIONS SSOP-24
Ver. A
i
0.375 TYP.
0.220.05
1.15±0.1
0.65
0.10
+0.1
0.15
M
0.1±0.05
1.4Max.
7.9±0.2
7.6±0.2
5.6±0.2
0.150.05
+0.1
0.5±0.2
0 to 10°
SSOP-24 Package Dimensions (Unit: mm)
Ricoh is committed to reducing the environmental loading materials in electrical devices
with a view to contributing to the protection of human health and the environment.
Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
April 1, 2012.
Halogen Free
https://www.e-devices.ricoh.co.jp/en/
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1.Theproductsand the productspecificationsdescribed inthisdocument are subjectto change ordiscontinuationof
productionwithoutnotice for reasons
suchasimprovement. Therefore, before deciding tousethe products, please
refertoRicohsalesrepresentativesforthelatestinformationthereon.
2.Thematerialsin this document maynotbe copied orotherwisereproducedin whole orinpart without prior written
consentofRicoh.
3.Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise
takingoutofyourcountrytheproductsorthetechnicalinformationdescribedherein.
4.Thetechnicalinformationdescribedinthisdocumentshowstypicalcharacteristicsofandexampleapplicationcircuits
fortheproducts.Thereleaseofsuchinformationisnottobeconstruedasawarrantyoforagrantoflicenseunder
Ricoh'soranythirdparty'sintellectualpropertyrightsoranyotherrights.
5.Theproductslistedinthisdocumentareintendedanddesignedforuseasgeneralelectroniccomponentsinstandard
applications (office equipment, telecommunication equipment, measuring instruments, consumer electronic products,
amusementequipment etc.). Thosecustomersintending tousea product inanapplication requiringextremequality
andreliability,forexample,inahighlyspecificapplicationwherethefailureormisoperationoftheproductcouldresult
inhumaninjuryordeath(aircraft,spacevehicle,nuclearreactorcontrolsystem,trafficcontrolsystem,automotiveand
transportationequipment,combustionequipment,safetydevices,lifesupportsystemetc.)shouldfirstcontactus.
6.Wearemakingourcontinuousefforttoimprovethequalityandreliabilityofourproducts,butsemiconductorproducts
arelikelytofailwithcertainprobability.Inordertopreventanyinjurytopersonsordamagestopropertyresultingfrom
suchfailure,customersshouldbecarefulenoughtoincorporatesafetymeasuresintheirdesign,suchasredundancy
feature,firecontainmentfeatureandfail-safefeature.Wedonotassumeanyliability
orresponsibilityforanylossor
damagearisingfrommisuseorinappropriateuseoftheproducts.
7.Anti-radiationdesignisnotimplementedintheproductsdescribedinthisdocument.
8.The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and
characteristicsintheevaluationstage.
9.WLCSP products should be used in light shielded environments. The light exposure can influence functions and
characteristicsoftheproductsunderoperationorstorage.
10.There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the
caseofrecognizingthemarkingcharacteristicwithAOI,pleasecontactRicohsalesorourdistributorbeforeattempting
touseAOI.
11.
PleasecontactRicohsalesrepresentativesshouldyouhaveanyquestionsorcommentsconcerningtheproductsor
thetechnicalinformation.