R5432V SERIES
3 to 5 Cells Li-ion Batt ery Protector IC
NO.EA-263-1600711
1
OUTLINE
The R5432V is a h igh vo ltage CMOS-based prot ection IC for overcharge /dis charge of r ech argeable three-cell / four-cell / five-
cell Lithium-ion / Lit hium- polymer battery, further inc lude a short circuit a nd the pr otectio n circuit s again st the ex cess dis charge
current and ex cess charge current.
Each of these ICs is composed of eighteen voltage detectors (fourteen for 3cell protection type, sixteen for 4cell protection
type), a reference circuit, a delay circuit, a short detector circuit, an oscillator, a counter and a logic circuit.
The output of COUT is P-channel open-drain type, and DOUT is CMOS type.
If the overcharge voltage or overcharge current is detected by the R5432V, after the preset output delay time, the output of
COUT becomes Hi-Z.
While the overdischarge voltage or current is detected, after the preset output delay time, the output of DOUT becomes ”L”.
After det ectin g overc harge v oltage, when the cell vol tage retur ns low er than the overcharge relea sed v oltage, t hen overcharge
is released and the output of COUT becomes “H”. After detecting overcharge current, by disconnecting a charger and
connecting a load, then overcharge current is released and the output of COUT becomes “H”.
After detecting overdischarge voltage, when the cell voltage becomes the released voltage from overdischarge or more,
then overdischarge is released and the output of DOUT bec omes “H”. After detecting overdischarge current and short circuit,
by disconnecting the load, the function of the output of DRAIN pin, the external NMOSFET turns on, and VMP pin voltage is
pulled dow n by the resistance connected to GND and released overdischarge current or short and the o utput of DOUT becomes
“H”.
By forcing a certain voltage to SEL1 and SEL2 pins, the testing time of protection circuits can be short. Specifically,
overcharge, discharge, over current delay time can be shortening into approximately 1/80.
The R5432V can prote ct 6-cell or more by connecting 2 pieces of the R5432V in cascade. H igh side IC’s COUT and
DOUT must connect to CTLC and CTLD respectively of the low side IC. As a result, the signal of the high side of COUT and
DOUT is transmit to the lower side IC, and control FETs for charge and discharge.
The R5432V has cell-balance function to solve the unbalance condition of serially connected cells. If ce ll volt age is
beyond the cell balance detector threshold, by the output of the cell balance control pin, the external NMOSFET turns on, and
a current path is made, and during charge, charge current is bypassed, otherwise, cell is discharged until the cell voltage
becomes the released voltage from cell-balance operation.
If the connection between a cell and a protection board is broken, the open-wire condition is detected by the R5432V, and t he
output of COUT bec omes Hi-Z. After detecting the open-wire, when the cell and the protection board is connected again, the
open-wire detector is released and the output of COUT becomes “H”.
FEATURES
• Absolute Maximum Rating ............................................... 30V
• Supply Current ................................................................. Typ. 12.0µA
Detector thresholds range and accuracy
• Overcharge detector threshold ......................................... 3.6V to 4.5V (5mV step) (n=1, 2, 3, 4, 5) (±25mV)
• Overdischarge detector threshold .................................... 2.0V to 3.0V (5mVstep) (n=1, 2, 3, 4, 5) (±2.5%)
• Excess disch arge current threshold 1 .............................. 0.1V to 0.3V (10mVstep) (±20mV) for BA/BB/BC ver.
0.1V to 0.2V (10mV step) (±20mV) for AD/BD ver .
• Excess discharge current threshold 2 .............................. 0.45V/0.60V for BA ver.
0.25V to 0.40V for BB/BC ver.
0.25V/0.3V(Vdet3-1+ 0.1V or more) for AD/BD ver.
R5432V
NO.EA-263-160711
2
• Short detector threshold ..................................................... 1.00V for BA ver.
0.75V for BB/BC ver.
Vdet3-2 x 1.67 for AD/BD ver.
•
Excess charge current threshold ........................................
-0. 05V (
±
30mV), -0.1V (
±
30mV), -0.2V (
±
30mV), -0.4V (
±
40mV)
• Overcharge released voltage.............................................. VDET1n-0.1V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5)
• Overdischarge released voltage ......................................... VDET2n+0.2V to 0.7V (100mV steps) (n=1, 2, 3, 4, 5)
up to 3.4V
• Cell-balance detector thre sho l d .......................................... 3.45V to 4.45V (5mV steps) (n=1, 2, 3, 4, 5)
• Cell-balance released voltage ............................................ CBDETn-0.0V to 0.4V (50mV steps) (n=1, 2, 3, 4, 5)
Output delay time
• Overcharge detector Output Delay ..................................... 1.0s
• Overdischarge detector Output Delay ................................ Settable by Ext.Capacitance1
• Excess disch arge current detector Output Delay 1/2 .......... Settable by Ext.Capacitance2
• Excess charge curr e nt detector Output Delay .................... 8ms
• Short detector Output Delay ............................................... 300µs
Functions
• 0V-battery charger ........................................... .................. accepta ble/ una cce pta ble options
• Cascade connection ........................................ .................. Available. Refer to the typical application.
• 3/4/5 cell protec tio n ........................................ .................. Selectable
• Output Delay Time Shortening Function ............................. By forcing a certain voltage to SEL pin, overcharge,
discharge v ol tage and curr ent is re duc ed approx imately 1/80.
Overcharge delay time can be shorten into around 4ms for
testing.
• Cell-balance function .......................................................... Available
• Cell-unbalance condition .................................................... If e ither of c ell s dete ct s overchar ge and ei ther of cells dete cts
overdischarge, the output of COUT becomes “Hi-Z”, the output of DOUT becomes “L”.
• Overcharge/Overdischarge released condition................... By voltage condition.
• Output of COUT/DOUT ...................................................... COUT: VDD source P-channel open drain output. Normal
state “H”(VDD) , Detected state “Hi-Z”.
DOUT: 12V regulator source CMOS output. Normal state
“H”(12V), Detected state “L”.
• Open-wire detection ........................................................... Open-wire between VDD, VSS, VCx pin and the pack is
supervised.
• Small Package .................................................................... SSOP-24
R5432V
NO.EA-263-160711
3
BLOCK DIAGR AMS
R5432VxxxBA
V
C2
V
C1
VD2-1
VD1-1
VD2-2
VD1-2
VD2-3
VD1-3
VD2-4
VD1-4
V
C3
V
C4
V
C5
SEL1
V
DD
VD2-5
VD1-5
V
SS
Logic
Circuit
SEL2
Logic
Circuit
CB
2
CB
1
CB
3
CB
4
CTLT
CB
5
CB
Circuit-1
CB
Circuit-2
CB
Circuit-3
CB
Circuit-4
CB
Circuit-5
Delay
Short
Circuit
SENS
Ds
Circuit
Logic
Circuit
Logic
Circuit
Regulator
Regulator
CT1
CT2
DRAIN
VMP
CTLD
CTLC
Logic
Circuit
D
OUT
C
OUT
tV
DET2
VD3-2
VD3-1
VD4
T Stop
T Start
odd sw
even sw
tV
DET3
Counter
Oscillatpr
R5432V
NO.EA-263-160711
4
SELECTION GUIDE
Product Name
Package
Quantity per Reel
Pb Free
Halogen Free
R5432Vxxx$
∗
SSOP-24 3000 Yes Yes
xxx :Serial Number for the R5432V designating voltages such as overcharge threshold, overcharge
released vol tag e, Cell-balance threshold, Cell-balance released voltage, overdischarge threshold,
overd isc harge rel eased vo lt age, ov er discharge current1/2, overcharge current, short voltage.
$ : Designation of Output delay option.
Overcharge
Delay time
(s)
Overdischarge
Delay time
(ms)
Overdischarge
Current Delay time1
(ms)
Overdischarge
Current Delay time2
(ms)
Overcharge
Current Delay time
(ms)
Short
Delay time
(µs)
A
1.0
3.64×C
CT1
(nF)
3.05×C
CT2
(nF)
tV
DET
31/ 100
8
300
B
1.0
3.88×CCT1 (nF)
3.26×CCT2 (nF)
tVDET31/ 6
8
300
*capacitor for CT1: CCT1, capacitor for CT2:CCT2.
∗ : Designation of Output delay option.
Overcharge
Released condition
Overdischarge
Released condition
0V battery
Charge
Short detect or
Threshold
Open-wire
detection
Cascade
connection
A
Auto Release
Auto Release
Acceptable
1.0V
Available
Available
B
Auto Release
Auto Release
Unacceptable
0.75V
Available
Available
C
Auto Release
Auto Release
Acceptable
0.75V
Available
Available
D
Auto Release
with hysteres is
cancellation
Auto Release Acceptable VDET32 x 1.67
Available Available
R5432V
NO.EA-263-160711
5
1) Product Code List
Code
VDET1n
(V) *1
VREL1n
(V) *1
VCBDn
(V) *1
VCBRn
(V) *1
VDET2n
(V) *1
VREL2n
(V) *1
VDET31
(V)
VDET32
(V)
VSHORT
(V)
VDET4
(V)
R5432V402BA
4.350
4.050
4.200
4.200
2.400
2.700
0.200
0.600
1.000
-0.100
R5432V403BA
3.900 3.800 3.500 3.500 2.500 3.000 0.100 0.600 1.000 -0.100
R5432V404BA
4.250
4.100
4.200
4.200
2.500
3.000
0.200
0.600
1.000
-0.200
R5432V405BA
3.900 3.800 3.650 3.650 2.000 2.300 0.100 0.600 1.000 -0.200
R5432V406BA
3.650
3.550
3.500
3.500
2.500
3.000
0.300
0.600
1.000
-0.200
R5432V407BA
4.200 4.000 3.900 3.900 2.700 2.850 0.200 0.450 1.000 -0.200
R5432V408BA
3.800
3.600
3.450
3.450
2.000
2.300
0.200
0.450
1.000
-0.100
R5432V409BA
4.100 4.000 3.900 3.900 3.000 3.100 0.200 0.600 1.000 -0.200
R5432V410BC
4.200
4.000
4.150
4.150
2.750
2.950
0.100
0.250
0.750
-0.050
R5432V412BA
4.300 4.050 4.200 4.200 2.700 3.000 0.200 0.600 1.000 -0.100
R5432V413BA
4.250
4.100
4.200
4.200
2.500
3.000
0.100
0.600
1.000
-0.100
R5432V416BA
4.200 4.100 4.170 4.170 2.500 3.000 0.200 0.450 1.000 -0.100
R5432V417BC
4.200
4.100
4.180
4.180
2.500
3.000
0.100
0.400
0.750
-0.050
R5432V418BC
4.180 4.080 4.180 4.180 2.500 3.000 0.100 0.400 0.750 -0.050
R5432V419BD
3.900
3.800
3.500
3.500
2.500
3.000
0.100
0.300
0.500
-0.100
R5432V420BD
4.350 4.050 4.200 4.200 2.400 2.700 0.100 0.250 0.418 -0.100
R5432V501BA
3.900
3.700
3.800
3.600
2.000
2.300
0.200
0.600
1.000
-0.200
R5432V502BA
4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.450 1.000 -0.050
R5432V503BB
4.250
4.150
4.150
4.140
2.700
3.000
0.150
0.300
0.750
-0.050
R5432V504BD
4.250 4.100 4.200 4.190 2.800 3.000 0.100 0.250 0.418 -0.050
R5432V505BD
4.250
4.100
4.200
4.190
2.500
3.000
0.100
0.250
0.418
-0.050
R5432V506BD
3.900 3.800 3.650 3.640 2.000 2.300 0.100 0.250 0.418 -0.050
R5432V507BD
4.215
4.100
4.200
4.180
2.800
3.000
0.100
0.250
0.418
-0.100
R5432V508BA
3.800 3.700 3.600 3.580 2.800 2.900 0.200 0.600 1.000 -0.100
R5432V509BD
3.900
3.800
3.650
3.640
2.000
2.300
0.100
0.250
0.418
-0.100
R5432V510BD
3.900 3.800 3.475 3.465 2.000 2.300 0.100 0.250 0.418 -0.100
*1：n＝1,2,3,4,5
R5432V
NO.EA-263-160711
6
PIN DESCR IPTIO NS
SSOP-24
1
5
2
3
4
6
7
8
16
15
14
13
9
10
11
12
17
18
19
20
21
22
23
24
Pin No Symbol Pin Description
1
CTLC
C
OUT
control pin
2 CTLD DOUT control pin
3
C
OUT
Output pin of overcharge d et ecti on, Pch OPEN DRAIN output
4 VMP Pin for charger negative input
5
DRAIN
Release from Excess discharge-current threshold Pin
6
D
OUT
Output pin of overdischarge detection,CMOS output
7
SENS
Current sense pin
8
CTLT
Disconnection detection movement interval setting capacitance pin
9
V
SS
V
SS
pin. Ground pin for the IC
10
CT1
tV
DET2
setting capacitance connection pin
11
CT2
tV
DET3
setting capacitance connection pin
12
SEL1
3cell/4cell/5cell alternative pin1
13 SEL2 3cell/4cell/5cell alternative pin2
14
CB5
CELL5 Cell balance Control pin
15 VC5 Positive terminal pin for Cell5
16
CB4
CELL4 Cell balance Control pin
17
V
C4
Positive terminal pin for Cell4
18
CB3
CELL3 Cell balance Control pin
19
V
C3
Positive terminal pin for Cell3
20
CB2
CELL2 Cell balance Control pin
21
V
C2
Positive terminal pin for Cell2
22 CB1 CELL1 Cell balance Control pin
23
V
C1
Positive terminal pin for Cell1
24 VDD VDD
pin
R5432V
NO.EA-263-160711
7
ABSOLUTE MAXIMUM R ATINGS
Symbol
Item
Rating
Unit
VDD
Supply voltage
-0.3 to 30
V
Input voltage
VC1
Positive input pin for Cell1
VC2-0.3 to VC2+6.5
V
V
C2
Positive input pin for Cell2
VC3-0.3 to VC3+6.5
V
V
C3
Positive input pin for Cell3
V
C4
-0.3 to V
C4
+6.5
V
VC4 Positive input pin for Cell4 VC5-0.3 to VC5+6.5 V
VC5
Positive input pin for Cell5
-0.3 to 6.5
V
VMP
Charger negative terminal input pin
-0.3 to 30.0
V
VSEL1 3Cell/4Cell/5Cell alternative pin1 -0.3 to VDD+0.3 V
V
SEL2
3Cell/4Cell/5Cell alternative pin2
-0.3 to VDD+0.3
V
VCTLC COUT c ontrol pin
-0.3 to VDD+25
V
-0.3 to 48
VCTLD DOUT c ontrol pin
-0.3 to VDD+25
V
-0.3 to 48
V
SENSE
Current sense pin
-0.3 to VDD+0.3
V
V
CT1
Delay time setting pin1
-0.3 to 3.5
V
VCT2
Delay time setting pin2
-0.3 to 3.5
V
VCTLT
Disconnection detection movement interval setting
capacitance pin
-0.3 to 3.5 V
Output voltage
VCOUT
Output pin of overcharge d et ecti on,CMOS outp ut
VDD-30 to VDD+0.3 V
V
DOUT
Output pin of overdischarge detection,CMOS output
-0.3 to VOH2+0.3
V
VDRAIN Release from Excess discharge-current threshold Pin -0.3 to VOH3+0.3 V
VCB1
Cell balance Control pin for Cell1
V
C2
-0.3 to V
C2+
6.5
V
VCB2
Cell balance Control pin for Cell2
VC3-0.3 to VC3+6.5 V
V
CB3
Cell balance Control pin for Cell3
VC4-0.3 to VC4+6.5
V
VCB4
Cell balance Control pin for Cell4
VC5-0.3 to VC5+6.5
V
V
CB5
Cell balance Control pin for Cell5
-0.3 to 6.5
V
PD
Power dissipation(1)
770
mW
Ta
Operating temperature range
-40 to 85
°C
Tstg
Storage temperature range
-55 to 125
°
C
ABSOLUTE MAXIMUM RATINGS
Electroni c and mechani cal stre ss momentarily exceeded ab solute maximu m ratings may cause the permanent da mages
and may degrade the life ti me and safety f or both devi ce and system using the de v ice in the field.
The functional operations at or over these absolute maximum ratings are not assured.
(1) Refer to POWER DISSIPATION for detailed information.
R5432V
NO.EA-263-160711
8
ELEC TRICAL CHAR ACTERIS TICS
• R5432VxxxBA Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1 Operating input voltage VDD-VSS 2 25 V -
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect fa l l i ng edge of supply voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V (n=2,3,4,5),
VCELL1=3.5V→4.5V
0.7 1.0 1.3 s B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Detect rising edge of supply voltage
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VCBRn
-0.050 VCBRn
Lower of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Detect rising ed ge of supply voltage
VREL2n
×0.975 VREL2n
VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
→
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n
=
2, 3, 4, 5), V
CELL1=
1.5V
1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=33nF
89 128 167 ms -
tVREL2 Output delay of
release from overdischarge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising edge of supply voltage
0.500 0.600 0.700 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Detect falling edge of supply voltage
VDET31
×0.50 VDET31
×0.75 VDET31
×１.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENSE=VSS→0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V
(n=1,2,3,4,5) SENSE
=
V
SS→
0.7V
2.0 3.0 4.0 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V (n=2,3,4,5)
SENSE=0.4V, VMP=4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=3.3nF
7.3 10.8 14.7 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=3.3nF
1.25 1.8 2.4 ms -
tVREL3
Output delay of release from
Excess
discharge-current
Threshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
9
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply voltage
0.7 1.0 1.7 V K
tshort
Output Delay of Sh o rt pr otection
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5) SENS=0.0V→2.0V,
VMP=4.0V
180 300 550 µs K
VDET4 Excess char ge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld
V
DD
=V
C1,
V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→-1.0V
5 8 11 ms L
tVrel4
Output delay
of release from
Excess
charge-current threshold
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3 V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) 4.0 VDD/2
-0.5V V M
VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
VSS
-0.3
VSS
+1.0
V M
VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5) VDD
-0.3 VDD
+0.3 V N
VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
4.0 VDD/2
-0.5V
V N
VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+0.3 V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
, C
TLD
=V
DD
VCELLn =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age IOL=50μA, VDD=VC1,
VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50
μ
A, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
R5432V
NO.EA-263-160711
10
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
C
TLC
=V
SS
VDD
-0.5 VDD
-0.1 V T
VVR12 VR 12V output voltage (*1)
I
OH
=-5µA, V
DD
=V
C1
, C
TLD
=V
SS
,
VCELL=3.2V (n=1, 2, 3, 4, 5)
Measured to draw the current
through DOUT
10 12 14 V U
VOH2 DOUT Pch ON voltage (*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLD= VSS
VVR12
-0.5V VVR12
-0.1V V U
VOH3 DRAIN Pch ON volta ge (*1)
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
SENS =VMP =4.0V
VVR12
-0.5V VVR12
-0.1V V V
VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
VCELLn=3.2V (n =2, 3, 4, 5)
VC1
-0.5 VC1
-0.3 V W
VOH5 CB2 Pch ON voltage
I
OH
=-50µA, V
DD
=V
C1
, V
C1
=4.5V,
V
CELL
n
=
3.2V (n
=
1, 3, 4, 5)
V
C2
-0.5
V
C2
-0.3
V W
VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V,
V
CELL
n
=
3.2V (n
=
1, 2, 4, 5)
VC3
-0.5 VC3
-0.3 V W
VOH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 5)
VC4
-0.5 VC4
-0.3 V W
VOH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1,
VC1=4.5V, VCELLn=3.2V
(n=1, 2, 3, 4)
VC5
-0.5 VC5
-0.3 V W
ILCOUT COUT pin off leak current
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
CTLC=VDD, COUT=-14V
-0.1 µA X
ICTLT CTLT Charge Current VDD=VC1, VCELLn=3.2V
(n
=
1, 2, 3, 4, 5)
145 205 264 nA Y
VDTLT CTLT detector threshold
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 4, 5)
VC3=VD1+0.2V
1.58 2.00 2.42 V Z
VRTLT CTLT released voltage
V
DD
=V
C1
, V
CELL
n=3.2V
(n=1, 2, 3, 4, 5)
0.07 0.13 0.19 V Z
tLT Disconnection detec tion
Test Interval
CCTLT×(VDTLT-VRTLT)/ICTLT
CCTLT =3.3µF 21 30 39 s -
ISS1 Supply Currnt1
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=VDET1n-0.4V
(n=1, 2, 3, 4, 5)
12 30 µA a
ISS2 Supply Currnt2
V
DD
=V
C1
,C
OUT
=OPEN
VCELLn=1.5V
(n=1, 2, 3, 4, 5)
10 25 µA a
∗ VCELLn=CELLn voltage n=1, 2, 3, 4, 5
(*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.
RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS)
All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. The
semiconductor devices may receive serious damage when they continue to operate over the recommended operating
conditions.
R5432V
NO.EA-263-160711
11
• R5432VxxxBB/BC Unless otherwise specified, Ta=25°C
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
VDD1
Operating input voltage
VDD-VSS
2
25
V
-
VDET1n
CELLn Overcharge threshold
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
V
DET1
n
-0.025
VDET1n
V
DET1
n
+0.025
V A
VREL1n
CELLn Overcharge released
Voltage (n=1,2,3,4,5)
Detect falling edge of supply
voltage
V
REL1
n
-0.050
VREL1n
V
REL1
n
+0.050
V A
tVDET1 Output delay of overcharge
V
DD
=V
C1
,V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=3.5V→4.5V
0.7 1.0 1.3 s B
tVREL1
Output delay of
release from overcharge
V
DD
=V
C1
, V
CELL
n=3.5V
(n=2,3,4,5), VCELL1=4.5V→3.5V
11 16 21 ms B
VCBDn
CELLn balance threshold
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
V
CBD
n
-0.025
VCBDn
V
CBD
n
+0.025
V C
VCBRn CELLn balance
released
threshold
(n=1,2,3,4,5)
Detect falling edge of supply
voltage
VCBRn
-0.050 VCBRn
Lower
of
VCBRn
+0.050
or
VCBDn
+0.025
V C
VDET2n
CELLn Overdischarge
threshold
(n=1,2,3,4,5)
Detect falling edge of supply
voltage
VDET2n
×0.975 VDET2n VDET2n
×1.025 V D
VREL2n
CELLn Overdischarge released Voltage
(n=1,2,3,4,5)
Det ect ri sing e dge of s upp ly volt age
VREL2n
×0.975 VREL2n VREL2n
×1.025 V D
ICT1
CT1 charge Current
V
DD
=V
C1
, V
CELL
n=3.5V
(n
=
2, 3, 4, 5), V
CELL1
=
3.5V
→
1.5V
350 500 650 nA E
VDCT1
CT1 d etector voltag e
VDD=VC1, VCELLn=3.5V
(n=2, 3, 4, 5), VCELL1=1.5V 1.48 1.85 2.22 V F
tVDET2
Output delay of overdischarge
tV
DET2
=C
CT1
×V
DCT1
/I
CT1
CCT1=33nF
89 128 167 ms -
tVREL2 Output delay of
release from overdischarge
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5), VMP=4.0V
V
CELL1
=1.5V→3.5V
0.7 1.2 1.7 ms G
VDET31 Excess dischar ge -current
threshold1
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Det ect ri sing e dge of s upp ly volt age
VDET31
-0.020 VDET31 VDET31
+0.020 V H
VDET32 Excess dischar ge -current
Threshold2
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Det ect ri sing e dge of s upp ly volt age
VDET32
-0.070 VDET32 VDET32
+0.070 V I
VREL3
Output delay of
release from Excess
discharge-current threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), SENSE=0V
Det ect f alli ng edge of su pply volt age
VDET31
×0.50 VDET31
×0.75 VDET31
×１.00 V H
ICT231 CT2 Charge Current1
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS→0.4V
350 500 650 nA I
ICT232 CT2 Charge Current2
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENSE=VSS→0.7V
2.0 3.0 4.0 µA I
VDCT2 CT2 Charge voltage
V
DD
=V
C1
, V
CELL
n =3.5V
(n=2,3,4,5)
SENSE=0.4V, VMP=4.0V
1.23 1.55 1.87 V J
tVDET31
Output delay of Exces s
discharge-current thr es hold1
t
VDET31
=C
CT2
×V
DCT2
/I
CT231
CCT2=3.3nF
7.3 10.8 14.7 ms -
tVDET32
Output delay of Exces s
discharge-cur rent T hreshold2
t
VDET32
=C
CT2
×V
DCT2
/I
CT232
CCT2=3.3nF
1.25 1.80 2.40 ms -
tVREL3
Output delay of release from
Excess
discharge-cur rent T hreshold
VDD=VC1, VCELLn=3.5V
(n=1,2,3,4,5)
SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H
R5432V
NO.EA-263-160711
12
Symbol
Items
Conditions
Min.
Typ.
Max.
Unit
Circuit
Vshort Short protection voltage
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=4.0V
Detect rising of supply vol t age
0.7 1.0 1.7 V K
tshort
Output Delay of Sh o rt pr otection
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→2.0V,VMP=4.0V
180 300 550 μs K
VDET4 Excess charge-current
threshold
V
DD
=V
C1
, V
CELL
n=3.5V
(n=1,2,3,4,5), VMP=-1.0V
Detect falling edge of supply voltage
VDET4
-0.030 VDET4 VDET4
+0.030 V L
tVDET4
Output delay
of Excess
charge-cur rent thr e sho ld
V
DD
=V
C1,
V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=0.0V→-1.0V
5 8 11 ms L
tVrel4
Output delay
of release from
Excess charge-current
threshold
V
DD
=V
C1
, V
CELL
n =3.5V
(n=1,2,3,4,5)
SENS=VSS,VMP=-1.0V→1.0V
0.7 1.2 1.7 ms L
VIH1 SEL1 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V M
VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V
(n=1,2,3,4,5)
4.0 VDD/2
-0.5V
V M
VIL1 SEL1 pin “L” input voltage
V
DD
=V
C1,
V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+1.0
V M
VIH2 SEL2 pin “H” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V N
VIM2 SEL2 pin “M” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
4.0
V
DD
/2
-0.5V
V N
VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V
(n=1,2,3,4,5) VSS
-0.3 VSS
+0.3 V N
CTLC1H CTLC pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V O
CTLC2H CTLC pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V O
CTLC1L CTLC pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V O
CTLD1H CTLD pin “H1” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
+2.0
V P
CTLD2H CTLD pin “H2” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
DD
-0.3
V
DD
+0.3
V P
CTLD1L CTLD pin “L” input voltage
V
DD
=V
C1
, V
CELL
n =3.2V
(n=1,2,3,4,5)
V
SS
-0.3
V
SS
+0.3
V P
VOL2 DOUT Nch ON voltage
I
OL
=50μA, V
DD
=V
C1
, C
TLD
=V
DD
V
CELL
n =3.2V (n=1,2,3,4,5)
0.1 0.5 V Q
VOL3 DRAIN Nch ON volt age IOL=50μA, VDD=VC1,
VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R
VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC2
+0.2
VC2
+0.5
V S
VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC3
+0.2
VC3
+0.5
V S
VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC4
+0.2
VC4
+0.5
V S
VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1,
VCELLn=3.2V (n=1,2,3,4,5) VC5
+0.2
VC5
+0.5
V S
VOL8 CB5 Nch ON voltage
I
OL
=50μA, V
DD
=V
C1
,
VCELLn=3.2V (n=1,2,3,4,5)
0.2 0.5 V S
VOH1 COUT Pch ON voltage
I
OH
=-50
μ
A, V
DD
=V
C1
,
VCELLn =3.2V (n=1,2,3,4,5)
CTLC=VSS
VDD-0.5 VDD-0.1 V T