Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6 1Publication Order Number:
SN74LS259/D
SN74LS259
8-Bit Addressable Latch
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed
for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in eight
addressable latches, and also a 1-of-8 decoder and demultiplexer with
active HIGH outputs. The device also incorporates an active LOW
common Clear for resetting all latches, as well as, an active LOW
Enable.
•Serial-to-Parallel Conversion
•Eight Bits of Storage With Output of Each Bit Available
•Random (Addressable) Data Entry
•Active High Demultiplexing or Decoding Capability
•Easily Expandable
•Common Clear
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V
TAOperating Ambient
Temperature Range 0 25 70 °C
IOH Output Current – High –0.4 mA
IOL Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS259N 16 Pin DIP 2000 Units/Box
SN74LS259D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS259
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Address Inputs
Data Input
Enable (Active LOW) Input
Clear (Active LOW) Input
Parallel Latch Outputs
A0, A1, A2
D
E
C
Q0 – Q7
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
14 13 12 11 10 9
1234567
16 15
8
VCC
Ao
C E DQ
7Q5
Q6Q4
A1A2Q0Q1Q2Q3GND
EC MODE
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
QN–1 = Previous Output State
SN74LS259
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3
LOGIC DIAGRAM
EDA
0A1A2C
Q0Q1Q2Q3Q4Q5Q6Q7
14 12
67
3
4 5 9 11 1210
13 15 VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A0A1A2Q0Q1Q2Q3Q4Q5Q6Q7MODE
L H X X X X L L L L L L L L Clear
LLL L L L L L L L L L L L Demultiplex
LLH L L L H LLLLLLL
LLL H L L L LLLLLLL
LLH H L L L HLLLLLL
••• • •
••• • •
••• • •
••• • •
••• • •
LLH H H H L LLLLLLH
H H X X X X QN–1 Memory
H I I L L L L QN–1 QN–1 QN–1 Addressable
HLH L L L H QN–1 QN–1 Latch
HLL H L L Q
N–1 LQ
N–1
HLH H L L Q
N–1 HQ
N–1
••• • •
••• • •
••• • •
••• • •
••• • •
HLL H H H Q
N–1 QN–1 L
H L H H H H QN–1 QN–1 H
SN74LS259
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4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage 0.8 VGuaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.7 3.5 VVCC = MIN, IOH = MAX, VIN = VIH
or VIL per T ruth Table
VO
Out
p
ut LOW Voltage
0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
tp
u
t
LOW
Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL
or
V
IH
per T ruth Table
I
In
p
ut HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
I
IH
Inp
u
t
HIGH
C
u
rrent
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 36 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL T urn-Off Delay, Enable to Output
T urn-On Delay, Enable to Output 22
15 35
24 ns
ns
tPLH
tPHL T urn-Off Delay, Data to Output
T urn-On Delay, Data to Output 20
13 32
21 ns
ns CL = 15 pF
tPLH
tPHL T urn-Off Delay, Address to Output
T urn-On Delay, Address to Output 24
18 38
29 ns
ns
L
tPHL T urn-On Delay, Clear to Output 17 27 ns
AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol Parameter Min Typ Max Unit
tsInput Setup T ime 20 ns
tWPulse Width, Clear or Enable 15 ns
thHold T ime, Data 5.0 ns
thHold T ime, Address 20 ns
SN74LS259
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5
ts
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
Figure 2. Turn-on and Turn-off Delays,
Data to Output
Figure 3. Turn-on and Turn-off Delays,
Address to Output
NOTES:
1. The Address to Enable Setup T ime is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
OTHER CONDITIONS: C = H, A = STABLE
OTHER CONDITIONS: E = L, C = H, A = STABLE
OTHER CONDITIONS: E = L, C = L, D = H OTHER CONDITIONS: C = H, A = STABLE
OTHER CONDITIONS: E = H
1.3 V
tPHL tPLH
1.3 V
D
E
Q
1.3 V 1.3 V
1.3 V1.3 V
tPLH
tPHL
D
Q
1.3 V
1.3 V
tPHL
C
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
A1
A1
Q1
tPLH
D
E
Q
th(H) th(L)
1.3 V
OTHER CONDITIONS: C = H
STABLE ADDRESS
A
E
ts(H) ts(L)
tPHL
twtw
Q=D Q=D
AC WAVEFORMS
Figure 4. Setup and Hold Time, Data to Enable
Figure 5. Turn-on Delay, Clear to Output
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
SN74LS259
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6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
SN74LS259
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7
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
SN74LS259
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