Energy Metering IC with Autocalibration ADE9153A Data Sheet FEATURES GENERAL DESCRIPTION mSure autocalibration Automatic calibration based on a direct measurement of the full signal path Calibration procedure not requiring a reference meter mSure autocalibration Class 1 meter guaranteed 3 high performance ADCs 88 dB SNR High gain current channel: 26.04 mV peak, 18.4 mV rms input at highest gain setting Advanced metrology feature set WATT, VAR, VA, Wh, VARh, and VAh Supports active energy standards: IEC 62053-21; IEC 62053-22; EN50470-3; OIML R46; and ANSI C12.20 Supports reactive energy standards: IEC 62053-23 and IEC 62053-24 Current and voltage rms measurement Power quality measurements Operating temperature, industrial range: -40C to +85C The ADE9153A1 is a highly accurate, single-phase, energy metering IC with autocalibration. The mSure(R) autocalibration feature allows a meter to automatically calibrate the current and voltage channels without using an accurate source or an accurate reference meter when a shunt resistor is used as a current sensor. Class 1 and Class 2 meters are supported by mSure autocalibration. The ADE9153A incorporates three high performance analogto-digital converters (ADCs), providing an 88 dB signal-to-noise ratio (SNR). The ADE9153A offers an advanced metrology feature set of measurements like line voltage and current, active energy, fundamental reactive energy, and apparent energy calculations, and current and voltage rms calculations. ADE9153A includes power quality measurements such as zero crossing detection, line period calculation, angle measurement, dip and swell, peak and overcurrent detection, and power factor measurements. Each input channel supports independent and flexible gain stages. Current Channel A is ideal for shunts, having a flexible gain stage and providing full-scale input ranges from 62.5 mV peak down to 26.04 mV peak. Current Channel B has gain stages of 1x, 2x, and 4x for use with current transformers (CTs). A high speed, 10 MHz, serial peripheral interface (SPI) port allows access to the ADE9153A registers. APPLICATIONS Single-phase energy meters Energy and power measurement Street lighting Smart power distribution system Machine health Note that throughout this data sheet, multifunction pins, such as ZX/DREADY/CF2, are referred to either by the entire pin name or by a single function of the pin, for example, CF2, when only that function is relevant. The ADE9153A operates from a 3.3 V supply and is available in a 32-lead LFCSP package. TYPICAL APPLICATIONS CIRCUIT IAMS IBMS mSure VOLTAGE DRIVER SINC AND DECIMATION ADC METROLOGY ENGINE PGA ADC WATT, VA, VAR, WATT-HR, VA-HR, VAR-HR, IRMS, VRMS mSure CURRENT DRIVER IBN AGND/DGND LOAD PGA CLOCK GENERATION CF GENERATION ZERO CROSSING CLKIN CLKOUT CF1 ZX/DREADY/CF2 mSure DETECTOR ADC TEMPERATURE SENSOR ADE9153A IRQ IBP B DIGITAL SIGNAL PROCESSING SPI INTERFACE SAR SS SCLK MISO/TX MOSI/RX 16519-001 NEUTRAL PHASE AGND/DGND VAMS VAN RSMALL RBIG VAP AGND/DGND IAN RSHUNT IAP Figure 1. 1 Protected by U.S. Patents 8,350,558; 8,010,304; WO2013038176 A3; 0113507 A1; 0253102 A1; 0354266 A1; and 0154029 A1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADE9153A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 mSure Autocalibration Feature................................................. 21 Applications ....................................................................................... 1 Measurements ............................................................................. 22 General Description ......................................................................... 1 Power Quality Measurements................................................... 26 Typical Applications Circuit............................................................ 1 Applications Information .............................................................. 29 Revision History ............................................................................... 2 Interrupts/Events ........................................................................ 29 Specifications..................................................................................... 3 IRQ Pin Interrupts ...................................................................... 29 Autocalibration ............................................................................. 6 Servicing Interrupts ................................................................... 29 SPI Timing Characteristics ......................................................... 7 CF2/ZX/DREADY Event Pin ................................................... 29 Absolute Maximum Ratings............................................................ 8 Accessing On-Chip Data ............................................................... 30 Thermal Resistance ...................................................................... 8 SPI Protocol Overview .............................................................. 30 ESD Caution .................................................................................. 8 UART Interface ........................................................................... 30 Pin Configuration and Function Descriptions ............................. 9 Communication VerifIcation Registers ................................... 31 Typical Performance Characteristics ........................................... 11 CRC of Configuration Registers............................................... 31 Energy Linearity Over Supply and Temperature ................... 11 Configuration Lock .................................................................... 31 Energy Error Over Frequency and Power Factor................... 13 Register Information ...................................................................... 32 RMS Linearity Over Temperature and RMS Error Over Frequency .................................................................................... 14 Register Summary ...................................................................... 32 Signal-To-Noise Ratio (SNR) Performance Over Dynamic Range ............................................................................................ 17 Test Circuit ...................................................................................... 18 Register Details ........................................................................... 36 Outline Dimensions ....................................................................... 50 Ordering Guide .......................................................................... 50 Terminology .................................................................................... 19 Theory of Operation ...................................................................... 21 REVISION HISTORY 2/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 50 Data Sheet ADE9153A SPECIFICATIONS VDD = 2.97 V to 3.63 V, AGND = DGND = 0 V, on-chip reference, CLKIN = 12.288 MHz, TMIN to TMAX = -40C to +85C, and TA = 25C (typical), unless otherwise noted. Table 1. Parameter ACCURACY (MEASUREMENT ERROR PER PHASE) Total Active Energy Fundamental Reactive Energy Total Apparent Energy RMS Current (IRMS) and Apparent Power (VA) RMS Voltage (VRMS) Active Power (WATT), Fundamental Reactive Power (VAR) One Cycle RMS Current and Voltage Refreshed Each Half Cycle Line Period Measurement Voltage to Current Angle Measurement Min Typ Max Unit 0.1 % 0.2 0.25 % % 0.5 0.1 % % 0.2 0.25 % % 0.5 0.1 % % 0.2 0.25 % % 0.5 0.1 % % 0.2 % 0.3 % 0.6 % 0.2 0.25 % % 0.5 % 0.5 % 1 % 0.001 0.036 Hz Degrees Rev. 0 | Page 3 of 50 Test Conditions/Comments Percentage of the typical value derived from comparing the actual value with the typical-based expected values when a 10:1 signal is applied Over a dynamic range of 3000 to 1, 10 sec accumulation programmable gain amplifier (PGA), AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 10,000 to 1, 30 sec accumulation; AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 3000 to 1, 10 sec accumulation; AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 10,000 to 1, 30 sec accumulation AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 1000 to 1, 1 sec accumulation; AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 3000 to 1, 10 sec accumulation AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Over a dynamic range of 1000 to 1, 1 sec (averaging) AI_PGAGAIN = 16x, BI_PGAGAIN = 1x Over a dynamic range of 1000 to 1, 1 sec (averaging), AI_PGAGAIN = 38.4x Over a dynamic range of 3000 to 1, 1 sec (averaging), AI_PGAGAIN = 16x, BI_PGAGAIN = 1x Over a dynamic range of 3000 to 1, 1 sec (averaging), AI_PGAGAIN = 38.4x Over a dynamic range of 1000 to 1, 1 sec (averaging) Over a dynamic range of 3000 to 1, 1 sec, AI_PGAGAIN = 16x Over a dynamic range of 3000 to 1, 1 sec, AI_PGAGAIN = 38.4x Over a dynamic range of 500 to 1 on current and 250 to 1 on voltage Over a dynamic range of 1000 to 1 on current and 500 to 1 on voltage Resolution at 50 Hz Resolution at 50 Hz ADE9153A Parameter ADC PGA Gain Settings (xI_PGAGAIN) Current Channel A (Phase Shunt) Current Channel B (Neutral CT) Pseudo Differential Input Voltage Range (IAP - IAN) (VAP - VAN) Differential Input Voltage Range (IBP - IBN) Maximum Operating Voltage on the Analog Input Pins VAP IAP, IAN IBP, IBN SNR Current Channel A AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Current Channel B BI_PGAGAIN = 1x BI_PGAGAIN = 4x Voltage Channel ADC Output Pass Band (0.1 dB) ADC Output Bandwidth (-3 dB) Crosstalk AC Power Supply Rejection Ratio (AC PSRR) Current Channel A Current Channel B Voltage Channel AC Common-Mode Rejection Ratio (AC CMRR) ADC Gain Error Current Channel A Current Channel B Voltage Channel ADC Offset Current Channel A AI_PGAGAIN = 16x AI_PGAGAIN = 38.4x Current Channel B Voltage Channel ADC Offset Drift Data Sheet Min Typ Max 16, 24, 32, 38.4 1, 2, 4 Unit Test Conditions/Comments V/V PGA gain setting is referred to as gain V/V PGA gain setting is referred to as gain -1/gain -0.5 +1/gain +0.5 V V 44.19 mV rms on Current Channel A, AI_PGAGAIN = 16x 353.6 mV rms on voltage channel -1/gain +1/gain V 707 mV rms on Current Channel B 0 -0.1125 0.35 1.35 +0.1125 1.45 V V V Voltage on the pin with respect to ground Voltage on the IAx pin with respect to ground Voltage on the IBx pin with respect to ground; internal common-mode voltage at IBx pin = 0.9 V 90 88 dB dB VIN is a full-scale signal VIN is a full-scale signal 90 78 87 0.672 1.6 -120 dB dB dB kHz kHz dB VIN is a full-scale signal VIN is a full-scale signal VIN is a full-scale signal -115 -100 -100 -120 dB dB dB dB At 50 Hz or 60 Hz; see the Terminology section At 50 Hz; see the Terminology section At 50 Hz Percentage of error from the ideal value; see the Terminology section 0.2 -2.0 -0.8 1.5 3.5 3.0 % % % +0.04 -0.02 -0.26 +0.35 0.5 0.1 0.05 0.37 0.75 5 mV mV mV mV V/C See the Terminology section Rev. 0 | Page 4 of 50 See the Terminology section Data Sheet Parameter Channel Drift (PGA, ADC, Internal Voltage Reference) Current Channel A Current Channel B Voltage Channel Differential Input Impedance (DC) Current Channel A Current Channel B Voltage Channel INTERNAL VOLTAGE REFERENCE Voltage Reference Temperature Coefficient ADE9153A Min Max Unit 5 20 20 30 50 50 ppm/C ppm/C ppm/C Test Conditions/Comments See the Terminology section See the Terminology section 5000 100 240 TEMPERATURE SENSOR Temperature Accuracy Temperature Readout Step Size CRYSTAL OSCILLATOR Input Clock Frequency Internal Capacitance on CLKIN, CLKOUT Internal Feedback Resistance Between CLKIN and CLKOUT Transconductance (gm) EXTERNAL CLOCK INPUT Input Clock Frequency, CLKIN Duty Cycle CLKIN Logic Input Voltage High, VINH Low, VINL LOGIC INPUTS--MOSI/RX, SCLK Input Voltage High, VINH Low, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS MISO/TX, IRQ Output Voltage High, VOH Low, VOL Internal Capacitance, CIN CF1, CF2 Output Voltage High, VOH Low, VOL Internal Capacitance, CIN LOW DROPOUT REGULATORS (LDOs) AVDD DVDD VDD2P5 Typ 7800 113 256 k k k 1.25 5 30 V ppm/C 0.3 C C 5 12.287 12.288 4 12.289 MHz pF 2.58 M 5 8.7 mA/V 12.287 45:55 12.288 50:50 12.289 55:45 MHz Nominal = 1.25 V 1 mV TA = 25C at REFIN TA = -40C to +85C; tested during device characterization -40C to +85C All specifications at CLKIN = 12.288 MHz; the crystal oscillator is designed to interface with 100 W crystals 100 ppm 100 ppm 3.3 V tolerant 1.2 0.5 V V 0.8 11 10 V V A pF 0.4 10 V V pF ISOURCE = 4 mA ISINK = 3 mA 0.8 10 V V pF ISOURCE = 6 mA ISINK = 6 mA 2.4 2.5 2.4 1.9 1.7 2.5 V V V Rev. 0 | Page 5 of 50 VIN = 0 V ADE9153A Parameter POWER SUPPLY VDD Pin VDD Pin Current, IDD Data Sheet Min Typ 2.97 9.3 8.5 Max Unit 3.63 12 V mA A Test Conditions/Comments For specified performance Minimum = 3.3 V - 10%; maximum = 3.3 V + 10% Consumption in operation, without mSure running When the ADE9153A is held in reset AUTOCALIBRATION VDD = 3.3 V, AGND = DGND = 0 V, on-chip reference, CLKIN = 12.288 MHz, TA = 25C (typical), IMAX = 60 A rms, VNOM = 230 V, RSHUNT_PHASE = 200 , turns ratio on CTNEUTRAL = 2500:1, burden on CTNEUTRAL = 16.4 , and CTNEUTRAL voltage potential divider of 1000:1 (990 k and 1 k resistors), unless otherwise noted. The values in Table 2 are specified for the system described; if the shunt or voltage potential divider is changed, the values in Table 2 change as well. For example, increasing the shunt value decreases the calibration time required for the phase current channel; conversely, decreasing the shunt value increases the calibration time. Table 2. Parameter AUTOCALIBRATION Current Channel A (Phase Shunt) Calibration Time Turbo Mode 0.353% Accuracy Target 0.25% Accuracy Target Normal Mode 0.353% Accuracy Target 0.25% Accuracy Target Current Consumption Turbo Mode Normal Mode Current Channel (Neutral CT) Calibration Time 0.5 % Accuracy Target, Turbo Mode Normal Mode Current Consumption Turbo Mode Normal Mode Voltage Channel Calibration Time 0.353% Accuracy Target 0.25% Accuracy Target Current Consumption Min Typ Max Unit Test Conditions/Comments TA = 25C 5 C For more information on the power modes and calibration times, see the mSure Autocalibration Feature section 16 45 sec sec 40 115 sec sec 16 9.3 mA rms mA rms Additional consumption from 3.3 V supply With peak consumption of 33 mA With peak consumption of 19 mA For more information, see the mSure Autocalibration Feature section 12 20 sec sec 16 9.3 mA rms mA rms Additional consumption from 3.3 V supply With peak consumption of 33 mA With peak consumption of 19 mA For more information, see the mSure Autocalibration Feature section 25 85 <1 sec sec mA rms Rev. 0 | Page 6 of 50 Additional consumption from 3.3 V supply Data Sheet ADE9153A SPI TIMING CHARACTERISTICS Table 3. Parameter SS to SCLK Edge SCLK Frequency SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Data Output Fall Time Data Output Rise Time SCLK Fall Time SCLK Rise Time MISO Disable After SS Rising Edge SS High After SCLK Edge Symbol tSS fSCLK tSL tSH tDAV tDSU tDHD tDF tDR tSF tSR tDIS tSFS Min 10 Typ Max 10 40 40 40 10 10 10 10 10 10 100 0 SS tSS tSFS SCLK tSL tSH tDAV tSF tSR tDIS MSB MISO INTERMEDIATE BITS tDF LSB tDR INTERMEDIATE BITS MSB IN MOSI LSB IN 16519-002 tDSU tDHD Figure 2. SPI Interface Timing Diagram Rev. 0 | Page 7 of 50 Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ADE9153A Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Parameter VDD to AGND/DGND Analog Input Voltage to AGND/DGND, IAP, IAN, IBP, IBN, VP, VN1 Reference Input Voltage to AGND/DGND Digital Input Voltage to AGND/DGND Digital Output Voltage to AGND/DGND Operating Temperature Industrial Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec)2 Electrostatic Discharge (ESD) Human Body Model (HBM) Machine Model (MM) Field Induced Charged Device Model (FICDM) 1 Rating -0.3 V to +3.96 V -0.75 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +3.96 V -0.3 V to +3.96 V THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. -40C to +85C -65C to +150C 260C JA and JC are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 4 kV 200 V 1.25 kV Table 5. Thermal Resistance Package Type CP-32-123 The rating of -0.75 V on the analog input pins is limited by protection diodes inside the ADE9153A. These pins were tested with 7.5 mA going to the pin to simulate a 30x overcurrent condition on the channel, based on the test circuit antialiasing resistor of 150 . 2 Analog Devices, Inc., recommends that reflow profiles used in soldering RoHS-compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard. 1 JA1 27.83 JC2 2.10 The JA measurement uses a 2S2P JEDEC test board. The JC measurement uses a 1S0P JEDEC test board. 3 All thermal measurements comply with JESD51. 2 ESD CAUTION Rev. 0 | Page 8 of 50 Unit C/W Data Sheet ADE9153A 32 31 30 29 28 27 26 25 SS SCLK MISO/TX MOSI/RX RESET IRQ CF1 ZX/DREADY/CF2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADE9153A TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VDD FA0 FA1 MSH DGND IBMS REFIN AGND NOTES 1. EXPOSED PAD. THE EXPOSED PAD MUST BE LEFT FLOATING. 16519-003 AGND VDDOUT2P5 IBN IBP VAMS VAP VAN AVDDOUT 9 10 11 12 13 14 15 16 DGND DVDDOUT CLKOUT CLKIN VDD IAMS IAN IAP Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 20 Mnemonic DGND 2 DVDDOUT 3 CLKOUT 4 CLKIN 5, 24 VDD 6 IAMS 7, 8 IAN, IAP 9, 17 AGND 10 VDDOUT2P5 11, 12 IBN, IBP 13 VAMS 14, 15 VAP, VAN 16 AVDDOUT Description Digital Ground. These pins provide the ground reference for the digital circuitry in the ADE9153A and form the return path for the Current Channel A and Current Channel B mSure currents. 1.7 V Output of the Digital LDO Regulator. Decouple this pin with a 0.1 F ceramic capacitor in parallel with a 4.7 F ceramic capacitor to Pin 1 (DGND). Do not connect external load circuitry to this pin. Clock Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. An external buffer is required to drive other circuits from CLKOUT. Master Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. See the ADE9153A Technical Reference Manual for details on choosing a suitable crystal. Alternatively, an external clock can be provided at the logic input. Supply Voltage. These pins provide the supply voltage for the ADE9153A. Maintain the supply voltage at 3.3 V 10% for specified operation. Decouple these pins to AGND or DGND with a 4.7 F capacitor in parallel with a ceramic 0.1 F capacitor. Output for the mSure Current Driver on Current Channel A (Phase Current Channel). IAMS is connected to the positive end of the shunt on the phase (to the side of the shunt closest to the load, on the same side as IAP). Analog Inputs for Current Channel A (Phase Current Channel). The IAP and IAN current channel is ideal for use with shunts. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of 125 mV. These channels have an internal PGA gain of 16, 24, 32, and 38.4. Use these pins with the related input circuitry, as shown in Figure 37. Ground Reference for the Analog Circuitry. See Figure 37 for information on how to connect these ground pins. 2.5 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 F ceramic capacitor in parallel with a 4.7 F ceramic capacitor to Pin 9 (AGND). Do not connect external load circuitry to this pin. Analog Inputs for Current Channel B (Neutral Current Channel). The IBP and IBN current channel is ideal for use with CTs. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of 1000 mV. These channels have an internal PGA gain of 1, 2, or 4. Use these pins with the related input circuitry, as shown in Figure 37. Path for mSure on the Voltage Channel. VAMS is connected to the bottom end of the resistor divider, which is typically connected to the phase, as shown in Figure 1. Analog Inputs for the Voltage Channels. The VAP (positive) and VAN (negative) inputs are fully differential with an input level of 0.1 V to 1.7 V. Use these pins with the related input circuitry, as shown in Figure 37. 1.9 V Output of the Analog LDO Regulator. Decouple this pin with a 0.1 F ceramic capacitor in parallel with a 4.7 F ceramic capacitor to Pin 17 (AGND). Do not connect external load circuitry to this pin. Rev. 0 | Page 9 of 50 ADE9153A Pin No. 18 Mnemonic REFIN 19 IBMS 21 MSH 22 23 25 FA1 FA0 ZX/DREADY/CF2 26 CF1 27 IRQ 28 29 30 31 RESET MOSI/RX MISO/TX SCLK 32 SS EPAD Data Sheet Description Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V. Decouple this pin to Pin 17 (AGND) with a 0.1 F ceramic capacitor in parallel with a 4.7 F ceramic capacitor. After reset, the on-chip reference is enabled. An external reference source with 1.25 V 0.01% can also be connected at this pin. Output for the mSure Current Driver on Current Channel B (Neutral Current Channel). IBMS is connected to a wire leading through the primary winding of the CT and back to Pin 20 (DGND). External Capacitor Pin for the mSure Current Driver. Connect an external 0.47 F ceramic capacitor between the MSH pin and Pin 20 (DGND). mSure Capacitor, Positive Terminal. Connect an external capacitor of value 0.47 F between FA0 and FA1. mSure Capacitor, Negative Terminal. Connect an external capacitor of value 0.47 F between FA0 and FA1. Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel section. This pin can be configured to output CF2 if necessary. See the description for CF1. Calibration Frequency (CF) Logic Outputs. The CF1 and CF2 outputs provide proportional power information based on the CFxSEL bits in the CFMODE register. Use these outputs for operational and calibration purposes. Scale the full-scale output frequency by writing to the CFxDEN registers, respectively. Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for information about events that trigger interrupts. Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for a minimum of 10 s. Data Input for the SPI Port (MOSI) and Receive Pin for the UART (RX). Data Output for the SPI Port (MISO) and Transmit Pin for the UART (TX). Serial Clock Input for the SPI Port. All serial data transfers are synchronized to this clock. The SCLK pin has a Schmitt trigger input for use with a clock source that has a slow edge transition time (for example, transitioning to opto-isolator outputs). Slave Select for the SPI Port. Exposed Pad. The exposed pad must be left floating. Rev. 0 | Page 10 of 50 Data Sheet ADE9153A TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE Energy characteristics obtained from a 50% of full scale, sinusoidal, 50 Hz voltage signal; the sinusoidal, 50 Hz, swept amplitude current signal is from 100% of full scale to 0.01% of full scale. 0.50 0.25 0 -0.25 -0.25 -0.50 -0.50 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 4. Total Active Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1, Current Channel A (AI) PGA Gain = 16x 0.75 0.50 -0.75 0.01 16519-004 0.1 0.75 TA = -40C TA = +25C TA = +85C 0.50 ERROR (%) ERROR (%) -0.25 -0.50 -0.50 1 10 100 -0.75 0.01 16519-005 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 5. Total Active Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1, AI PGA Gain = 38.4x 0.1 1 10 100 Figure 8. Total Apparent Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1, AI PGA Gain = 16x 0.75 TA = -40C TA = +25C TA = +85C 0.50 TA = -40C TA = +25C TA = +85C 0.25 ERROR (%) ERROR (%) TA = -40C TA = +25C TA = +85C PERCENTAGE OF FULL-SCALE CURRENT (%) 0.25 0 0 -0.25 -0.25 -0.50 -0.50 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 -0.75 0.01 16519-006 -0.75 0.01 100 0 -0.25 0.50 10 0.25 0 0.75 1 Figure 7. Fundamental Reactive Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 0, AI PGA Gain = 38.4x 0.25 -0.75 0.01 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) 16519-007 ERROR (%) ERROR (%) 0.25 -0.75 0.01 TA = -40C TA = +25C TA = +85C 16519-008 0.50 0.75 TA = -40C TA = +25C TA = +85C Figure 6. Fundamental Reactive Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 0, AI PGA Gain = 16x 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 16519-009 0.75 Figure 9. Total Apparent Energy Error as a Percentage of Full-Scale Current over Temperature, Power Factor = 1, AI PGA Gain = 38.4x Rev. 0 | Page 11 of 50 ADE9153A 0.75 0.25 0.25 ERROR (%) 0.50 0 0 -0.25 -0.25 -0.50 -0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 10. Total Active Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25C, AI PGA Gain = 16x 0.75 0.50 -0.75 0.01 16519-110 -0.75 0.01 0.75 2.97V 3.3V 3.63V 0.50 ERROR (%) ERROR (%) -0.25 -0.50 -0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) 2.97V 3.3V 3.63V -0.75 0.01 16519-111 -0.75 0.01 Figure 11. Total Active Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25C, AI PGA Gain = 38.4x 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 14. Total Apparent Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25C, AI PGA Gain = 16x 0.75 2.97V 3.3V 3.63V 0.50 2.97V 3.3V 3.63V 0.25 ERROR (%) 0.25 ERROR (%) 100 0 -0.25 0 0 -0.25 -0.25 -0.50 -0.50 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 -0.75 0.01 16519-112 -0.75 0.01 10 0.25 0 0.50 1 Figure 13. Fundamental Reactive Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 0, TA = 25C, AI PGA Gain = 38.4x 0.25 0.75 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) 16519-114 ERROR (%) 0.50 2.97V 3.3V 3.63V 16519-113 2.97V 3.3V 3.63V Figure 12. Fundamental Reactive Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 0, TA = 25C, AI PGA Gain = 16x 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 16519-115 0.75 Data Sheet Figure 15. Total Apparent Energy Error as a Percentage of Full-Scale Current over Supply Voltage, Power Factor = 1, TA = 25C, AI PGA Gain = 38.4x Rev. 0 | Page 12 of 50 Data Sheet ADE9153A ENERGY ERROR OVER FREQUENCY AND POWER FACTOR Energy characteristics obtained from a 50% of full scale, sinusoidal, 50 Hz voltage signal and a 10% of full scale, sinusoidal, 50 Hz, current signal over a variable frequency between 45 Hz and 65 Hz. 0.10 0.10 POWER FACTOR = +1 POWER FACTOR = +0.5 POWER FACTOR = -0.5 0.05 ERROR (%) 0 -0.05 -0.05 40 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 16. Total Active Energy Error vs. Line Frequency, Power Factor = -0.5, +0.5, and +1, AI PGA Gain = 38.4x 0.10 -0.10 16519-116 -0.10 ERROR (%) 0 50 55 60 LINE FREQUENCY (Hz) 65 70 16519-117 -0.05 45 45 50 55 60 65 70 Figure 18. Total Apparent Energy Error vs. Line Frequency, AI PGA Gain = 38.4x POWER FACTOR = -0.866 POWER FACTOR = 0 POWER FACTOR = +0.866 40 40 LINE FREQUENCY (Hz) 0.05 -0.10 0 16519-118 ERROR (%) 0.05 Figure 17. Fundamental Reactive Energy Error vs. Line Frequency, Power Factor = -0.866, +0.866, and 0, AI PGA Gain = 38.4x Rev. 0 | Page 13 of 50 ADE9153A Data Sheet RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY RMS linearity obtained with a sinusoidal, 50 Hz current and voltage signals with a swept amplitude from 100% of full scale to 0.033% of full scale. 0.50 0.25 0 0 -0.25 -0.25 -0.50 -0.50 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 19. Current Channel A RMS Error as a Percentage of Full-Scale Current over Temperature, AI PGA Gain = 16x 0.75 0.50 -0.75 0.01 16519-126 0.1 ERROR (%) ERROR (%) 0.25 0 -0.50 -0.50 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) 16519-127 -0.25 Figure 20. Current Channel A RMS Error as a Percentage of Full-Scale Current over Temperature, AI PGA Gain = 38.4x -0.75 0.01 0.75 TA = -40C TA = +25C TA = +85C 100 TA = -40C TA = +25C TA = +85C 0.50 0.25 ERROR (%) ERROR (%) 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 23. Current Channel A RMS Offset Error as a Percentage of Full-Scale Current over Temperature, AI PGA Gain = 16x 0.25 0 0 -0.25 -0.25 -0.50 -0.50 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 -0.75 0.01 16519-128 -0.75 0.01 100 TA = -40C TA = +25C TA = +85C 0.50 -0.25 0.50 10 0.75 TA = -40C TA = +25C TA = +85C 0 0.75 1 Figure 22. Voltage Channel RMS Error as a Percentage of Full-Scale Current over Temperature 0.25 -0.75 0.01 0.1 PERCENTAGE OF FULL-SCALE CURRENT (%) 16519-129 ERROR (%) ERROR (%) 0.25 -0.75 0.01 TA = -40C TA = +25C TA = +85C 16519-130 0.50 0.75 TA = -40C TA = +25C TA = +85C Figure 21. Current Channel B RMS Error as a Percentage of Full-Scale Current over Temperature 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 16519-131 0.75 Figure 24. Current Channel A RMS Offset Error as a Percentage of Full-Scale Current over Temperature, AI PGA Gain = 38.4x Rev. 0 | Page 14 of 50 Data Sheet ADE9153A 0.75 0.10 TA = -40C TA = +25C TA = +85C 0.50 0.05 ERROR (%) ERROR (%) 0.25 0 0 -0.25 -0.05 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) -0.10 16519-132 -0.75 0.01 50 55 60 65 70 Figure 27. Current Channel A RMS Error vs. Line Frequency 0.10 TA = -40C TA = +25C TA = +85C 0.50 45 LINE FREQUENCY (Hz) Figure 25. Current Channel B RMS Offset Error as a Percentage of Full-Scale Current over Temperature 0.75 40 16519-134 -0.50 0.05 ERROR (%) ERROR (%) 0.25 0 0 -0.25 -0.05 0.1 1 10 PERCENTAGE OF FULL-SCALE CURRENT (%) 100 Figure 26. Voltage Channel RMS Offset Error as a Percentage of Full-Scale Current over Temperature Rev. 0 | Page 15 of 50 -0.10 40 45 50 55 60 65 70 LINE FREQUENCY (Hz) Figure 28. Current Channel B RMS Error vs. Line Frequency 16519-135 -0.75 0.01 16519-133 -0.50 ADE9153A Data Sheet 0.05 0.05 ERROR (%) 0.10 0 45 50 55 60 65 70 LINE FREQUENCY (Hz) -0.10 16519-136 40 50 55 60 65 70 LINE FREQUENCY (Hz) 0.10 0.05 0.05 ERROR (%) 0.10 ERROR (%) 45 Figure 31. Current Channel B RMS Overcurrent Error vs. Line Frequency Figure 29. Voltage Channel RMS Error vs. Line Frequency 0 0 -0.05 -0.05 40 45 50 55 60 LINE FREQUENCY (Hz) 65 70 -0.10 16519-137 -0.10 40 16519-138 -0.05 -0.05 -0.10 0 Figure 30. Current Channel A RMS Overcurrent Error vs. Line Frequency 40 45 50 55 60 LINE FREQUENCY (Hz) 65 70 16519-139 ERROR (%) 0.10 Figure 32. Voltage Channel RMS Overcurrent Error vs. Line Frequency Rev. 0 | Page 16 of 50 Data Sheet ADE9153A 100 98 98 96 96 94 94 90 90 88 88 86 -25 -20 -15 -10 -5 0 5 INPUT SIGNAL (dBFS) 86 -25 98 98 96 96 94 94 SNR (dB) 100 92 88 88 -10 -5 INPUT SIGNAL (dBFS) 0 5 16519-142 90 -15 -10 -5 0 5 92 90 -20 -15 Figure 35. Current Channel B SNR with Respect to Full Scale 100 86 -25 -20 INPUT SIGNAL (dBFS) Figure 33. Current Channel A SNR with Respect to Full Scale, AI PGA Gain = 16x SNR (dB) 92 Figure 34. Current Channel A SNR with Respect to Full Scale, AI PGA Gain = 38.4x Rev. 0 | Page 17 of 50 86 -25 -20 -15 -10 -5 0 INPUT SIGNAL (dBFS) Figure 36. Voltage Channel SNR with Respect to Full Scale 5 16519-144 92 16519-143 SNR (dB) 100 16519-140 SNR (dB) SIGNAL-TO-NOISE RATIO (SNR) PERFORMANCE OVER DYNAMIC RANGE ADE9153A Data Sheet TEST CIRCUIT 2 4.7F DVDDOUT 0.1F 5 24 VDD PHASE 0.1F VDD 4.7F 4.7F AVDDOUT 16 0.1F 150 7 IAN REFIN 18 0.1F SHUNT 0.1F 4.7F 0.1F 4.7F FA1 22 0.1F 150 8 IAP 6 IAMS ZX/DREADY/CF2 25 TO MCU CF1 26 TO MCU IRQ 27 TO MCU RESET 28 TO MCU MOSI/RX 29 TO MCU MISO/TX 30 TO MCU SCLK 31 TO MCU SS 32 TO MCU 10 VDDOUT2P5 4.7F TO LOAD NEUTRAL 0.1F 150 ADE9153A 11 IBN 0.1F Rb 0.1F 150 0.47F FA0 23 12 IBP 19 IBMS 13 VAMS CLKOUT 15 VAN 1k 3 22pF 12.288pF 0.15F 330k 330k 330k 22pF CLKIN 4 14 VAP AGND AGND 1 20 9 17 16519-010 DGND 0.1F DGND 21 MSH 4.7F Figure 37. Test Circuit Rev. 0 | Page 18 of 50 Data Sheet ADE9153A TERMINOLOGY Crosstalk Crosstalk is measured by grounding one channel and applying a full-scale 50 Hz or 70 Hz signal on all the other channels. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 200 sec. Crosstalk is expressed in decibels. ADC Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when an external voltage reference of 1.25 V is used. The difference is expressed as a percentage of the ideal code and represents the overall gain error of one channel. Differential Input Impedance (DC) The differential input impedance represents the impedance between the IAP and IAN pair, the IBP and IBN pair, or the VAP and VAN pair. AC Power Supply Rejection (AC PSRR) AC PSRR quantifies the measurement error as a percentage of reading when the dc power supply is VNOM and modulated with ac and the inputs are grounded. For the ac PSRR measurement, 100 sec of samples are captured with nominal supplies (3.3 V) and a second set is captured with an additional ac signal (233 mV rms at 100 Hz) introduced onto the supplies. Then, the PSRR is expressed as PSRR = 20 log10(VRIPPLE/VNOMINAL). ADC Offset ADC offset is the difference between the average measured ADC output code with both inputs connected to ground and the ideal ADC output code of zero. ADC offset is expressed in mV. ADC Offset Drift over Temperature The ADC offset drift is the change in offset over temperature. It is measured at -40C, +25C, and +85C. Calculate the offset drift over temperature as follows: Drift Offset40C Offset 25C , 40C (25C) max Offset 85C Offset 25C 85C (25C) ADC Output Pass Band The ADC output pass band is the bandwidth within 0.1 dB, resulting from the digital filtering in the sinc4 filter and sinc4 filter + infinite impulse response (IIR), low-pass filter (LPF). Offset drift is expressed in V/C. Channel Drift over Temperature The channel drift over temperature coefficient includes the temperature variation of the PGA and ADC gain when using the internal voltage reference. This coefficient represents the overall temperature coefficient of one channel. With the internal voltage reference, the ADC gain is measured at -40C, +25C, and +85C. Then, the temperature coefficient is calculated as follows: Drift max Gain40C Gain 25C , Gain(25C) 40C 25C Gain 85C Gain 25C Gain(25C) 85C 25C Gain drift is measured in ppm/C. Signal-to-Noise Ratio (SNR) SNR is calculated by inputting a 50 Hz signal, and acquiring samples over 10 sec. The amplitudes for each frequency, up to the bandwidth given in Table 1 as the ADC output bandwidth (-3 dB), are calculated. To determine the SNR, the signal at 50 Hz is compared to the sum of the power from all the other frequencies, removing power from its harmonics. The value for SNR is expressed in decibels. ADC Output Bandwidth The ADC output bandwidth is the bandwidth within -3 dB, resulting from the digital filtering in the sinc4 and sinc4 + IIR LPF. Speed of Convergence The speed of convergence is the time it takes for mSure to reach a certain level of accuracy. This speed, or time required, is logarithmically proportional to the required accuracy. In other words, if a greater accuracy is required in mSure autocalibration, the time required increases logarithmically. Similarly, the speed is related to the power mode in which mSure is being run: the lower the power mode, the slower the speed of convergence. This relationship is shown in Table 2 for the specified system. The speed of convergence determines the time it takes to complete the autocalibration process and to reach a certain specified accuracy. Rev. 0 | Page 19 of 50 ADE9153A Data Sheet Absolute Accuracy Absolute accuracy takes into account the accuracy of the mSure reference. The speed of convergence to reach this accuracy depends on the time of an mSure autocalibration run. The longer the time of an mSure autocalibration run, the greater the accuracy. Conversion Constant In this data sheet, the conversion constant (CC) is the value that mSure returns when estimating the transfer function of the sensor and front end. This value is in units of A/code or V/code, depending on which channel the estimation occurs. Certainty of Estimation The certainty of the mSure estimation, which is also referred to as simply certainty (CERT), is a metric of the precision of the mSure measurement. This certainty is displayed as a percentage; the lower the value, the more confidence there is in the estimation value. Rev. 0 | Page 20 of 50 Data Sheet ADE9153A THEORY OF OPERATION The ADE9153A offers mSure autocalibration technology, enabling the automatic calibration of the current and voltage channel accurate, automatic calibration. Autocalibration features have two main components: absolute accuracy and the speed of convergence (see the Terminology section for more details). When performing autocalibration, the current channels, AI and BI, can be run in two power modes: turbo mode and normal mode. The power mode is a trade-off between the speed of convergence and current consumption. In turbo mode, the speed of convergence is 4x faster and the current consumption is only 2x higher when compared to normal mode, which means that the average consumption over a full run is less than in low power mode, but the instantaneous consumption is higher, as shown in Figure 38. POWER CONSUMPTION NORMAL MODE p0 + 2 x p1 0 t1 4 x t1 TIME The MS_TIMEOUT bit is set if autocalibration is left to run for more than the 600 sec limit of the system. If this interrupt is triggered, ensure that the runs of mSure are being correctly handled in terms of enabling and disabling mSure when appropriate. The MS_SHIFT bit is set when there is a shift in the CC value that occurs in the middle of a run. This setting means that an event at the meter level changed the CC before the run finished and another run must be performed to achieve a more accurate value. The certainty in this case is high, >50,000 ppm. Figure 39 to Figure 41 show the speed of convergence of the mSure result (the CC value). As the value of the shunt increases, or as the gain of the PGA increases, the speed of convergence also increases due to the signal size being larger. These are both parameters that must be set based on the overall system, taking into account factors such as the maximum current being measured. Figure 39 to Figure 41 show how the speed of convergence is influenced from factors in a system. 1.000 300 500 1000 2000 ABSOLUTE ACCURACY TARGET (%) Figure 38. mSure Autocalibration Power Modes to Same Certainty The ADE9153A can perform the autocalibration of a meter without requiring an accurate source or reference meter. By powering up the meter, the CC of each channel can be measured, and that requirement alone is enough to perform the autocalibration. 0.353 0.250 0.200 20 40 60 73.2 0 21.6 80 100 120 140 150 180 200 CALIBRATION TIME TO REACH ACCURACY (Seconds) Figure 39. Speed of Convergence for Autocalibration (Shunt Channel, Normal Mode) Based on Shunt Value 0.600 300 500 1000 2000 0.500 ACCURAC Y TARGET (%) The MS_CONFERR bit is set if a run of mSure is incorrectly set up with the MS_ACAL_CFG register. Clear these registers to 0 and check the settings being written before starting another run. 0.400 0 mSure System Warning Interrupts A set of interrupts in the ADE9153A are dedicated to alerting the user regarding any issues during an mSure autocalibration. These alerts are all indicated as a bit in the MS_STATUS_IRQ register, which is a Tier 2 status register as described in the Interrupts/Events section. 0.600 18.3 After the meter is powered, the autocalibration feature can be run on each channel, one at a time, by using the MS_ACAL_CFG register. Each channel has a set amount of run time. After each channel finishes a run, the certainty of the measurements are confirmed with the MS_ACAL_xCERT registers. Then, the MS_ACAL_xCC register can be used to calculate a gain value that calibrates the meter. 0.800 0.400 0.353 0.300 0.250 0.200 0.100 30 40 50 60 70 74.7 20 26.9 10 22.1 0 8 0 80 CALIBRATION TIME TO REACH ACCURACY (Seconds) 90 16519-240 ADE9153 A p0 mSure DISABLED 16519-038 LOW POWER MODE p0 + p1 The MS_ABSENT bit is set if the mSure signal is not detected. If this bit is triggered, wiring in the meter may be incorrect or broken. 16519-039 mSURE AUTOCALIBRATION FEATURE Figure 40. Speed of Convergence for Autocalibration (Shunt Channel, Turbo Mode) Based on Shunt Value Rev. 0 | Page 21 of 50 ADE9153A Data Sheet MEASUREMENTS 1501:1 1001:1 619:1 0.500 Current Channel The ADE9153A has two current channels. Channel A is optimized for use with a shunt, and Channel B is for use with a current transformer. The current channel datapaths for Channel A and Channel B are shown in Figure 42 and Figure 43, respectively. 0.400 0.353 0.300 0.250 Current Channel Gain, xIGAIN 0.200 The ADE9153A provides current gain calibration registers, AIGAIN and BIGAIN, with one register for each channel. 0.100 200 CALIBRATION TIME TO REACH ACCURACY (Seconds) The current channel gain varies with xIGAIN, as shown in the following equation: 16519-016 150 228.1 50 101.4 33.6 38.8 0 5.7 15.0 RELATIVE ACCURACY TARGET (%) 0.600 Current Channel Gain = 1 xIGAIN 27 2 Figure 41. Speed of Convergence for Autocalibration (Voltage Channel) Based on the Potential Divider Ratio VIN VIN +1/AI_PGAGAIN +1V ONE CYCLE RMS RMS_OC_SRC AI_WAV 0V ZERO-CROSSING DETECTION ZX_SRC_SEL -1V -1/AI_PGAGAIN ANALOG INPUT RANGE ANALOG INPUT RANGE CURRENT PEAK DETECTION REFERENCE 4kSPS IAP PGA VIN - MODULATOR LPF SINC4 HPFDIS AI GAIN 4:1 HPF TOTAL ACTIVE AND FUNDAMENTAL REACTIVE POWER CALCULATIONS PHASE COMP RMS AND VA CALCULATIONS IAN Figure 42. ADE9153A Current Channel A Datapath VIN +1.9V RMS_OC_SRC ONE CYCLE RMS BI_WAV 0.9V ZX_SRC_SEL -0.1V ZERO-CROSSING DETECTION ANALOG INPUT RANGE 4kSPS IBP - MODULATOR VIN SINC4 LPF BI GAIN 4:1 HPFDIS CURRENT PEAK DETECTION INTEN_BI PHASE COMP HPF RMS CALCULATIONS INTEGRATOR IBN Figure 43. ADE9153A Current Channel B Datapath VIN 1.3V RMS_OC_SRC ONE CYCLE RMS 0.3V ANALOG INPUT RANGE ZX_SRC_SEL REFERENCE 4kSPS VAP - MODULATOR VIN SINC4 LPF 4:1 AVGAIN PHASE COMP VAN Figure 44. ADE9153A Voltage Channel Datapath Rev. 0 | Page 22 of 50 ZERO-CROSSING DETECTION VOLTAGE PEAK DETECTION FUNDAMENTAL AND TOTAL ACTIVE AND REACTIVE POWER CALCULATIONS HPFDIS HPF AV_WAV FUNDAMENTAL AND TOTAL RMS, VA, THD CALCULATIONS 16519-019 0.8V 16519-018 REFERENCE 16519-017 0V Data Sheet ADE9153A High-Pass Filter A high-pass filter removes dc offsets for accurate rms and energy measurements. This filter is enabled by default and features a corner frequency of 1.25 Hz. To disable the high-pass filter on all current and voltage channels, set the HPFDIS bit in the CONFIG0 register. The corner frequency is configured with the HPF_CRN bits in the CONFIG2 register. Digital Integrator A digital integrator is included on Current Channel B for the possibility of interfacing with a di/dt current sensor, also known as Rogowski coils. It is important to take note that the integrator cannot be used with any of the mSure functions. To configure the digital integrator, use the INTEN_BI bits in the CONFIG0 register. The digital integrator is disabled by default. Calculate the VLEVEL value according to the following equation: VLEVEL = x x 1,444,084 where x is the dynamic range of the nominal voltage input signal with respect to full scale. For example, if the signal is at 1/2 of full scale, x = 2. Therefore, VLEVEL = 2 x 1,444,084 Total RMS The ADE9153A offers total current and voltage rms measurements on all channels. Figure 45 shows the datapath of the rms measurements. xRMS_OS Phase Compensation 15 x2 LPF2 xRMS +0.064% 52725703 -0.064% Use the following equation to calculate the xPHASECAL value for a given phase correction () angle. Phase correction () is positive to correct a current that lags the voltage, and negative to correct a current that leads the voltage, as seen in a current transformer. 16519-145 The ADE9153A provides a phase compensation register for each current channel: APHASECAL and BPHASECAL. The phase calibration range is -15 to +2.25 at 50 Hz and -15 to +2.7 at 60 Hz. AV_WAV OR xI_WAV VOLTAGE OR CURRENT CHANNELWAVEFORM 0 Figure 45. Filter-Based Total RMS Datapath sin( - ) sin 27 2 xPHASECAL = sin( 2 - ) = 2 x fLINE/fDSP where: fLINE is the line frequency. fDSP = 4 kHz. Voltage Channel The ADE9153A has a single voltage channel with the datapath shown in Figure 44. The AVGAIN register calibrates the voltage channel and has the same scaling as the xIGAIN registers. RMS and Power Measurements The ADE9153A calculates total values of rms current, rms voltage, active power, fundamental reactive power, and apparent power. The algorithm for computing the fundamental reactive power requires initialization of the network frequency using the SELFREQ bit in the ACCMODE register and the nominal voltage in the VLEVEL register. The total rms calculations, one for each channel (AIRMS, BIRMS, and AVRMS), are updated every 4 kSPS. The xIRMS value at full scale is 52,725,703 codes. The xVRMS value at full scale is 26,362,852 codes. The total rms measurements can be calibrated for gain and offset. Perform gain calibration on the respective Current A voltage channel datapath with the xGAIN registers. The following equation indicates how the offset calibration registers modify the result in the corresponding rms registers: xRMS = xRMS02 215 xRMOS _ OS where xRMS0 is the initial xRMS register value before offset calibration. Total Active Power The ADE9153A offers a total active power measurement. The datapath for the total active power measurement is shown in Figure 46. AI_WAV CONFIG0. DISAPLPF APGAIN AWATT_OS AWATT ENERGY/ POWER/ CF ACCUMULATION 16519-146 LPF2 AV_WAV Figure 46. Total Active Power (AWATT) Datapath Rev. 0 | Page 23 of 50 ADE9153A Data Sheet The total active power calculation, AWATT, is updated every 4 kSPS. With full-scale inputs, the AWATT value is 10,356,306 codes. The total apparent power calculation, AVA, is updated every 4 kSPS. With full-scale inputs, the AVA value is 10,356,306 codes. LPF2 is enabled by default (DISRPLPF = 0) and must be set to this default value for typical operation. Disable LPF2 by setting the DISRPLPF bit in the CONFIG0 register. The low-pass filter, LPF2, is enabled by default (DISAPLPF = 0) and must be set to this default value for typical operation. Disable LPF2 by setting the DISAPLPF bit in the CONFIG0 register. The following equation indicates how the gain and offset calibration registers modify the results in the power register: AWATT = 1 The ADE9153A offers a register, VNOM, to calculate the total apparent power when the voltage is missing. This register is set to correspond to a desired voltage rms value. If the VNOMA_ EN bit in the CONFIG0 register is set, the VNOM value is used instead of AVRMS. APGAIN AWATT0 + AWATT_OS 227 APGAIN is a common gain for all power measurements: active, reactive, and apparent power measurements. Energy Accumulation, Power Accumulation, and No Load Detection Features Fundamental Reactive Power The ADE9153A calculates total active, fundamental reactive, and total apparent energy. By default, the accumulation mode is signed accumulation but can be changed to absolute, positive only, or negative only for active and reactive energies using the WATTACC and VARACC bits in the ACCMODE register. The ADE9153A offers a fundamental reactive power measurement. Figure 47 shows the datapath for the fundamental reactive power calculation. APGAIN AFVAR_OS Energy Accumulation AFVAR FUNDAMENTAL VAR ENERGY/ POWER/CF ACCUMUL ATION The energy is accumulated into a 42-bit signed internal energy accumulator at 4 kSPS. The user readable energy register is signed and 45 bits wide, split between two 32-bit registers as shown in Figure 49. With full-scale inputs, the user energy register overflows in 106.3 sec. Figure 47. Fundamental Reactive Power (AFVAR) Datapath The fundamental reactive power calculation, AFVAR, is updated every 4 kSPS. With full-scale inputs, the AFVAR value is 10,356,306 codes. fDSP AWATT + LPF2 is enabled by default (DISRPLPF = 0) and must be set to this default value for typical operation. Disable LPF2 by setting the DISRPLPF bit in the CONFIG0 register. Energy Accumulation Modes The energy registers can accumulate a user defined number of samples or half line cycles configured by the EGY_TMR_ MODE bit in the EP_CFG register. Half line cycle accumulation uses the voltage channel zero crossings. The number of samples or half line cycles is set in the EGY_TIME register. The maximum value of EGY_TIME is 8191 decimal. With full-scale inputs, the internal register overflows in 13.3 sec. For a 50 Hz signal, EGY_ TIME must be lower than 1329 decimal to prevent overflow during half line cycle accumulation. 215 APGAIN AIRMS AVA AVRMS LPF2 VNOM 0 ENERGY/ POWER/ CF ACCUMULATION 1 215 AVRMS_OS 16519-148 x2 0 AWATTHR_LO AIRMS_OS AV_WAV 12 Figure 49. Internal Energy Accumulator to AWATTHR_HI and AWATTHR_LO APGAIN AFVAR0 + AFVAR_OS 227 LPF2 12 AWATTHR_HI 0 31 The ADE9153A offers a total apparent power measurement. The datapath for the total apparent power calculation is shown in Figure 48. x2 INTERNAL ENERGY ACCUMULATOR 31 Total Apparent Power AI_WAV 0 13 The following equation indicates how the gain and offset calibration registers modify the results in the power register: AFVAR = 1 41 + 16519-149 AV_WAV 16519-147 AI_WAV After EGY_TIME + 1 samples or half line cycles, the EGYRDY bit is set in the status register and the energy register is updated. The data from the internal energy register is added or latched to the user energy register, depending on the EGY_LD_ACCUM bit setting in the EP_CFG register. Figure 48. Total Apparent Power (AVA) Datapath Rev. 0 | Page 24 of 50 Data Sheet ADE9153A power changes, the corresponding REVx bits in the status register are set and IRQ generates an interrupt. Reset Energy Register on Read The user can reset the energy register on a read using the RD_RST_EN bit in the EP_CFG register. In this way, the value in the user energy register is reset when it is read. The ADE9153A allows the user to accumulate total active power and fundamental reactive power into separate positive and negative accumulation registers: PWATT_ACC, NWATT_ ACC, PFVAR_ACC, and NFVAR_ACC. A new accumulation from zero begins when the power update interval set in PWR_TIME elapses. Power Accumulation The ADE9153A accumulates the total active, fundamental reactive, and total apparent powers into the AWATT_ACC, AFVAR_ACC, and AVA_ACC 32-bit signed registers, respectively. This accumulation can be used as an averaged power reading. No Load Detection Feature The ADE9153A features no load detection for each energy to prevent energy accumulation due to noise. If the accumulated energy over the user defined time period is below the user defined threshold, zero energy is accumulated into the energy register. The NOLOAD_TMR bits in the EP_CFG register determine the no load time period, and the ACT_NL_LVL, REACT_NL_LVL, and APP_NL_LVL registers contain the user defined no load threshold. The no load status is available in the PHNOLOAD register and the status register, which can be driven to the IRQ interrupt pin. The number of samples accumulated is set using the PWR_ TIME register. The PWRRDY bit in the status register is set after PWR_TIME + 1 samples accumulate at 4 kSPS. The maximum value of the PWR_TIME register is 8191 decimal, and the maximum power accumulation time is 1.024 sec. The CFxSIGN, AVARSIGN, and AWSIGN bits in the PHSIGN register indicate the sign of accumulated powers over the PWR_TIME interval. When the sign of the accumulated 4.096MHz 000 AVA 010 AFVAR 512 100 DIGITAL TO FREQUENCY CFxDIS CFx BITS 0 1 CFxSEL 1 CFxDEN WTHR CFx_LT PULSE WIDTH CONFIGURATION CFx PIN CF_LTMR 000 CF_ACC_CLR VATHR 010 VARTHR 100 CFxSEL ADE9153A Figure 50. Digital to Frequency Conversion for CFx Rev. 0 | Page 25 of 50 16258-150 AWATT ADE9153A Data Sheet Digital to Frequency Conversion--CFx Output POWER QUALITY MEASUREMENTS The ADE9153A includes two pulse outputs on the CF1 and CF2 output pins that are proportional to the energy accumulation. The block diagram of the CFx pulse generation is shown in Figure 50. CF2 is multiplexed with ZX and DREADY. Zero-Crossing Detection Calibration Frequency (CF) Energy Selection The ADE9153A offers zero-crossing detection on the voltage and both current channels. The current and voltage channel datapaths preceding the zero-crossing detection are shown in Figure 51 and Figure 52. The CFxSEL bits in the CFMODE register select which type of energy to output on the CFx pins. For example, with CF1SEL = 000b and CF2SEL = 100b, CF1 indicates the total active energy, and CF2 indicates the fundamental reactive energy. Use the ZX_SRC_SEL bit in the CONFIG0 register to select data before the high-pass filter or after phase compensation to configure the inputs to zero-crossing detection. ZX_SRC_SEL = 0 by default after reset. Configuring the CFx Pulse Width To provide protection from noise, voltage channel zero-crossing events (ZXAV) do not generate if the absolute value of the LPF1 output voltage is smaller than the threshold, ZXTHRSH. The current channel zero-crossing detection outputs, ZXAI and ZXBI, are active for all input signals levels. The values of the CFx_LT and the CF_LTMR bits in the CF_LCFG register determine the pulse width. The maximum CFx with threshold (xTHR) = 0x00100000 and CFxDEN = 2 is 78.9 kHz. It is recommended to leave xTHR at the default value of 0x00100000. Calculate the zero-crossing threshold, ZXTHRSH, from the following equation: CFx Pulse Sign ZXTHRSH = The CFxSIGN bits in the PHSIGN register indicate whether the energy in the most recent CFx pulse is positive or negative. The REVPCFx bits in the status register indicate if the CFx polarity changed sign. This feature generates an interrupt on the IRQ pin. (V _ WAV at Full Scale ) (LPF1 Attenuatio n) x 32 2 8 where V_WAV at Full Scale is 37,282,702 decimal. LPF1 Attenuation is 0.86 at 50 Hz, and 0.81 at 60 Hz. x is the dynamic range below which the voltage channel zero crossing must be blocked. Clearing the CFx Accumulator To clear the accumulation in the digital to frequency converter and CFDEN counter, write 1 to the CF_ACC_CLR bit in the CONFIG1 register. The CF_ACC_CLR bit automatically clears itself. ZX_SRC_SEL HPFDIS AVGAIN /32 PHASE COMP HPF ZERO-CROSSING DETECTION 16258-151 LPF1 AV_WAV Figure 51. Voltage Channel Signal Path Preceding Zero-Crossing Detection ZX_SRC_SEL HPFDIS INTEN_BI ZX DETECTION /32 LPF1 PHASE COMP HPF xI_WAV INTEGRATOR Figure 52. Current Channel Signal Path Preceding Zero-Crossing Detection Rev. 0 | Page 26 of 50 16258-152 xIGAIN Data Sheet ADE9153A The zero-crossing detection circuits have two different output rates: 4 kSPS and 512 kSPS. The 4 kSPS zero-crossing signal calculates the line period, updates the ZXx bits in the status register, and monitors the zero-crossing timeout and energy accumulation functions. The 512 kSPS zero-crossing signal calculates the angle and updates the zero-crossing output on the CF2/ZX/ DREADY pin. CF1/ZX/DREADY The CF1/ZX/DREADY pin can output zero crossings using the ZX_OUT_OE bit in the CONFIG1 register. The CF1/ZX/ DREADY output pin goes from low to high when a negative to positive transition is detected and from high to low when a positive to negative transition occurs. Zero-Crossing Timeout If a zero crossing is not received after (ZXTOUT + 1)/4000 sec, the ZXTOAV bit in the status register is set and generates an interrupt on the IRQ pin. Line Period Calculation The ADE9153A calculates the line period on the voltage with the result available in the APERIOD register. Calculate the line period, tL, from the APERIOD register according to the following equation: tL = APERIOD 1 4000 216 (sec) If the calculated period value is outside the range of 40 Hz to 70 Hz, or if zero crossings are not detected, the APERIOD register is coerced to correspond to 50 Hz or 60 Hz, depending on the SELFREQ bit in the ACCMODE register. Angle Measurement The ADE9153A provides two angle measurements: ANGL_AV_AI for the angle between current Channel A and the voltage channel, and ANGL_AI_BI for the angle between Current Channel A and Current Channel B. To convert angle register readings to degrees, use the following equations. One Cycle RMS Measurement RMS1/2 is an rms measurement performed over one line cycle, updated every half cycle. This measurement is provided on all three channels for voltage and current. All the half cycle rms measurements are performed over the same time interval and update at the same time, as indicated by the RMS_OC_RDY bit in the status register. The results are stored in the AIRMS_OC, AVRMS_OC, and BIRMS_OC registers. The xIRMS_OC and AVRMS_OC register reading with full-scale inputs is 52,725,703 codes and 26,362,852, respectively. It is recommended to select the data before the high-pass filter for the fast rms measurement by setting the RMS_OC_SRC bit in the CONFIG0 register. The voltage channel is used for the timing of the rms1/2 measurement. Alternatively, set the UPERIOD_SEL bit in the CONFIG2 register to set desired period in the USER_PERIOD register for line period measurement. An offset correction register, xRMS_OC_OS, is available for improved performance with small input signal levels. The datapath is shown in Figure 53. Dip and Swell Indication The ADE9153A monitors the rms1/2 value on the voltage channel to determine a dip and swell event. If the voltage goes below a threshold specified in the DIP_LVL register for a user configured number of half cycles in the DIP_CYC register, the DIPA bit is set in the EVENT_STATUS register. The minimum rms1/2 value measured during the dip is stored in the DIPA register. Similarly, if the voltage goes above a threshold specified in the SWELL_LVL register for a user configured number of half cycles in the SWELL_CYC register, the SWELLA bit is set in the EVENT_STATUS register. The maximum rms1/2 value measured during the swell is stored in the SWELLA register. The dip and swell event generates an interrupt on the IRQ pin. For a 50 Hz system, Angle (Degrees) = ANGL_x_y x 0.017578125 For a 60 Hz system, Angle (Degrees) = ANGL_x_y x 0.02109375 INTEN_BI PHASE COMP HPF INTEGRATOR (ON BI ONLY) xI_WAV RMS_OC_SEL xIRMSONE xIRMSONEOS FAST RMS1/2 APERIOD USER_PERIOD UPERIOD_SEL Figure 53. RMS1/2, RMS Measurements Rev. 0 | Page 27 of 50 16258-153 HPFDIS CURRENT CHANNEL SAMPLES ADE9153A Data Sheet The ADE9153A monitors the rms1/2 value on current channels to determine overcurrent events. If an rms1/2 current is greater than the user configured threshold in the OI_LVL register, the OIx bit in the EVENT_STATUS register is set. The overcurrent event generates an interrupt on the IRQ pin. The OIx_EN bits in the CONFIG3 register select the current channel to monitor for overcurrent events. The OIx bits in the EVENT_STATUS register indicate which current channel exceeded the threshold. The overcurrent value is stored in the OIA and OIB registers. Peak Detection The ADE9153A records the peak value measured on all three channels from the AI_WAV, AV_WAV, and BI_WAV waveforms. The PEAK_SEL bits in the CONFIG3 register allow the user to select which channel to monitor. determine the power factor from the APF register value, use the following equation: Power Factor = APF x 2-27 VAR 270 LAGGING WATT (-) VAR (-) QUADRANT III WATT (+) VAR (-) QUADRANT IV INDUCTIVE: CURRENT LAGS VOLTAGE CAPACITIVE: CURRENT LEADS VOLTAGE 1 = -30 PF1 = 0.866 CAP V 2 = 60 PF2 = 0.5 IND CAPACITIVE: CURRENT LEADS VOLTAGE INDUCTIVE: CURRENT LAGS VOLTAGE I WATT (-) VAR (+) QUADRANT II WATT WATT (+) VAR (+) QUADRANT I 90 LAGGING WATT(+) INDICATES POWER RECEIVED (IMPORTED FROM GRID) WATT(-) INDICATES POWER DELIVERED (EXPORTEDTO GRID) 16258-154 Overcurrent Indication The IPEAK register stores the peak current value in the IPEAKVAL bits and indicates which phase currents reached the value in the IPPHASE bits. IPEAKVAL is equal to xI_WAV/25. Temperature Similarly, VPEAK stores the peak voltage value in the VPEAKVAL bits. VPEAKVAL is equal to AV_WAV/25. After a read, the VPEAK and IPEAK registers reset. The temperature reading is available in the TEMP_RSLT register. To convert the temperature range into Celsius, use the following equation: Figure 54. WATT and VAR Power Sign for Capacitive and Inductive Loads Power Factor The power factor calculation, APF, is updated every 1.024 sec. The sign of the APF calculation follows the sign of AWATT. To determine if power factor is leading or lagging, refer to the sign of the total or fundamental reactive energy and the sign of the APF or AWATT value, as shown in Figure 54. Temperature (C) = TEMP_RSLT x (-TEMP_GAIN/217) + (TEMP_OFFSET/25) During the manufacturing of each device, the TEMP_GAIN and TEMP_OFFSET bits of Register TEMP_TRIM are programed. To configure the temperature sensor, program the TEMP_CFG register. The power factor result is stored in 5.27 format. The highest power factor value is 0x07FF FFFF, which corresponds to a power factor of 1. A power factor of -1 is stored as 0xF800 0000. To Rev. 0 | Page 28 of 50 Data Sheet ADE9153A APPLICATIONS INFORMATION INTERRUPTS/EVENTS For the Tier 1 status register bits, Bits[25:0], The ADE9153A has two pins, IRQ and ZX/DREADY/CF2, that can be used as interrupts to the host processor. 1. 2. IRQ PIN INTERRUPTS For the Tier 2 status register bits, Bits[31:29], The IRQ pin goes low when an enabled interrupts occurs and stays low until the event is acknowledged by setting the corresponding status bit in the status register. The bits in the mask register configure the respective interrupts. 1. 2. SERVICING INTERRUPTS The CF2 pin is multiplexed with the ZX and DREADY functions that track the state of zero crossings and when new data is available, respectively. The ZX pin functionality goes high with negative to positive zero crossings and goes low with positive negative zero crossings. The DREADY pin functionality outputs a 1 ms pulse when new data is ready. Interrupts in the ADE9153A are in a tiered system where it never takes more than two communications to clear an interrupt. The status register is a Tier 1 interrupt register and CHIP_STATUS, EVENT_STATUS, and MS_STATUS_IRQ are Tier 2 interrupt registers, which correspond to the status bits, CHIP_STAT, EVENT_STAT, and MS_STAT. Read the status register to see which bit is set. Write a 1 to the status bits that must be cleared. Read the status register to see which Tier 2 register is set. Read the Tier 2 register (CHIP_STATUS, EVENT_STATUS, or MS_STATUS_IRQ); the register is cleared on a read. CF2/ZX/DREADY EVENT PIN Rev. 0 | Page 29 of 50 ADE9153A Data Sheet ACCESSING ON-CHIP DATA The UART communication is comprised of 11-bit frames with one start bit, eight data bits, one odd parity bit, and one stop bit. 10 9 SPI PROTOCOL OVERVIEW The ADE9153A has an SPI-compatible interface consisting of four pins: SCLK, MOSI/RX, MISO/TX, and SS. The ADE9153A is always an SPI slave; it never initiates a SPI communication. The SPI interface is compatible with 16-bit and 32-bit read/write operations. The maximum serial clock frequency supported by this interface is 10 MHz. Figure 56. Frame Bits Every UART communication starts with two command frames that contain the ADE9153A address being accessed, a read or write bit, a bit indicating whether to include the checksum, and then 00b as the lower two bits (see Figure 57). 15 4 3 R/W CHIP ADDRESS 2 1 0 00B CHECKSUM WRITE = 0 READ = 1 OFF = 0 ON = 1 Figure 57. Command Header (CMD) Figure 55. Command Header, CMD_HDR The frames are then organized with the two command header frames, followed by the data frames, and finally an optional checksum that is enabled in the command frames. 0 The ADE9153A SPI port calculates a 16-bit cyclic redundancy check (CRC-16) of the data sent out on the MOSI/RX pin so that the integrity of the data received by the master can be checked. The CRC of the data sent out on the MOSI/RX pin during the last register read is offered in a 16-bit register, CRC_SPI, and can be appended to the SPI read data as part of the SPI transaction. 1 CMD0 RX 2 CMD1 4 DATA1 CHECKSUM OPTIONAL Figure 58. UART 16-Bit Write 0 RX 1 CMD0 2 3 4 CMD1 DATA0 TX DATA1 CHECKSUM OPTIONAL UART INTERFACE Figure 59. UART 16-Bit Read The ADE9153A has a UART interface consisting of two pins: RX and TX. This UART interface allows an isolated communication interface to be achieved using only two low cost opto-isolators. The UART interface is compatible with 16-bit and 32-bit read/write operations. When the UART is selected, the Baud rate is 4800 Baud; however, a faster communication rate of 115,200 Baud can also be selected. The ADE9153A Baud rates are shown in Table 7. 0 RX 1 CMD0 2 CMD1 3 DATA0 DATA1 4 DATA2 5 DATA3 6 CHECKSUM OPTIONAL Figure 60. UART 32-Bit Write Table 7. UART Baud Rate ADE9153A Actual Rate (Baud) (CLKIN = 12.288 MHz) CLKIN/2560 = 4800 CLKIN/104 = 118153.8 3 DATA0 16258-162 0 xxx 16258-163 R/W READ = 1 WRITE = 0 Ideal Rate (Baud) 4800 115,200 STOP Error 0.00% 2.56% Rev. 0 | Page 30 of 50 16258-164 3 2 ADDR[11:0] 0 ODD PARITY DON'T CARE BITS 16258-159 15 1 DATA [7:0] The ADE9153A provides SPI burst read functionality on certain registers, allowing multiple register to be read after sending one command header, CMD_HDR. ADDRESS TO BE ACCESSED 2 START 16258-160 After power-on or reset, to select the SPI interface, the SS pin must be low and the SCLK pin must be high. To select the UART interface, the SS pin must be high and the SCLK pin must be low. When the ADE9153A is powered, the communication is set, and it is locked in until the next ADE9153A reset. If the UART is to be used at 4800 Baud, no action is required when the UART interface is chosen after a reset. The 115,200 Baud rate is chosen with a single write of 0x0052 to the UART_BAUD_ SWITCH register. The Baud rate can be switched back to 4800 Baud by writing 0x000 to the UART_BAUD_SWITCH register. UART_BAUD_SWITCH is a write only register. 16258-161 The ADE9153A has two communication protocols for accessing on-chip data, a fast 10 MHz SPI and a slower 4800 Baud/ 115,200 Baud universal asynchronous receiver/transmitter (UART). Data Sheet ADE9153A COMMUNICATION VERIFICATION REGISTERS CONFIGURATION LOCK The ADE9153A includes three register that allow SPI operation verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16 (Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers record the received CMD_HDR and the last read or transmitted data. The configuration lock feature prevents changes to the ADE9153A configuration. To enable this feature, write 0x3C64 to the WR_LOCK register. To disable the feature, write 0x4AD1. CRC OF CONFIGURATION REGISTERS The configuration register CRC feature in the ADE9153A monitors certain user and private register values. The results are stored in the CRC_RSLT register. When enabled, the ADE9153A generates an interrupt on IRQ if any of the monitored registers change the value of the CRC_RSLT register. To determine whether this feature is active, read the WR_LOCK register, which reads as 1 if the protection is enabled and 0 if it is disabled. When this feature is enabled, it prevents writing to addresses from Address 0x000 to Address 0x073 and Address 0x400 to Address 0x4FE. Rev. 0 | Page 31 of 50 ADE9153A Data Sheet REGISTER INFORMATION REGISTER SUMMARY Table 8. Register Summary Address 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 Name AIGAIN APHASECAL AVGAIN AIRMS_OS AVRMS_OS APGAIN AWATT_OS AFVAR_OS 0x008 0x009 0x010 0x011 0x013 0x019 0x020 0x021 AVRMS_OC_OS AIRMS_OC_OS BIGAIN BPHASECAL BIRMS_OS BIRMS_OC_OS CONFIG0 VNOM 0x022 DICOEFF 0x023 0x030 0x045 BI_PGAGAIN MS_ACAL_CFG MS_AICC_USER 0x046 MS_BICC_USER 0x047 MS_AVCC_USER 0x049 CT_PHASE_DELAY 0x04A CT_CORNER 0x04C VDIV_RSMALL 0x200 AI_WAV 0x201 AV_WAV 0x202 0x203 0x204 0x206 0x207 0x208 0x209 AIRMS AVRMS AWATT AVA AFVAR APF AIRMS_OC 0x20A AVRMS_OC Description Phase A current gain adjust. Phase A phase correction factor. Phase A voltage gain adjust. Phase A current rms offset for filter-based AIRMS calculation. Phase A voltage rms offset for filter-based AVRMS calculation. Phase A power gain adjust for AWATT, AVA, and AFVAR calculations. Phase A total active power offset correction for AWATT calculation. Phase A fundamental reactive power offset correction for AFVAR calculation. Phase A voltage rms offset for fast rms, AVRMS_OC calculation. Phase A current rms offset for fast rms, AIRMS_OC calculation. Phase B current gain adjust. Phase B correction factor. Phase B current rms offset for filter-based BIRMS calculation. Phase B current rms offset for fast rms, BIRMS_OC calculation. DSP configuration register. Nominal phase voltage rms used in the calculation of apparent power, AVA, when the VNOMA_EN bit is set in the CONFIG0 register. Value used in the digital integrator algorithm. If the integrator is turned on, with INTEN_BI equal to 1 in the CONFIG0 register, it is recommended to leave this register at the default value. PGA gain for Current Channel B ADC. mSure autocalibration configuration register. User input Current Channel A CC value for mSure initialization and threshold calculation. User input Current Channel B CC value for mSure initialization and threshold calculation. User input Voltage Channel CC value for mSure initialization and threshold calculation. Phase delay of the CT used on Current Channel B. This register is in 5.27 format and expressed in degrees. Corner frequency of the CT. This value is calculated from the CT_PHASE_DELAY value. This register holds the resistance value, in , of the small resistor in the resistor divider. Instantaneous Current Channel A waveform processed by the DSP at 4 kSPS. Instantaneous voltage channel waveform processed by the DSP at 4 kSPS. Phase A filter-based current rms value updated at 4 kSPS. Phase A filter-based voltage rms value updated at 4 kSPS. Phase A low-pass filtered total active power updated at 4 kSPS. Phase A total apparent power updated at 4 kSPS. Phase A fundamental reactive power updated at 4 kSPS. Phase A power factor updated at 1.024 sec. Phase A current fast rms calculation; one cycle rms updated every half cycle. Phase A voltage fast rms calculation; one cycle rms updated every half cycle. Rev. 0 | Page 32 of 50 Length (Bits) 32 32 32 32 32 32 32 32 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W 32 32 32 32 32 32 32 32 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R/W R/W R/W R/W R/W R/W R/W R/W 32 0x00000000 R/W 32 32 32 0x00000000 0x00000000 0x00000000 R/W R/W R/W 32 0x00000000 R/W 32 0x00000000 R/W 32 0x00000000 R/W 32 0x00000000 R/W 32 0x00000000 R/W 32 0x00000000 R 32 0x00000000 R 32 32 32 32 32 32 32 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R 32 0x00000000 R Data Sheet Address 0x210 Name BI_WAV 0x212 0x219 BIRMS BIRMS_OC 0x220 0x221 0x222 0x223 0x224 0x225 0x240 MS_ACAL_AICC MS_ACAL_AICERT MS_ACAL_BICC MS_ACAL_BICERT MS_ACAL_AVCC MS_ACAL_AVCERT MS_STATUS_CURRENT 0x241 VERSION_DSP 0x242 0x39D VERSION_PRODUCT AWATT_ACC 0x39E AWATTHR_LO 0x39F AWATTHR_HI 0x3B1 AVA_ACC 0x3B2 AVAHR_LO 0x3B3 AVAHR_HI 0x3BB AFVAR_ACC 0x3BC AFVARHR_LO 0x3BD AFVARHR_HI 0x3EB PWATT_ACC 0x3EF NWATT_ACC 0x3F3 PFVAR_ACC 0x3F7 NFVAR_ACC 0x400 0x401 0x402 0x405 0x409 0x40A IPEAK VPEAK Status Mask OI_LVL OIA 0x40B 0x40E OIB USER_PERIOD ADE9153A Description Instantaneous Phase B Current Channel waveform processed by the DSP at 4 kSPS. Phase B filter-based current rms value updated at 4 kSPS. Phase B Current fast rms calculation; one cycle rms updated every half cycle. Current Channel A mSure CC estimation from autocalibration. Current Channel A mSure certainty of autocalibration. Current Channel B mSure CC estimation from autocalibration. Current Channel B mSure certainty of autocalibration. Voltage channel mSure CC estimation from autocalibration. Voltage channel mSure certainty of autocalibration. The MS_STATUS_CURRENT register contains bits that reflect the present state of the mSure system. This register indicates the version of the ADE9153B DSP after the user writes run = 1 to start measurements. This register indicates the version of the product being used. Phase A accumulated total active power, updated after PWR_TIME 4 kSPS samples. Phase A accumulated total active energy, least significant bits (LSBs). Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total active energy, most significant bits (MSBs). Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total apparent power, updated after PWR_TIME 4 kSPS samples. Phase A accumulated total apparent energy, LSBs. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated total apparent energy, MSBs. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental reactive power. Updated after PWR_TIME 4 kSPS samples. Phase A accumulated fundamental reactive energy, LSBs. Updated according to the settings in the EP_CFG and EGY_TIME registers. Phase A accumulated fundamental reactive energy, MSBs. Updated according to the settings in the EP_CFG and EGY_TIME registers. Accumulated positive total active power from the AWATT register; updated after PWR_TIME 4 kSPS samples. Accumulated negative total active power from the AWATT register; updated after PWR_TIME 4 kSPS samples. Accumulated positive fundamental reactive power from the AFVAR register, updated after PWR_TIME 4 kSPS samples. Accumulated negative fundamental reactive power from the AFVAR register, updated after PWR_TIME 4 kSPS samples. Current peak register. Voltage peak register. Tier 1 interrupt status register. Tier 1 interrupt enable register. Overcurrent RMS_OC detection threshold level. Phase A overcurrent RMS_OC value. If overcurrent detection on this channel is enabled with OIA_EN in the CONFIG3 register and AIRMS_OC is greater than the OILVL threshold, this value is updated. Phase B overcurrent RMS_OC value. See the OIA description. User configured line period value used for RMS_OC when the UPERIOD_SEL bit in the CONFIG2 register is set. Rev. 0 | Page 33 of 50 Length (Bits) 32 Reset 0x00000000 Access R 32 32 0x00000000 0x00000000 R R 32 32 32 32 32 32 32 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R 32 0x00000000 R 32 32 0x0009153A 0x00000000 R R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 0x00000000 R 32 32 32 32 32 32 0x00000000 0x00000000 0x00000000 0x00000000 0x00FFFFFF 0x00000000 R R R/W R/W R/W R 32 32 0x00000000 0x00500000 R R/W ADE9153A Address 0x40F Name VLEVEL 0x410 0x411 0x414 0x415 0x418 0x41C 0x41D 0x41E 0x41F 0x420 DIP_LVL DIPA SWELL_LVL SWELLA APERIOD ACT_NL_LVL REACT_NL_LVL APP_NL_LVL PHNOLOAD WTHR 0x421 0x422 VARTHR VATHR 0x423 LAST_DATA_32 0x424 CT_PHASE_MEAS 0x425 0x471 CF_LCFG TEMP_TRIM 0x472 0x473 0x480 0x481 0x485 CHIP_ID_HI CHIP_ID_LO Run CONFIG1 ANGL_AV_AI 0x488 ANGL_AI_BI 0x48B 0x48C 0x490 0x491 0x492 0x493 0x494 0x495 0x498 0x499 0x49A 0x49D 0x4A8 0x4A9 DIP_CYC SWELL_CYC CFMODE COMPMODE ACCMODE CONFIG3 CF1DEN CF2DEN ZXTOUT ZXTHRSH ZX_CFG PHSIGN CRC_RSLT CRC_SPI 0x4AC LAST_DATA_16 0x4AE LAST_CMD 0x4AF CONFIG2 Data Sheet Description Register used in the algorithm that computes the fundamental reactive power. Voltage RMS_OC dip detection threshold level. Phase A voltage RMS_OC value during a dip condition. Voltage RMS_OC swell detection threshold level. Phase A voltage RMS_OC value during a swell condition. Line period on the Phase A voltage. No load threshold in the total active power datapath. No load threshold in the fundamental reactive power datapath. No load threshold in the total apparent power datapath. Phase no load register. Sets the maximum output rate from the digital to frequency converter of the total active power for the CF calibration pulse output. It is recommended to leave this at WTHR = 0x00100000. See WTHR. It is recommended to leave this at VARTHR = 0x00100000. See WTHR. It is recommended to leave this value at VATHR = 0x00100000. This register holds the data read or written during the last 32-bit transaction on the SPI port. Set to 0xE5 for CT_PHASE_DELAY measurement; otherwise, the value must be 0xE4. CF calibration pulse width configuration register. Temperature sensor gain and offset, calculated during the manufacturing process. Chip identification, 32 MSBs. Chip identification, 32 LSBs. Write this register to 1 to start the measurements. Configuration Register 1. Time between positive to negative zero crossings on Phase A voltage and current. Time between positive to negative zero crossings on Phase A and Phase B currents. Voltage RMS_OC dip detection cycle configuration. Voltage RMS_OC swell detection cycle configuration. CFx configuration register. Computation mode register. Set this register to 0x0005. Accumulation mode register. Configuration Register 3 for configuration of power quality settings. CF1 denominator register. CF2 denominator register. Zero-crossing timeout configuration register. Voltage channel zero-crossing threshold register. Zero-crossing detection configuration register. Power sign register. This register holds the CRC of the configuration registers. The register holds the 16-bit CRC of the data sent out on the MOSI/RX pin during the last SPI register read. This register holds the data read or written during the last 16-bit transaction on the SPI port. When using UART, this register holds the lower 16 bits of the last data read or write. This register holds the address and the read/write operation request (CMD_HDR) for the last transaction on the SPI port. Configuration Register 2. This register controls the high-pass filter (HPF) corner and the user period selection. Rev. 0 | Page 34 of 50 Length (Bits) 32 Reset 0x0045D450 Access R/W 32 32 32 32 32 32 32 32 32 32 0x00000000 0x007FFFFF 0x00FFFFFF 0x00000000 0x00500000 0x00008225 0x00008225 0x00008225 0x00000000 0x00100000 R/W R R/W R R R/W R/W R/W R R/W 32 32 0x00100000 0x00100000 R/W R/W 32 0x00000000 R 32 0x000000E4 R/W 32 32 0x00000000 0x00000000 R/W R 32 32 16 16 16 0x00000000 0x00000000 0x0000 0x0300 0x0000 R R R/W R/W R 16 0x0000 R 16 16 16 16 16 16 16 16 16 16 16 16 16 16 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0x0009 0x0000 0x0000 0x0000 0x0000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R 16 0x0000 R 16 0x0000 R 16 0x0C00 R/W Data Sheet Address 0x4B0 0x4B1 0x4B2 0x4B4 0x4B6 0x4B7 0x4B9 0x4BF 0x4C0 Name EP_CFG PWR_TIME EGY_TIME CRC_FORCE TEMP_CFG TEMP_RSLT AI_PGAGAIN WR_LOCK MS_STATUS_IRQ 0x4C1 EVENT_STATUS 0x4C2 CHIP_STATUS 0x4DC UART_BAUD_SWITCH 0x4FE 0x600 0x601 Version AI_WAV_1 AV_WAV_1 0x602 0x604 0x605 0x606 0x608 0x60A 0x60C 0x60E 0x610 0x611 0x612 0x613 0x614 0x615 0x616 0x617 0x618 0x61A BI_WAV_1 AIRMS_1 BIRMS_1 AVRMS_1 AWATT_1 AFVAR_1 AVA_1 APF_1 AI_WAV_2 AV_WAV_2 AIRMS_2 AVRMS_2 AWATT_2 AVA_2 AFVAR_2 APF_2 BI_WAV_2 BIRMS_2 ADE9153A Description Energy and power accumulation configuration. Power update time configuration. Energy accumulation update time configuration. This register forces an update of the CRC of configuration registers. Temperature sensor configuration register. Temperature measurement result. This register configures the PGA gain for Current Channel A. This register enables the configuration lock feature. The Tier 2 status register for the autocalibration mSure system related interrupts. Any bit set in this register causes the corresponding bit in the status register to be set. This register is cleared on a read and all bits are reset. If a new status bit arrives on the same clock on which the read occurs, the new status bit remains set; in this way, no status bit is missed. Tier 2 status register for power quality event related interrupts. See the MS_STATUS_IRQ description. Tier 2 status register for chip error related interrupts. See the MS_STATUS_IRQ description. This register switches the UART Baud rate between 4800 Baud and 115,200 Baud. Writing a value of 0x0052 sets the Baud rate to 115,200 Baud; any other value maintains a Baud rate of 4800. Version of the ADE9153B IC. SPI burst read accessible registers organized functionally. See AI_WAV. SPI burst read accessible registers organized functionally. See AV_WAV. SPI burst read accessible registers organized functionally. See BI_WAV. SPI burst read accessible registers organized functionally. See AIRMS. SPI burst read accessible registers organized functionally. See BIRMS. SPI burst read accessible registers organized functionally. See AVRMS. SPI burst read accessible registers organized functionally. See AWATT. SPI burst read accessible registers organized functionally. See AFVAR. SPI burst read accessible registers organized functionally. See AVA. SPI burst read accessible registers organized functionally. See APF. SPI burst read accessible registers organized by phase. See AI_WAV. SPI burst read accessible registers organized by phase. See AV_WAV. SPI burst read accessible registers organized by phase. See AIRMS. SPI burst read accessible registers organized by phase. See AVRMS. SPI burst read accessible registers organized by phase. See AWATT. SPI burst read accessible registers organized by phase. See AVA. SPI burst read accessible registers organized by phase. See AFVAR. SPI burst read accessible registers organized by phase. See APF. SPI burst read accessible registers organized by phase. See BI_WAV. SPI burst read accessible registers organized by phase. See BIRMS. Rev. 0 | Page 35 of 50 Length (Bits) 16 16 16 16 16 16 16 16 16 Reset 0x0000 0x00FF 0x00FF 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W W R/W R R/W R/W R 16 0x0000 R 16 0x0000 R 16 0x0000 W 16 32 32 0x0000 0x00000000 0x00000000 R R R 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 R R R R R R R R R R R R R R R R R R ADE9153A Data Sheet REGISTER DETAILS Table 9. Register Details Addr. 0x020 Name CONFIG0 Bits [31:10] 9 8 Bit Name Reserved Reserved DISRPLPF 7 DISAPLPF 6 5 Reserved VNOMA_EN 4 RMS_OC_SRC Settings 0 1 3 ZX_SRC_SEL 0 1 0x023 BI_PGAGAIN 2 INTEN_BI 1 0 RESERVED HPFDIS [31:0] BI_GAIN 0 1 10 Rev. 0 | Page 36 of 50 Description Reserved. Reserved. Set this bit to disable the low-pass filter in the fundamental reactive power datapath. Set this bit to disable the low-pass filter in the total active power datapath. Reserved. Set this bit to use the nominal phase voltage rms, VNOM, in the computation of the Phase A total apparent power, AVA. This bit selects the samples used for the RMS_OC calculation. x_WAV waveforms after the high-pass filter and phase compensation. ADC samples, before the high-pass filter. This bit selects whether data going into the zero-crossing detection circuit comes before the high-pass filter and phase compensation, or afterwards. After the high-pass filter and phase compensation. Before the high-pass filter and phase compensation. Set this bit to enable the integrator on Current Channel B. Reserved. Set this bit to disable highpass filters in all current and voltage channels. PGA gain for Current Channel B. Gain = 1. Gain = 2. Gain = 4. Reset 0x0 Access R 0x0 R/W 0x0 R/W 0x0 0x0 R R 0x0 R 0x0 R 0x0 R/W 0x0 0x0 R/W R 0x0 R/W Data Sheet Addr. 0x030 Name MS_ACAL_CFG ADE9153A Bits [31:7] 6 Bit Name Reserved AUTOCAL_AV 5 AUTOCAL_BI 4 AUTOCAL_AI 3 ACALMODE_BI Settings 0 1 2 ACALMODE_AI 0 1 1 ACAL_RUN 0 ACAL_MODE 0x240 MS_STATUS_CURRENT [31:1] 0 Reserved MS_SYSRDYP 0x400 IPEAK [31:27] [26:24] Reserved IPPHASE [23:0] IPEAKVAL [31:24] [23:0] Reserved VPEAKVAL 0x401 VPEAK Rev. 0 | Page 37 of 50 Description Reserved. Enable autocalibration on the voltage channel. Enable autocalibration on Current Channel B. Enable autocalibration on Current Channel A. Current Channel B autocalibration power mode. Normal mode. Turbo mode. Current Channel A autocalibration power mode. Normal mode. Turbo mode. Runs autocalibration as configured in Bits[6:2]. The ACAL_MODE bit must also be set while running autocalibration. This bit must be set when running auto-calibration; otherwise, autocalibration does not run. All registers, except for the autocalibration result registers, are disabled when this bit is set. Reserved. When this bit is set, the mSure system is ready for a run of autocalibration. Reserved. These bits indicate which current channels generate the IPEAKVAL value. Note that the PEAKSEL[1:0] bits in the CONFIG3 register determine on which current channel to monitor the peak value. When IPPHASE, Bit 0 is set to 1, Current Channel A generates the IPEAKVAL (Bits[23:0]) value. Similarly, IPPHASE (Bit 1) indicates that Current Channel B generates the peak value. The IPEAK register stores the absolute value of the peak current. IPEAK is equal to xI_WAV/25. Reserved. The VPEAK register stores the absolute value of the peak voltage. VPEAK is equal to AV_WAV/25. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R 0x0 0x0 R R 0x0 R 0x0 0x0 R R ADE9153A Addr. 0x402 Name Status Data Sheet Bits 31 Bit Name CHIP_STAT 30 EVENT_STAT 29 MS_STAT [28:26] 25 Reserved PF_RDY 24 CRC_CHG 23 CRC_DONE 22 21 Reserved ZXTOAV 20 ZXBI 19 ZXAI 18 17 Reserved ZXAV 16 RSTDONE Settings Rev. 0 | Page 38 of 50 Description When set, this indicates a bit in the CHIP_STATUS register is set. This bit is cleared when CHIP_STATUS is read. When set, this indicates a bit in the EVENT_STATUS register is set. This bit is cleared when EVENT_STATUS is read. When set, this indicates a bit in the MS_STATUS_IRQ register is set. This bit is cleared when MS_STATUS_ IRQ is read. Reserved. This bit goes high to indicate when the power factor measurements are updated, every 1.024 sec. This bit is set if any of the registers monitored by the configuration register CRC change value. The CRC_RSLT register holds the new configuration register CRC value. This bit is set to indicate when the configuration register CRC calculation is complete, after being initiated by writing to the FORCE_CRC_UPDATE bit in the CRC_FORCE register. Reserved. This bit is set to indicate a zero-crossing timeout on the voltage channel; this means that a zero crossing on the voltage channel is missing. This bit is set to 1 to indicate that a zero crossing is detected on Current Channel B. This bit is set to 1 to indicate that a zero crossing is detected on Current Channel A. Reserved. This bit is set to 1 to indicate that a zero crossing is detected on Voltage Channel. This bit is set to indicate that the IC finished the power-up sequence after a reset, which means that the user can configure the IC via the SPI port or UART. Reset 0x0 Access R 0x0 R 0x0 R 0x0 0x0 R R/W1 0x0 R/W1 0x0 R/W1 0x0 0x0 R R/W1 0x0 R/W1 0x0 R/W1 0x0 0x0 R R/W1 0x0 R/W1 Data Sheet Addr. Name ADE9153A Bits 15 Bit Name FVARNL 14 VANL 13 WATTNL 12 TEMP_RDY 11 RMS_OC_RDY 10 PWRRDY 9 DREADY 8 EGYRDY 7 CF2 6 CF1 5 REVPCF2 4 REVPCF1 3 Reserved Settings Rev. 0 | Page 39 of 50 Description This bit is set when fundamental reactive energy enters or exits the no load condition. This bit is set when total apparent energy enters or exits the no load condition. This bit is set when total active energy enters or exits the no load condition. This bit is set when there is a new temperature reading ready from the temperature sensor. This bit is set when the RMS_OC values update. This bit is set when the power values in the AWATT_ ACC, AVA_ACC, and AFVAR_ ACC registers update, after PWR_TIME 4 kSPS samples. This bit is set when new waveform samples are ready. This bit is set when the power values in the AWATTHR_x, AVAHR, and AFVARHR registers update, after EGY_ TIME 4 kSPS samples or line cycles, depending on the EGY_TMR_MODE bit in the EP_CFG register. This bit is set when a CF2 pulse is issued, when the CF2 pin goes from a high to low state. This bit is set when a CF1 pulse is issued, when the CF1 pin goes from a high to low state. This bit is set to indicate if the CF2 polarity changed sign. For example, if the last CF2 pulse was positive active energy and the next CF2 pulse is negative active energy, the REVPCF2 bit is set. This bit is updated when a CF2 pulse is output, when the CF2 pin goes from high to low. This bit is set to indicate if the CF1 polarity changed sign. See the REVPCF2 description. Reserved. Reset 0x0 Access R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R/W1 0x0 R ADE9153A Addr. 0x405 Name Mask Data Sheet Bits 2 Bit Name REVRPA 1 0 Reserved REVAPA 31 CHIP_STAT 30 EVENT_STAT 29 MS_STAT [28:26] 25 Reserved PF_RDY 24 CRC_CHG 23 CRC_DONE 22 21 Reserved ZXTOAV 20 ZXBI Settings Rev. 0 | Page 40 of 50 Description This bit indicates if the Phase A fundamental reactive power changed sign. This bit is updated when the power value in the AFVAR_ACC register updates, after PWR_TIME 4 kSPS samples. Reserved. This bit indicates if the Phase A total active power changes sign. See the REVRPA description. Set this bit to enable an interrupt when any bit in the CHIP_STATUS register is set. Set this bit to enable an interrupt when any bit in the EVENT_STATUS register is set. Set this bit to enable an interrupt when any bit in the MSURE_STATUS_IRQ register is set. Reserved. Set this bit to enable an interrupt when the power factor measurements update, every 1.024 sec. Set this bit to enable an interrupt if any of the registers monitored by the configuration register CRC change value. The CRC_RSLT register holds the new configuration register CRC value. Set this bit to enable an interrupt when the configuration register CRC calculation is complete, after being initiated by writing the FORCE_CRC_UPDATE bit in the CRC_FORCE register. Reserved. Set this bit to enable an interrupt when there is a zero-crossing timeout on the voltage channel; this means that a zero crossing on the voltage channel is missing. Set this bit to enable an interrupt when a zero crossing is detected on Current Channel B. Reset 0x0 Access R/W1 0x0 0x0 R R/W1 0x0 R 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W Data Sheet Addr. Name ADE9153A Bits 19 Bit Name ZXAI 18 17 Reserved ZXAV 16 15 Reserved FVARNL 14 VANL 13 WATTNL 12 TEMP_RDY 11 RMS_OC_RDY 10 PWRRDY 9 DREADY 8 EGYRDY 7 CF2 6 CF1 5 REVPCF2 Settings Rev. 0 | Page 41 of 50 Description Set this bit to enable an interrupt when a zero crossing is detected on Current Channel A. Reserved. Set this bit to enable an interrupt when a zero crossing is detected on the voltage channel. Reserved. Set this bit to enable an interrupt when fundamental reactive energy enters or exits the no load condition. Set this bit to enable an interrupt when total apparent energy enters or exits the no load condition. Set this bit to enable an interrupt when the total active energy enters or exits the no load condition. Set this bit to enable an interrupt when there is a new temperature reading ready from the temperature sensor. Set this bit to enable an interrupt when the RMS_OC values update. Set this bit to enable an interrupt when the power value in the AWATT_ACC, AVA_ACC, and AFVAR_ACC registers update after PWR_TIME 4 kSPS samples. Set this bit to enable an interrupt when new waveform samples are ready. Set this bit to enable an interrupt when the power values in the AWATTHR, AVAHR, and AFVARHR registers update, after EGY_TIME 4 kSPS samples or line cycles, depending on the EGY_TMR_MODE bit in the EP_CFG register. Set this bit to enable and interrupt when the CF2 pulse is issued, when the CF2 pin goes from a high to low state. Set this bit to enable and interrupt when the CF1 pulse is issued, when the CF1 pin goes from a high to low state. Set this bit to enabled an interrupt when the CF2 polarity changed sign. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W ADE9153A Addr. Name Data Sheet Bits 4 Bit Name REVPCF1 3 2 Reserved REVRPA 1 0 Reserved REVAPA 0x409 OI_LVL [31:24] [23:0] Reserved OILVL_VAL 0x40A OIA [31:24] [23:0] Reserved OIA_VAL 0x40B OIB [31:24] [23:0] Reserved OIB_VAL 0x40F VLEVEL [31:24] [23:0] Reserved VLEVEL_VAL 0x411 DIPA [31:24] [23:0] Reserved DIPA_VAL 0x415 SWELLA [31:24] [23:0] Reserved SWELLA_VAL 0x41F PHNOLOAD [31:3] 2 Reserved AFVARNL 1 AVANL 0 AWATTNL Settings Rev. 0 | Page 42 of 50 Description Set this bit to enabled an interrupt when the CF1 polarity changed sign. Reserved. Set this bit to enable an interrupt when the Phase A fundamental reactive power has changed sign. Reserved. Set this bit to enable an interrupt when the Phase A total active power changes sign. Reserved. Overcurrent detection threshold level. Reserved. Current Channel A overcurrent RMS_OC value. If this phase is enabled with the OIA_EN bit set in the CONFIG3 register and AIRMS_OC is greater than the OILVL threshold, this value updates. Reserved. Current Channel B overcurrent RMS_OC value. If this phase is enabled with the OIB_EN bit set in the CONFIG3 register and BIRMS_OC is greater than the OILVL threshold, this value updates. Reserved. This register is used in the algorithm that computes the fundamental reactive power. Reserved. Voltage channel RMS_OC value during a dip condition. Reserved. Voltage channel RMS_OC value during a swell condition. Reserved. This bit is set if the Phase A fundamental reactive energy is in no load. This bit is set if the Phase A total apparent energy is in no load. This bit is set if the Phase A total active energy is in no load. Reset 0x0 Access R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0xFFFFFF R R/W 0x0 0x0 R R 0x0 0x0 R R 0x0 0x45D450 R R/W 0x0 0x7FFFFF R R 0x0 0x0 R R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Data Sheet Addr. 0x425 0x471 0x481 Name CF_LCFG TEMP_TRIM CONFIG1 ADE9153A Bits [31:21] 20 Bit Name Reserved CF2_LT Settings 19 CF1_LT [18:0] CF_LTMR [31:16] TEMP_OFFSET [15:0] TEMP_GAIN 15 EXT_REF 14 DIP_SWELL_IRQ_MODE 0 1 [13:12] 11 Reserved BURST_EN 10 [9:8] Reserved PWR_SETTLE 0 1 10 11 [7:6] 5 Reserved CF_ACC_CLR Rev. 0 | Page 43 of 50 Description Reserved. If this bit is set, the CF2 pulse width is determined by the CF_LTMR register value. If this bit is equal to zero, the active low pulse width is set as 80 ms for frequencies lower than 6.25 Hz. If this bit is set, the CF1 pulse width is determined by the CF_LTMR register value. See the CF2_LT description. If the CFx_LT bit in the CF_LCFG register is set, this value determines the active low pulse width of the CFx pulse. Offset of temperature sensor, calculated during the manufacturing process. Gain of temperature sensor, calculated during the manufacturing process. Set this bit if using an external voltage reference. This bit sets the interrupt mode for dip/swell. Receive continuous interrupts after every DIP_CYC/SWELL_CYC cycles. Receive one interrupt when entering dip/swell condition and another interrupt when exiting dip/swell condition. Reserved. Set this bit to enable burst read functionality on the registers. Note that this bit disables the CRC being appended to SPI register reads. Reserved. These bits configure the time for the power and filterbased rms measurements to settle before starting the power, energy, and CF accumulations. 64 ms. 128 ms. 256 ms. 0 ms. Reserved. Set this bit to clear the accumulation in the digital to frequency converter and the CFDEN counter. This bit automatically clears itself. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x3 R R/W 0x0 0x0 R W ADE9153A Addr. 0x490 Name CFMODE Data Sheet Bits [4:3] 2 Bit Name Reserved ZX_OUT_OE 1 DREADY_OE 0 SWRST [15:8] 7 Reserved CF2DIS 6 CF1DIS [5:3] CF2SEL Settings 0 10 100 0x492 ACCMODE [2:0] CF1SEL [15:5] 4 Reserved SELFREQ 0 1 [3:2] VARACC 0 1 10 11 [1:0] WATTACC Rev. 0 | Page 44 of 50 Description Reserved. When this bit is set, ZX is driven to the CF2 pin. When this bit is set, DREADY is driven to the CF2 pin. Set this bit to initiate a software reset. This bit is self clearing. Reserved. CF2 output disable. Set this bit to disable the CF2 output and bring the pin high. Note that when this bit is set, the CFx bit in the status register is not set when a CF pulse is accumulated in the digital to frequency converter. CF1 output disable. See the CF2DIS description. Type of energy output on the CF2 pin. Total active power. Total apparent power. Fundamental reactive power. Selects type of energy output on the CF1 pin. See the CF2SEL description. Reserved. System frequency select bit. 50 Hz system. 60 Hz system. Fundamental reactive power accumulation mode for energy registers and CFx pulses. Signed accumulation mode. Absolute value accumulation mode. Positive accumulation mode. Negative accumulation mode. Total active power accumulation mode for energy registers and CFx pulses. See the VARACC description. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 W1 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W Data Sheet Addr. 0x493 Name CONFIG3 ADE9153A Bits [15:4] [3:2] Bit Name Reserved PEAK_SEL Settings 0 1 10 11 1 OIB_EN 0 OIA_EN 0x49A ZX_CFG [15:1] 0 Reserved DISZXLPF 0x49D PHSIGN [15:8] 7 Reserved CF2SIGN 6 CF1SIGN [5:2] 1 Reserved AVARSIGN 0 AWSIGN Rev. 0 | Page 45 of 50 Description Reserved. Peak detection phase selection. Phase A and Phase B disabled from voltage and current peak detection. Phase A Voltage and current peak detection enabled, Phase B current peak detection disabled. Phase A voltage and current peak detection disabled, Phase B current peak detection enabled. Phase A and Phase B enabled for voltage and current peak detection. Overcurrent detection enable for Current Channel B. Overcurrent detection enable for Current Channel A. Reserved. Zero-crossing low-pass filter disable. Reserved. Sign of the power in the CF2 datapath. The CF2 energy is positive if this bit is clear and negative if this bit is set. Sign of the power in the CF1 datapath. See the CF2SIGN description. Reserved. Phase A fundamental reactive power sign bit. The fundamental reactive power is positive if this bit is clear and negative if this bit is set. Phase A active power sign bit. The active power is positive if this bit is clear and negative if this bit is set. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R 0x0 R 0x0 0x0 R R 0x0 R ADE9153A Addr. 0x4AF Name CONFIG2 Data Sheet Bits [15:13] 12 Bit Name Reserved UPERIOD_SEL [11:9] HPF_CRN Settings 0 1 10 11 100 101 110 111 0x4B0 EP_CFG [8:0] [15:8] [7:5] Reserved Reserved NOLOAD_TMR 0 1 10 11 100 101 110 111 4 3 Reserved RD_RST_EN 2 EGY_LD_ACCUM Rev. 0 | Page 46 of 50 Description Reserved. Set this bit to use a user configured line period, in USER_PERIOD, for RMS_OC calculation. If this bit is clear, the voltage line period is used. High-pass filter corner (f3 dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. 38.695 Hz. 19.6375 Hz. 9.895 Hz. 4.9675 Hz. 2.49 Hz. 1.2475 Hz. 0.625 Hz. 0.3125 Hz. Reserved. Reserved. This register configures how many 4 kSPS samples over which to evaluate the no load condition. 64 samples. 128 samples. 256 samples. 512 samples. 1024 samples. 2048 samples. 4096 samples. Disable no load threshold. Reserved. Set this bit to enable the energy register read with reset feature. If this bit is set, when one of the AWATTHR_x, AFVARHR, or AVAHR registers are read, it is reset and begins accumulating energy from zero. If this bit is equal to zero, the internal energy register is added to the user accessible energy register. If this bit is set, the internal energy register overwrites the user accessible energy register when the EGYRDY event occurs. Reset 0x0 0x0 Access R R/W 0x6 R/W 0x0 0x0 0x0 R R R/W 0x0 0x0 R R/W 0x0 R/W Data Sheet Addr. Name ADE9153A Bits 1 Bit Name EGY_TMR_MODE Settings 0 1 0 EGY_PWR_EN 0x4B4 CRC_FORCE [15:1] 0 Reserved FORCE_CRC_UPDATE 0x4B6 TEMP_CFG [15:4] 3 Reserved TEMP_START 2 TEMP_EN [1:0] TEMP_TIME 0 1 10 11 0x4B7 TEMP_RSLT [15:12] [11:0] Reserved TEMP_RESULT 0x4B9 AI_PGAGAIN [15:5] 4 Reserved AI_SWAP 0 1 Rev. 0 | Page 47 of 50 Description This bit determines whether energy is accumulated based on the number of 4 kSPS samples or zero-crossing events configured in the EGY_TIME register. Accumulate energy based on 4 kSPS samples. Accumulate energy based on the zero-crossing events. Set this bit to enable the energy and power accumulator when the run bit is also set. Reserved. Write this bit to force the configuration register CRC calculation to start. When the calculation is complete, the CRC_DONE bit is set in the status register. Reserved. Set this bit to manually request a new temperature sensor reading. The new temperature reading is available in 1 ms, indicated by the TEMP_RDY bit in the status register. Note that this bit is self clearing. Set this bit to enable the temperature sensor. These bits select the number of temperature readings to average. 1 sample. New temperature measurement every 1ms. 256 samples. New temperature measurement every 256 ms. 512 samples. New temperature measurement every 512 ms. 1024 samples. New temperature measurement every 1 sec. Reserved. 12-bit temperature sensor result Reserved. This bit sets the signal side of the PGA, meaning that the IAP and IAN pins can be swapped by setting this bit. This bit must be set to 1 for proper operation, only set to 0 if sensor is connected in reverse. Signal on IAN. Signal on IAP. Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 R W1 0x0 0x0 R W1 0x0 R/W 0x0 R/W 0x0 0x0 R R 0x0 0x0 R R/W ADE9153A Addr. Name Data Sheet Bits 3 [2:0] Bit Name Reserved AI_GAIN Settings 10 11 100 101 0x4C0 MS_STATUS_IRQ 15 14 Reserved MS_SYSRDY 13 MS_CONFERR 12 MS_ABSENT 11 10 9 8 7 6 5 4 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MS_TIMEOUT 2 1 Reserved MS_READY 0 MS_SHIFT Rev. 0 | Page 48 of 50 Description Reserved. PGA gain for Current Channel A. Gain = 16. Gain = 24. Gain = 32. Gain = 38.4. Reserved. This bit is set when a new run of mSure is ready to be enabled after a run of mSure is disabled. A new run is ready less than 1 sec after disabling the previous run. This bit is set if there is an invalid configuration of mSure autocalibration. Fix the configuration error and try it running again. When this bit is set, mSure is not detected on the channel that was last enabled. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. This bit is set when mSure times out after 600 sec. Reserved. This bit is set when the mSure result registers first start to be populated (after the 8 sec block). Then, this bit is set every second for when the value is updated until mSure is stopped. This bit is set when there is a shift in the mSure CC value in the middle of a run, meaning that the value found for the xCC shifted and another run of mSure with the same settings must be performed to verify the shift. Reset 0x0 0x0 Access R R/W 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R R R R R R R R R 0x0 0x0 R R 0x0 R Data Sheet Addr. 0x4C1 0x4C2 Name EVENT_STATUS CHIP_STATUS ADE9153A Bits [15:6] 5 Bit Name Reserved OIB 4 OIA 3 2 Reserved SWELLA 1 0 Reserved DIPA [15:8] 7 Reserved UART_RESET 6 UART_ERROR2 5 UART_ERROR1 4 UART_ERROR0 3 ERROR3 2 ERROR2 1 ERROR1 0 ERROR0 Settings Rev. 0 | Page 49 of 50 Description Reserved. This bit is set when Current Channel B is in an overcurrent condition and is zero when it is not in an overcurrent condition. This bit is set when Current Channel A is in an overcurrent condition and is zero when it is not in an overcurrent condition. Reserved. This bit is set when the voltage channel is in a swell condition and is zero when it is not in a swell condition. Reserved. This bit is set when the voltage channel is in the dip condition and is zero when it is not in a dip condition. Reserved. When this bit is set, a UART interface reset is detected. Reset the UART interface to clear this error. Reset the UART interface to clear this error. Reset the UART interface to clear this error. Issue a software reset or hardware reset to clear this error. Issue a software reset or hardware reset to clear this error. Issue a software reset or hardware reset to clear this error. Issue a software reset or hardware reset to clear this error. Reset 0x0 0x0 Access R R 0x0 R 0x0 0x0 R R 0x0 0x0 R R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R ADE9153A Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 1 0.50 BSC 3.75 3.60 SQ 3.55 EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-004570 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 24 0.50 0.40 0.30 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 10-20-2017-C PIN 1 INDICATOR 0.30 0.25 0.18 Figure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 ADE9153AACPZ ADE9153AACPZ-RL EV-ADE9153ASHIELDZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP], 13" Tape and Reel Arduino Shield Evaluation Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16519-0-2/18(0) Rev. 0 | Page 50 of 50 Package Option CP-32-12 CP-32-12