1. General description
The NVT2003/04/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain or
push-pull applications. Bit wid ths ranging from 3-bit to 6-bit are of fered for level translation
application with transmission speeds < 33 MHz for an open-drain system with a 50 pF
capacitance and a pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREF A. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional dat a flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high - imp ed a nc e state durin g
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
2.5 V Vref(A) and 5 V Vref(B)
3.3 V Vref(A) and 5 V Vref(B)
NVT2003/04/06
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 3 — 25 October 2011 Product data sheet
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Product data sheet Rev. 3 — 25 October 2011 2 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Low 3.5 ON-state connection be tween input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP10, HXSON12, DHVQFN16, HVQFN16, TSSOP16
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Tamb =
40
C to +85
C.
Type number Topside
mark Number
of bits Package
Name Description Version
NVT2003DP N2003 3 TSSOP10 plastic thin shrink small outline package; 10 leads;
body width 3 mm SOT552-1
NVT2004TL N04 4 HXSON12 plastic, thermal enhanced extremely thin small outline
package; no leads; 12 terminals;
body 1.35 2.5 0.5 mm
SOT973-2
NVT2006BQ N2006 6 DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
NVT2006BS N06 6 HVQFN16 plastic thermal enh anced very thin quad flat package;
no leads; 16 terminals; body 3 30.85 mm SOT758-1
NVT2006PW NVT2006 6 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Logic diagram of NVT2003/04/06 (positive logic)
002aae132
A1
An
VREFA
GND
VREFB
B1
Bn
EN
SW
SW
NVT20xx
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Product data sheet Rev. 3 — 25 October 2011 3 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
5. Pinning information
5.1 Pinning
5.1.1 3-bit in TSSOP10 package
5.1.2 4-bit in HXSON12 package
Fig 2. Pi n co nfi gura tio n for TSSOP10
NVT2003DP
GND EN
VREFA VREFB
A1 B1
A2 B2
A3 B3
002aae836
1
2
3
4
56
8
7
10
9
Fig 3. Pi n confi gura tion for HXSON12U
002aae219
NVT2004TL
Transparent top view
112GND EN
211VREFA VREFB
310A1 B1
67A4 B4
49A2 B2
58A3 B3
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Product data sheet Rev. 3 — 25 October 2011 4 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packages
Fig 4. Pin configuration for TSSOP16 Fig 5. Pin configuration for DHVQFN16
Fig 6. Pin configuration for HVQFN16
NVT2006PW
GND EN
VREFA VREFB
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
002aae220
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
002aae221
NVT2006BQ
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
VREFA VREFB
A6
B6
GND
EN
Transparent top view
7 10
6 11
5 12
413
3 14
2 15
8
9
1
16
terminal 1
index area
002aae222
NVT2006BS
Transparent top view
A2 B6
A1 B5
VREFA B4
GND B3
A3
A4
A5
A6
EN
VREFB
B1
B2
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
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Product data sheet Rev. 3 — 25 October 2011 5 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
5.2 Pin description
[1] 3-bit NVT2003 available in TSSOP10 package.
[2] 4-bit NVT2004 available in HXSON12 package.
[3] 6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.
Table 2. Pin description
Symbol Pin Description
NVT2003[1] NVT2004[2] NVT2006[3]
GND 1 1 1 ground (0 V)
VREFA 2 2 2 low-voltage side reference supply voltage
for An
A1 - - - low-voltage side; connect to VREFA
through a pull-up resistor
A1 to An 3, 4, 5 3, 4, 5, 6 3, 4, 5, 6, 7, 8
B1 - - - high-voltage side; connect to VREFB
through a pull-up resistor
B1 to Bn 6, 7, 8 10, 9, 8, 7 14 , 13, 12,
11, 10, 9
VREFB 9 11 15 high-voltage side reference supply voltage
for Bn
EN 10 12 16 switch enable input; connect to VREFB
and pull-up through a high resistor
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Product data sheet Rev. 3 — 25 October 2011 6 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagram of NVT2003/04/06 (positive logic)”.
6.1 Function table
[1] EN is controlled by the Vref(B) logic levels and should be at least 1 V higher than Vref(A) for best translator
operation.
7. Application design-in information
The NVT2003/04/06 ca n be used in level translation applica tions for interfacing devices or
systems operating at dif ferent interface voltages with one another. The NVT2003/04/06 is
ideal for use in applications whe re an open-dra in driver is conne cted to the dat a I/Os. The
NVT2003/04/06 can also be used in applications where a push-pull driver is connected to
the data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
Table 3. Function selection (example)
H = HIGH level; L = LOW level.
Input EN[1] Function
HAn=Bn
L disconnect
(1) The applied voltages at Vref(A) and Vpu(D) should be such that Vref(B) is at least 1 V higher than
Vref(A) for best translator operation.
Fig 7. Typical application circuit (switch always en abled)
002aae134
A1
A2
VREFA
GND
3
4
VREFB
1
6
5
B1
B2
8EN
SW
SW
NVT2002
7
200 kΩ
RPU RPU
V
pu(D)
= 3.3 V
(1)
I
2
C-BUS
DEVICE
SCL
SDA
V
CC
GND
2
V
ref(A)
= 1.8 V
(1)
RPU RPU
I
2
C-BUS
MASTER
SCL
SDA
V
CC
GND
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Product data sheet Rev. 3 — 25 October 2011 7 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
[1] All typical values are at Tamb =25C.
Table 4. Application operating conditions
Refer to Figure 7.
Symbol Parameter Conditions Min Typ[1] Max Unit
Vref(B) reference voltage (B) Vref(A) +0.6 2.1 5 V
VI(EN) input voltage on pin EN Vref(A) +0.6 2.1 5 V
Vref(A) reference voltage (A) 0 1.5 4.4 V
Isw(pass) pass switch current - 14 - mA
Iref reference current transistor - 5 - A
Tamb ambient temperature operating in
free-air 40 - +85 C
(1) In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A) should be
such that Vref(B) is at least 1 V higher than Vref(A) for best translator operation.
(2) Note that the enable time and the disable time are essentially controlled by the RC time constant of
the capacitor and the 200 k resistor on the EN pin.
Fig 8. Typical application circuit (switch enable co ntrol)
002aae135
A1
A2
VREFA
GND
3
4
VREFB
1
6
5
B1
B2
8EN
SW
SW
NVT2002
7
200 kΩ
RPU RPU
V
pu(D)
= 3.3 V
I
2
C-BUS
DEVICE
SCL
SDA
V
CC
GND
2
V
ref(A)
= 1.8 V
(1)
RPU RPU
I
2
C-BUS
MASTER
SCL
SDA
V
CC
GND
on
off
3.3 V enable signal
(1)
(2)
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Product data sheet Rev. 3 — 25 October 2011 8 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to h igher voltage), the EN input m ust be connected to VREFB and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can b e totem pole or open-drain (pu ll-up resistors are requ ired to pull the Bn
outputs to Vpu(D)). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either dire ction. If both output s ar e open-drain, n o
direction control is needed.
The reference supply voltage (Vref(A)) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(A) is set between 1.0 V and (Vpu(D) 1 V ), the ou tp ut of ea ch An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to Vpu(D).
Fig 9. Bidirectional translation to multiple higher voltage levels
EN
VREFB
002aae133
B1
B2
200 kΩ
CHIPSET I/O
VCC
5 V
totem pole or
open-drain I/O
GND
VREFA
A1
A2
B3 VCC
Bn
3.3 V
A3
An
CPU I/O
VCORE
1.8 V
1.5 V
1.2 V
1.0 V
SW
NVT20XX
SW
SW
CHIPSET I/O
SW B4A4
B5A5 SW
SW B6A6
SW
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Product data sheet Rev. 3 — 25 October 2011 9 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.3 Bidirectional level shif ting between two different power domains
nominally at the same potential
The less obvious application for the NVT2003 is for level shifting between two different
power domains th at ar e no m ina lly at th e sa me pot en tia l, suc h as a 3.3 V syste m whe re
the line crosses power sup ply domains that unde r normal oper ation would be at 3.3 V, but
one could be at 3.0 V and the other at 3.6 V, or one could be experiencing a power failu re
while the other domain is trying to operate. One of the NVT2003 th ree ch annel transistors
is used as a second reference transistor with its B sid e connecte d to a volt age su pply that
is at least 1 V (and preferably 1.5 V) above the maximum possible for either Vpu(A) or
Vpu(B). Then if either pull-up voltage is at 0 V, the channels are disabled , and otherwise the
channels are biased such that they turn OFF at the lower pull-up voltage, and if the two
pull-up voltages are equal, the channel is biased such that it just turns OFF at the
common pull-up voltage.
7.4 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is
in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the
current through the p ass transistor is higher than 15 mA, the pass volt age also is higher in
the ON state. To set the current through each p ass transistor at 15 mA, the pull-up resistor
value is calculated as:
Table 5 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and 3 mA.
The resistor values shown in the +10 % column or a larger value should be used to
ensure that the p ass voltage of the tra nsistor would be 350 mV or less. The external driver
The applied enable voltage Vpu(H) and the applied voltage at Vref(A) and Vref(B) should be such that Vref(H) is at least 1 V higher
than Vref(A) and Vref(B) for best translator operation.
Fig 10. Bidirectional level shifting between two different power domains
002aae967
A1
A2
VREFA
GND
3
4
VREFB
1
8
7
B1
B2
10 EN
SW
SW
NVT2003
9
200 kΩ
RPU RPU
Vpu(B) = 3.3 V
I2C-BUS
DEVICE
SCL
SDA
VCC
GND
2
Vpu(A) = 3.3 V
RPU RPU
I2C-BUS
MASTER
SCL
SDA
VCC
GND
Vpu(H)
A3 5 6
SW B3
Vpu(B)
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Product data sheet Rev. 3 — 25 October 2011 10 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
must be able to sink the total current from the resistors on both sides of the NVT20xx
device at 0.175 V, although the 15 mA only applies to current flowing through the
NVT20xx device.
[1] +10 % to compensate for VCC range and resistor tolerance.
7.4.1 Maximum frequency calculation
The maximum freq uency is tota lly dependent u pon the sp ecifics of the application and the
device can operate > 33 MHz. Basically, the NVT20xx behaves like a wire with the
additional characte ristics of transistor device physics and should be capable of performing
at higher frequencies if used correctly.
Here are some guidelines to follow that will help maximize the performance of the device:
•Keep trace length to a minimum by placing the NVT20xx close to the processor.
•The trace length should have a time of flight less than half of the transition time to
reduce ringing an d re fle ctio n s .
•The faster the edge of the signal, the higher the chance for ringing.
•The higher the drive strength (up to 15 mA), the higher the frequency the device can
use.
In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type
driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of
concern is on the 1.8 V side since it is driven through the ON resistance of the NVT20xx.
If the line length on the 1.8 V side is long enough there can be a reflection at the
chip/terminating end of the wir e when the transition time is shorter than the time of flight of
the wire because the NVT20xx looks like a high-impedance compared to the wire. If the
wire is not too long and the lumped capacitance is not excessive the signal will only be
slightly degraded by the series resistance added by passing through the NVT20xx. If the
lumped capacitance is large the rise time will deteriorate, the fall time is much less
affected and if the rise time is slowed down too much the duty cycle of the clock will be
degraded and at some point the clock will no longer be useful. So the principle design
consideration is to minimize the wire length and the capacitance on the 1.8 V side for the
clock path. A pull-u p resistor on the 1.8 V side can also be used to trade a slower fall time
for a faster rise time and can also reduce the overshoot in some cases.
Table 5. Pull-up resistor values
Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.
Vpu(D) Pull-up resistor value ()
64 mA 32 mA 15 mA 10 mA 3mA
Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1]
5 V 310 341 465 512 1550 1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V 77 85 115 127 383 422
1.2 V 57 63 85 94 283 312
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Product data sheet Rev. 3 — 25 October 2011 11 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
7.4.1.1 Example maximum frequency
Question — W e need to make the PL L area of a new line card backwards comp atible and
need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL.
The signal we want to convert is random in nature but will mostly be around 19 MHz with
very long periods of inactivity where either a HIGH or LOW state will be maintained. The
traces are 1 or 2 inches lon g with tra ce capacitance of about 2 pF per inch .
Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the
capacitance of the traces and the pull-up resistors used. The limitin g case is pr oba bly th e
LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest
acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance
and 220 resistance, the RC time constant is 11 ns (50 pF 220 ). With 19 MHz
corresponding to 50 ns period the NVT20xx will support this application.
8. Limiting values
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
[2] Low duty cycle pulses, not DC because of heating.
9. Recommended operating conditions
[1] Vref(A) Vref(B) 1 V for best results in level shifting applications.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol Parameter Conditions Min Max Unit
Vref(A) reference voltage (A) 0.5 +6 V
Vref(B) reference voltage (B) 0.5 +6 V
VIinput voltage 0.5[1] +6 V
VI/O voltage on an input/output pin 0.5[1] +6 V
Ich channel current (DC) - 128 mA
IIK input clamping current VI<0V 50 - mA
IOK output clamping current [2] 50 +50 mA
Tstg storage temperature 65 +150 C
Table 7. Operating conditions
Symbol Parameter Conditions Min Max Unit
VI/O voltage on an input/output pin An, Bn 0 5.5 V
Vref(A) reference voltage (A) VREFA [1] 05.4V
Vref(B) reference voltage (B) VREFB [1] 05.5V
VI(EN) input voltage on pin EN 0 5.5 V
Isw(pass) pass switch current - 64 mA
Tamb ambient temperature operating in free-air 40 +85 C
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Product data sheet Rev. 3 — 25 October 2011 12 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
10. Static characteristics
[1] All typical values are at Tamb =25C.
[2] Not production tested, maximum value based on characterization data of typical parts.
[3] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two terminals.
[4] See curves in Figure 11 for typical temperature and VI(EN) behavior.
[5] Guaranteed by design.
Table 8. Static characteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VIK input clamping voltage II=18 mA; VI(EN) =0V - - 1.2 V
IIH HIGH-level input current VI=5V; V
I(EN) =0V --5A
Ci(EN) input capacitance on pin EN VI= 3 V or 0 V - 12 - pF
Cio(off) off-state input/output capacitance An, Bn; VO=3Vor0V;
VI(EN) =0V - 57pF
Cio(on) on-state input/output capacitance An, Bn; VO=3Vor0V;
VI(EN) =3V -11.513
[2] pF
Ron ON-state resistance An, Bn; VI=0V;I
O=64mA;
VI(EN) =4.5V [3][4][5] 12.45.0
VI=2.4V; I
O=15mA;
VI(EN) =4.5V [3][4] -4.87.5
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Product data sheet Rev. 3 — 25 October 2011 13 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
a. IO=64mA; V
I=0V b. I
O=15mA; V
I=2.4V; V
I(EN) =4.5V
c. IO=15mA; V
I= 2.4 V; VI(EN) =3.0V d. I
O=15mA; V
I=1.7V; V
I(EN) =2.3V
Fig 11. NVT2006 typical ON-state resistance versus ambient temperature
Tamb (°C)
−40 100−20
002aaf680
0 20 40 60 80
4
6
2
8
10
Ron(typ)
(Ω)
0
VI(EN) = 1.5 V
2.3 V
3.0 V
4.5 V
Tamb (°C)
−40 100−20
002aaf681
0 20 40 60 80
2
8
Ron(typ)
(Ω)
0
6
4
Tamb (°C)
−40 100−20
002aaf682
0 20 40 60 80
20
80
Ron(typ)
(Ω)
0
60
40
Tamb (°C)
−40 100−20
002aaf683
0 20 40 60 80
20
80
Ron(typ)
(Ω)
0
60
40
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Product data sheet Rev. 3 — 25 October 2011 14 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
11. Dynamic characteristics
11.1 Open-drain drivers
[1] See graphs based on Ron typical and Cio(on) +C
L=50pF.
Table 9. Dynamic characteristics for open-drain drivers
Tamb =
40
Cto+85
C; VI(EN) =V
ref(B); unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Figure 14
tPLH LOW to HIGH
propagation delay from (input) Bn
to (output) An [1] Ron (CL + Cio(on))ns
tPHL HIGH to LOW
propagation delay from (input) Bn
to (output) An Ron (CL + Cio(on))ns
Fig 12. AC test setup Fig 13. Example of typical AC waveform
002aaf347
DUT
EN VREFB
VREFA
1.5 V
200 kΩ
SIGNAL
GENERATOR
5.5 V
0.1 μF
1.5 V swing
50 pF 450 Ω
500 Ω
6.6 V
1 V/div
40 ns/div
002aaf348
Bn
An
GND
GND
a. Load circuit b. Timing diagram; high-impedance scope probe
used
S2 = translating down, and same voltage.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo=50; tr2ns; t
f2ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 14. Load circuit for outputs
002aab845
VTT
RL
S1
S2 (open)
CL
from output under test
002aab846
V
IH
V
IL
V
M
V
M
input
output
V
OH
V
OL
V
M
V
M
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12. Performance curves
tPLH up-translation is typically dominated by the RC time constant, i.e.,
CL(tot) RPU =50pF197 = 9.85 ns, but the Ron CL(tot) =50pF5=0.250ns.
tPHL is typically domina te d by the external pull-d o w n drive r + R on, which is typically small
compared to the tPLH in an up-translation case.
Enable/disable times are dominated by the RC time constant on the EN pin since the
transistor turn off is on the order of ns, but the enable RC is on the order of ms.
Fall time is dominated by the external pull-down driver with only a slight Ron addition.
Rise time is dominated by the RPU CL.
Skew time within the part is virtually non-existent, dominated by the difference in bond
wire lengths, which is typically small compared to the board-level ro uting differences.
Maximum data rate is dominated by the system capacitance and pull-up resistors.
(1) VI(EN) = 1.5 V; IO=64mA; V
I=0V.
(2) VI(EN) = 4.5 V; IO=15mA; V
I=2.4V.
(3) VI(EN) = 2.3 V; IO=64mA; V
I=0V.
(4) VI(EN) = 3.0 V; IO=64mA; V
I=0V.
(5) VI(EN) = 4.5 V; IO=64mA; V
I=0V.
(1) VI(EN) = 3.0 V; IO=15mA; V
I=2.4V.
(2) VI(EN) = 2.3 V; IO=15mA; V
I=1.7V.
Fig 15. NVT2006 typical capacitance versus propagation delay
0.2
0.4
0.6
tPD
(ns)
0
C (pF)
0 1008040 6020
002aaf707
(1)
(2)
(3)
(4)
(5)
1
2
3
tPD
(ns)
0
C (pF)
0 1008040 6020
002aaf708
(1)
(2)
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Bidirectional voltage-level translator
13. Package outline
Fig 16. Package outline SOT552-1 (TSSOP10)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.15 0.23
0.15 3.1
2.9 3.1
2.9 0.5 5.0
4.8 0.67
0.34 6°
0°
0.1 0.10.10.95
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.7
0.4
SOT552-1 99-07-29
03-02-18
wM
bp
D
Z
e
0.25
15
10 6
θ
A
A2A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm SOT552-1
1.1
pin 1 index
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Product data sheet Rev. 3 — 25 October 2011 17 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Fig 17. Package outline SOT973-2 (HXSON12)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT973-2 - - -
- - -
- - -
sot973-2_po
10-03-23
10-03-25
Unit(1)
mm max
nom
min
0.5 0.05
0.00 0.127 2.6
2.5
2.4
2.1
2.0
1.9
1.45
1.35
1.25 0.4 2 0.30
0.25
0.20 0.05
A
Dimensions
Note
1. Plastic or metal protrusions 0.0075 mm maximum per side are not included.
HXSON12: plastic, thermal enhanced extremely thin small outline package; no leads;
12 terminals; body 1.35 x 2.5 x 0.5 mm SOT973-2
A1b
0.25
0.20
0.15
cDD
hEE
h
0.45
0.40
0.35
ee
1k
0.2
Lv
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y
C
y1
detail X
c
A
A1
terminal 1
index area
BA
D
E
b
terminal 1
index area e1
eAC B
vCw
k
L
Dh
Eh
16
12 7
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Product data sheet Rev. 3 — 25 October 2011 18 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Fig 18. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
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Product data sheet Rev. 3 — 25 October 2011 19 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Fig 19. Package outline SOT758-1 (HVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT y
e
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.75
1.45
y1
3.1
2.9 1.75
1.45
e1
1.5
e2
1.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT758-1 MO-220 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT758-1
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
58
16 13
12
9
4
1
X
D
E
C
BA
e2
02-03-25
02-10-21
terminal 1
index area
1/2 e
1/2 e
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
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Product data sheet Rev. 3 — 25 October 2011 20 of 27
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Bidirectional voltage-level translator
Fig 20. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
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Product data sheet Rev. 3 — 25 October 2011 21 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
Table 10. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 11. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
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Product data sheet Rev. 3 — 25 October 2011 23 of 27
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Bidirectional voltage-level translator
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 12. Abbreviations
Acronym Description
CDM Charged Device Model
ESD ElectroStatic Discharge
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
I/O Input/Output
PRR Pulse Repetition Rate
RC Resistor-Capacitor network
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16. Revision history
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
NVT2003_04_06 v.3 20111025 Product data sheet - NVT2003_04_06 v.2
Modifications: •Section 2 “Features and benefits”,
–9th bullet item: removed phrase “200 V MM per JESD22-A115”
–10th bullet item: deleted “HXSON16U”
•Table 1 “Ordering information”: removed type number NVT2006TL (HXSON16U, SOT985-1)
•Section 5.1.3: removed “HXSON16U” from section title
•Deleted (old) Figure 7, “Pin configuration for HXSON16U”
•Table 2 “Pin description”, Table note [3]: deleted “HXSON16U”
•Deleted (old) Figure 22, “Package ou tline SOT985-1 (HXSON16U)”
NVT2003_04_06 v.2 20110329 Product data sheet - NVT2003_04_06 v.1
NVT2003_04_06 v.1 20101004 Product data sheet - -
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Product data sheet Rev. 3 — 25 October 2011 25 of 27
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Bidirectional voltage-level translator
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or envi ronmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby exp r essly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 3 — 25 October 2011 26 of 27
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors NVT2003/04/06
Bidirectional voltage-level translator
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 October 2011
Document identifier: NVT2003_04_06
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.1.1 3-bit in TSSOP10 package. . . . . . . . . . . . . . . . 3
5.1.2 4-bit in HXSON12 package. . . . . . . . . . . . . . . . 3
5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 6
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Application d esign-in inform ation . . . . . . . . . . 6
7.1 Enable and disable. . . . . . . . . . . . . . . . . . . . . . 6
7.2 Bidirectional translation . . . . . . . . . . . . . . . . . . 8
7.3 Bidirectional level shifting between two
different power domains nominally
at the same potential . . . . . . . . . . . . . . . . . . . . 9
7.4 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 9
7.4.1 Maximum frequency calculation . . . . . . . . . . . 10
7.4.1.1 Example maximum frequency . . . . . . . . . . . . 11
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
9 Recommended operating conditions. . . . . . . 11
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 12
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14
11.1 Open-drain drivers . . . . . . . . . . . . . . . . . . . . . 14
12 Performance curves . . . . . . . . . . . . . . . . . . . . 15
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Soldering of SMD packages . . . . . . . . . . . . . . 21
14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21
14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 21
14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21
14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22
15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18 Contact information. . . . . . . . . . . . . . . . . . . . . 26
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27