Field Programmable Gate Array (FPGAs) - Application Notes - Atmel Corporation

Implementing Cache Logic® with FPGAs

The Cache Logic Concept

Atmel Corporation has developed an

enabling technology to make adaptive

hardware possible for electronics sys-

tems. This capability, trademarked as

Cache Logic, was developed and pat-

ented by Atmel Corporation.(1)

Cache Logic is a cost-saving way of

implementing logic more efficiently. The

active functions of an application are

perfo rmed by a fi eld prog ramma ble gat e

array (FPGA) that can be reconfigure d

as it operates, while inactive functions

are stored in an inexpensive configura-

tion me mory – a n EPROM , for ex ample.

As new functio ns are required, they are

written over old ones.

A single application is made up of many

smaller macro-level operations, like

counters, multipliers, shift registers, and

multiplexers. When an application is bro-

ken down into its sub-operations, two

things become apparent. First, function-

ality overlaps. A single function may be

used a number o f different t imes. Sec-

ond, there is a high degree of functional

latency. At any given moment, only a

small portion of an application’s opera-

tions are ac tive; only a few fu nctions ar e

used at the same time.

By consolidating functionality, eliminat-

ing redundancy, and tracking the

occurrence of each sub-operation, func-

tions can be organized such that a

relativ ely smal l, inexpen sive logi c device

is reconfigured as it operates to perform

a complex function. In a 10,000-gate

application, for example, only 2,000

gates might be a ctive at once. By cach-

ing the extra 8,000 gates for later use, a

2,000-gate device replaces a more

expensive 10,000-gate device.

Cache Logic

Implementation

Cache Logic implementation is concep-

tually similar to c ache mem ory. In cach e

memory, the highest speed memory

(usually SRAM) is used to store active

data, while the bulk of data resides in

lower-cost storage, such as DRAM, or

EPROM, disk, etc. Cache Logic works in

a similar fas hio n. O nly a s ma ll fra ction of

the circuitry – those functions which are

loaded into the logic cache – is active in

a system at any given time, while

unused fun ctions or var iations resid e in

lower-cost system memory. It is even

possible to compile variations of a

design in real time. As logic functions are

required, they can be loaded i nto cache

logic, replacing or complementing the

logic already present.

Figure 1 shows the block diagram for the

Atmel AT6000 FPGA, which is an ideal

medium for cache logic. The ability to

implement cache logic requires FPGAs

that are capable of being d ynamically

reconfigured in-system, either com-

pletely or partially, without disrupting the

operation of the balan ce of logic i n the

device. Another requirement is architec-

ture symmetry. This is necessary to

make possible the arbitrary placement of

generic blocks in a location that is

available at the time required. It is also

Field

Programmable

Gate Array

Application

Note

Rev. 0461C–09/99

Note: 1. The method for exploiting Cache Logic was pioneered by the University of Strath-

clyde in Scotland and is described in Lysaght, P. and Dunlop, J., “Dynamic

Reconfiguration of Field Programmable Gate Arrays”, in More FPGAs, W. Moore

and W. Luk, Eds., Abingdon EE&CS Books, England 1994.

FPGA

necessary to allow for easy modeling of device characteris-

tics for the artificial intelligence required in the partitioning

of a design. The symmetry also simplifies the creation of

arrays of devices to create a larger digital mediu m for the

implementation of cache logic.

Predetermined and Dynamic Cache

Logic

There are two types of cache logic which have been

defined: predetermined cache logic and dynamic cache

logic. Predetermined cach e logic invo lves the us e of pre-

defined functions and macros that are stored in external,

nonvolatile memory (EPROM, EEPROM, disk, CD-ROM,

or even memory remote from the system loaded over a

communications l ink). These functions have already been

placed and r outed and have bit str eams which have bee n

previously generated (Figure 2). The implementation of

these function s is controlled by a resident mana ger in the

logic c ache, or i n an external control suc h as a mi crocon-

troller/processor routine. New functions may be

downlo aded to the l ogic cache in the backg round withou t

disrup ting t he o per atio n of t he ca che (l ogic , I /O, and reg is-

ter data), as shown in Figure 3. In fact, data in the registers

is not lost even in the area being overwritten.

The se cond t ype o f cache logic , dynamic, is the ba sis for

building adaptive hardware. Dynamic caching involves the

determination of logic, placement and routing of the logic,

bit stre am gene ration, a nd progr ammin g the logi c cache in

real time. The major issues to be addressed in the develop-

ment of this capability include (but are not limited to) the

scheduling and allocation of functions, random-logic collec-

tion, and collision handling and avoidance within the cache.

Dynamic cache logic exists as a concept today; the physi-

cal implementation issues described abov e have not yet

been fully addressed.

Figure 1. AT6000 Array Figure 2. Macro Library

•Symmetrical Ar ray

•Identical Cells

•8-by-8 Cell Sectors

•Programmable Interconnects

•Surrounded by I/O

•No Dedicated Functions

•Reconfigurable On-the-fly

•Full

•Partial

•Without Data Loss

•Over 200 Hard Macros

•Fast

•Fully Specified

•Fixed Routing

•All Can be Softened

•Flexible Placement

•User-defined Macros

•Create Own Library

•Use on Future Designs

•Test Macros

•For Debug/System Test

•Super Macros

•Major Predefined Functions

•Specialized for Markets

FPGA

Cache Logic may be applied in many applications. The

concept of virtual products will be introduced, which utilizes

the flexibility of programmable logic. Virtual products do not

require cache logic programmability but, as we see, the use

of cache logic greatly redu ces the amount of programma-

ble digital media needed to implement a virtual product.

Vi rtual Products

A virtual product is a combination of a “tangible asset,”

such as a data acquisition board, and a service, such as

product customization. The first thing to understand about

virtual products is what the end cu stomer wants, and how

system developers can match their core competencies with

these needs.

There are two issues raised in the manufacture of virtual

products:

1. How to balance economy of scale achieved in vol-

ume manufacturing with special features that

customers are willing to pay for; and

2. How to create diversity while maintaining a level of

quality associated with standard high-volume

production.

Cache Lo gic and FP GAs help th e manufactu rers achie ve

these two require ments of virtual produc ts. A virtual prod-

uct lin e is on e with c harac te ristics whi ch m eet the ne eds o f

a class of cu stomers. An example would be a P C-based

data-ac quisitio n produc t. Such a product has cer tain phy si-

cal requi rements consi stent with a PC-bus card standard.

The boa rd wo uld al so ha ve a series of s tandar d data gath-

erin g feature s suc h as multi ple- channel A-to- D conve rters ,

digital I/O ports, D-to-A converters, and high-speed clock

counters. These features are typically accomplished by

highly integr ated well-designed ICs readily avail able to all

manufactu res. The comple xity of such products is in t he

data path and protocol which connects the PC to the stan-

dard IC products. The structure of this data path is

prejudiced by optimum system performance, cost, and cus-

tomer preference, the key item being customer preference

for a successful virtual product, or for that matter any suc-

cessful product.

The traditional approach to creating a data-acquisition

product, like most products, is to create a board with a

standard bus footprint, use industry standard A-to-D and D-

to-A circuits, and then create a custom data path. The man-

ufactur er then ha s to trust mark eting st udies and insti nct to

determine the best data path approach. It is possible to

hedge the bet by addi ng r edu nda ncy. T hi s redu nda ncy has

two detrimental effects: added cost, and added complexity

for the end user. T he select ion of wr ong dat a path pr otocol

or excessive complexity caused by redundancy results in

dissatisfied or nonexistent customers.

A virt ua l prod uct does n ot mea n that a manufac turer w oul d

be able to off er one p roduc t whi c h was all thi ngs to a ll p eo-

ple. The use of programmable logic would allow a

manufacturer to create an extensive catalog of products,

but only have a small number of tangible assemblies to tool

for manufacturing. The manufacturer would use FPGAs

and cache logic FPGAs to create diversity in its product

line. T he co st of di versi ty to t he manu facturer is the cost of

servic e, o r “personalization engineering”, required to create

a niche d es ign on a s tand ar d as semb ly . T he advantage for

the customer is a mass-produced product which meets

their specific needs.

Figure 3. Cache Logic Concept

FPGA

The virtua l produc t appro ach allows a manuf actur er to per-

fect a single assembly. The FPGA’s ability to be configured

for self-test could even enhance the quality of the ass em-

bly. Atmel has developed the IEEE1148 boundary-scan

supermacro. Utilizing the reconfigurable logic capability of

the AT6000 family, the boundary-scan function may be

loade d into the d evice and diagnos tics perform ed, then th e

device can be re configu red for ot her logic functio ns. A sin-

gle Atmel dev ice may be used for tes ti ng an d lo gi c, with no

overhead or speed penalty, as is the case for all other

FPGAs and other ASIC devices.

The result would be an inventory of nearly identic al raw-

produc t assembli es, which thr ough virtu al design bec omes

a catalog full of products when shipped to the customer.

With a solid design, most customer problems can be traced

to the virtual-design personalization process, and be

repaired in the field with FPGA configuration updates. It is

also possible to introduce new features into virtual products

as soon as they are invented and proven, rather than wait

until a new hardware product is designed, tooled, and

manufactured.

Cache Logic Benefits

There are several benefits derived from cache logic design:

•New functionality may be added to existing hardware,

without having to make modifications to the board.

•The hardware may be tailored to the application,

resulting in higher system performance across a broad

range of applications.

•The FPGA densi ty li mit ati ons are elimi nate d.

•Overall system reliability is improved by reducing the

number of physical products manufactured and utilizing

boundary scan macros for manufacturing and system

testing.

Overall produc t life cycle c osts are s ignifica ntly reduced by

using reusable software and hardware:

•Lower development costs

•Lower inventory costs

•Quicker time to market

•Fewer parts on the board

•Lower power consumption

•Lower total system cost

•Reusable designs

Summary

To many people, the i deal of ad aptive hardwa re or virtua l

products is a futuristic concept. The AT6000 family is capa-

ble of impl ementi ng cache l ogic a nd virtua l produc ts today .

The Atmel FPGA and its abilities to implement cache logic

make it a foundation for adaptive hardware and virtual

products. Successful design with this new technology has

been co mmercial ly demonstr ated. Tod ay’s des ign meth od-

ology, that r equires a new product for eac h new f unction ,

will be repl aced by adaptive ha rdware products that meet

the needs of both customers and suppliers with customized

products and improved quality, while reducing product

development time and overall life cycle costs.

Examples of Cache Logic Applications

Power and Space-se nsit ive Applic atio ns Compute Intensiv e Applica tions

Portable Computers

Battery-Operated Instrumentation

Portable Communications

Portable Medical Equipment

Computer Graphics

Image Processing

Data Compression

Speech Recognition

Pattern Recognition

Reprogrammable Hardware Application Acceleration

Test Equipment

Industrial Control

Instrumentation

Special-purpose Computers

Connectors

CAD

Database

Spreadsheet

Multimedia

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