IRDC3811 - International Rectifier

IRDC3811

Rev 0.1

01/07/2008 1

USER GUIDE FOR IR3811 EVALUATION BOARD

DESCRIPTION

The IR3811 is a synchronous buck

converter, providing a compact, high

performance and flexible solution in a small

5mmx6mm Power QFN package.

Key features offered by the IR3811 include,

tracking capability for memory application,

programmable soft-start ramp, precision

0.6V reference voltage, thermal protection,

fixed 600kHz switching frequency requiring

no external component, input under-voltage

lockout for proper start-up, and pre-bias

start-up.

An output over-current protection function is

implemented by sensing the voltage developed

across the on-resistance of the synchronous

rectifier MOSFET for optimum cost and

performance.

This user guide contains the schematic and bill

of materials for the IR3811 evaluation board.

The guide describes operation and use of the

evaluation board itself. Detailed application

information for IR3811 is available in the

IR3811 data sheet.

BOARD FEATURES

•Vin = +12V (13.2V Max)

•Tracking Input

•Vout = 0.75V @ 0- 7A Vp:0.6V

•L= 0.6uH

•Cin= 3x10uF (ceramic 1206) + 330uF (electrolytic)

•Cout= 6x22uF (ceramic 0805)

SupIRBuckTM

IRDC3811

Rev 0.1

01/07/2008 2

A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 7A load should be

connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the

board are listed in Table I.

IR3811 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). These inputs are

connected on the board with a zero ohm resistor (R15). Separate supplies can be applied to these inputs.

Vcc input cannot be connected unless R15 is removed. Vcc input should be a well regulated 5V-12V supply

and it would be connected to Vcc+ and Vcc-.

Vp pin is connected to the internal reference (Vref) via R14 as the default configuration. External input can

be applied to Vp. For tacking applications, R14 should be removed, R17 should be inserted, and the

external tracking source should be applied between Vp_Ext and Agnd. The value of R17 and R28 can be

selected to provide the desired ratio between the output voltage and the tracking input. For proper operation

of IR3811, the voltage at Vp pin should be kept between 0.2V to 1.0V.

CONNECTIONS and OPERATING INSTRUCTIONS

LAYOUT

The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3811 SupIRBuck and all of the

passive components are mounted on the top side of the board.

Power supply decoupling capacitors, the charge-pump capacitor and feedback components are located

close to IR3811. The feedback resistors are connected to the output voltage at the point of regulation

and are located close to the SupIRBuck.

To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground

current path.

Table I. Connections

Analog (Signal) GroundAgnd

Ground for optional Vcc inputVcc-

Optional Vcc inputVcc+

Vout (+1.8V)VOUT+

Optional Tracking inputVp_Ext

Ground of Vout

VOUT-

Ground of Vin

VIN-

Vin (+12V)VIN+

Signal NameConnection

IRDC3811

Rev 0.1

01/07/2008 3

Fig. 1: Connection diagram of IR3811 evaluation board

Vin= +12v GROUND

Connection Diagram

Vp_Ext

GROUND

Agnd

VOUT

GROUND

VCC+

IRDC3811

Rev 0.1

01/07/2008 4

Fig. 2: Board layout, top overlay

Fig. 3: Board layout, bottom overlay (rear view)

IRDC3811

Rev 0.1

01/07/2008 5

Fig. 4: Board layout, mid-layer I

Fig. 5: Board layout, mid-layer II

Single point

connection

between AGND

and PGND.

AGND

Plain

PGND

Plain

IRDC3811

Rev 0.1

01/07/2008 6

Fig. 6: Schematic of the IR3811 evaluation board

Single point of connection between Power

Ground and Signal ( “analog” ) Ground

Vout-

C21

N/S

C22

N/S

Vin

C14

0.1uF

Vcc-

C10

0.1uF

PGND

C12

0.1uF

0.6u

1 2

C24

560pF

C23

N/S

BAT54S

C26

2200pF

C13

1uF

Vout

Vcc+

10uF

N/S

8.66K

R10

N/S

10uF

226K

4.32K

56.2K

10uF

C15

22uF

C16

22uF

C25

0.1uF

C17

22uF

R12

6.98k

Open

C18

22uF

C19

22uF

C20

22uF

C27

0.01uF

N/S

R18

N/S

330uF

VCC

180pF

0.1uF

R15

Agnd

Vin+

Vin-

Vout+

Vout-

IR3811

Vc 14

Hg 13

AGnd3

AGnd2

SW 11

Vref

COMP

OCset

7PGnd 10

AGnd1

Vcc

Vin 12

R17

N/S

Vp_Ext

C11

39pF

N/S

VCC

Vin+

Vin-

R14

R28

N/S

Vout+

IRDC3811

Rev 0.1

01/07/2008 7

Item Quantity Designator Value Description Size Manufacturer Mfr. Part Number

1 1 C1 330uF SMD Electrolytic, 25V, 20% SMD Panasonic EEV-FK1E331P

2 3 C2 C3 C4 10uF Ceramic, 16V, X7R, 10% 1206 Panasonic ECJ-3YX1C106K

35 C7 C10 C12

C14 C25 0.1uF Ceramic, 50V, X7R, 10% 0603 Panasonic ECJ-1VB1H104K

4 1 C27 0.01uF Ceramic, 16V, X7R, 10% 0603 Panasonic ECJ-1VB1C103K

5 1 C8 180pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H181JA01

6 1 C11 39pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H390JA01

7 1 C13 1uF Ceramic, 16V, X5R, 10% 0603 Panasonic ECJ-1VB1C105K

86 C15 C16 C17

C18 C19 C20 22uF Ceramic, 6.3V, X5R, 20% 0805 Panasonic ECJ-2FB0J226M

9 1 C24 560pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H561JA01

10 1 C26 2200pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H222JA01

11 1 D1 BAT54S Diode Schottky ,40V,

200mA SOT-23 Fairchild BAT54S

12 1 L1 0.6uH SMT Inductor, 1.7mOhm,

20%

11.5x

10mm Delta MPL104-0R6

13 1 R1 8.66K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06038K66FKEA

14 1 R3 226K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW0603226KFKEA

15 1 R2 56.2K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060356K2FKEA

16 1 R4 4.32K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06034K32FKEA

17 1 R6 20 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW060320R0FKEA

18 3 R9 R14 R15 0 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06030000Z0EA

19 1 R12 6.98K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06036K98FKEA

20 1 U1 IR3811 600kHz, 7A, SupIRBuck

Module 5x6mm International

Rectifier IR3811

21 2 - - Banana Jack, Insulated

Solder Terminal, Black -Johnson

Components 105-0853-001

22 1 - - Banana Jack- Insulated

Solder Terminal, Red -Johnson

Components 105-0852-001

23 1 - - Banana Jack- Insulated

Solder Terminal, Green -Johnson

Components 105-0854-001

Bill of Materials

IRDC3811

Rev 0.1

01/07/2008 8

Fig. 10: Output Voltage Ripple, 7A load,

Vp:0.6V, Ch1: Vout ,Ch4: Iout

Fig. 11: Inductor node at 7A load, Vp:0.6V,

Ch2:LX, Ch4:Iout

Fig. 12: Short (Hiccup) Recovery, Vp:0.6V

Ch2:VSS , Ch3:Vout

Fig. 9: Pre-Bias Start up, 0A Load, Vp:0.6V

Ch1:Vin, Ch2:VSS, Ch3:Vout

Fig. 7: Start up at 7A Load, Vp: 0.6V

Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:Iout

Fig. 8: Tracking Operation Vp: 0- 0.6V , 7A Load

Ch1:Vin, Ch2:Vp, Ch3:Vout, Ch4:Vss

TYPICAL OPERATING WAVEFORMS

Vin=Vcc=12.0V, Vp=0- 0.6V, Vo=0.75V, Io=0- 7A, Room Temperature, No Air Flow

IRDC3811

Rev 0.1

01/07/2008 9

TYPICAL OPERATING WAVEFORMS

Vin=Vcc=12V, Vo=0.75V, Io=3.5A-7A, Room Temperature, No Air Flow

Fig. 13: Transient Response, 3.5A to 7A step

Ch3:Vout, Ch4:Iout

IRDC3811

Rev 0.1

01/07/2008 10

TYPICAL OPERATING WAVEFORMS

Vin=Vcc=12V, Vo=0.75V, Io=7A, Room Temperature, No Air Flow

Fig. 14: Bode Plot at 7A load shows a bandwidth of 44kHz and phase margin of 50 degrees

IRDC3811

Rev 0.1

01/07/2008 11

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

01234567

Load Current (A)

Power Loss (W)

Power Loss Vin=Vcc=12V Power Loss Vin=12V @ Vcc=5V

0.5 1.5 2.5 3.5 4.5 5.5 6.5

Load Current (A)

Efficiency (%)

Efficiency Vin=Vcc=12V Efficiency Vin=12V @ Vcc=5V

Fig.16: Power loss versus load current

Fig.15: Efficiency versus load current

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vo=0.75V, Io=0- 7A, Room Temperature, No Air Flow

IRDC3811

Rev 0.1

01/07/2008 12

THERMAL IMAGES

Vin=Vcc=12V, Vo=0.75V, Io=7A, Room Temperature, No Air Flow

Fig. 17: Thermal Image at 7A load

Test point 1 is the IR3811

IRDC3811

Rev 0.1

01/07/2008

PCB Metal and Components Placement

The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum

lead to lead spacing should be ≥0.2mm to minimize shorting.

Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The

outboard extension ensures a large and inspectable toe fillet.

The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to

maximum part pad length and width. However, the minimum metal to metal spacing should be no less

than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz.

Copper.

IRDC3811

Rev 0.1

01/07/2008

Solder Resist

It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist

should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD

pads.

The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist

onto the copper of 0.05mm to accommodate solder resist mis-alignment.

Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to the

high aspect ratio of the solder resist strip separating the lead lands from the pad land.

IRDC3811

Rev 0.1

01/07/2008

Stencil Design

• The Stencil apertures for the lead lands should be approximately 80% of the area of the

lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead

shorts. If too much solder is deposited on the center pad the part will float and the lead

lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to the

solder resist opening minus an annular 0.2mm pull back to decrease the incidence of

shorting the center land to the lead lands when the part is pushed into the solder paste.

IRDC3811

Rev 0.1

01/07/2008

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

This product has been designed and qualified for the Consumer market.

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 11/07