IRF520 - Intersil Corporation

4-172

File Number 1574.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

IRF520

9.2A, 100V, 0.270 Ohm, N-Channel

Power MOSFET

This N-Channel enhancement mode silicon gate power ﬁeld

effect transistor is an advanced power MOSFET designed,

tested, and guaranteed to withstand a speciﬁed level of

energy in the breakdown avalanche mode of operation. All of

these power MOSFETs are designed for applications such

as switching regulators, switching convertors, motor drivers,

relay drivers, and drivers for high power bipolar switching

transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated

circuits.

Formerly developmental type TA09594.

Features

• 9.2A, 100V

•r

DS(ON) = 0.270Ω

• SOA is Power Dissipation Limited

• Single Pulse Avalanche Energy Rated

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB

Ordering Information

PART NUMBER PACKAGE BRAND

IRF520 TO-220AB IRF520

NOTE: When ordering, use the entire part number. G

SOURCE

DRAIN (FLANGE)

DRAIN

GATE

Data Sheet November 1999

4-173

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed

IRF520 UNITS

Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 100 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

TC= 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

D9.2

6.5 A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 37 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD60 W

Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 36 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 100 - - V

Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current IDSS VDS = 95V, VGS = 0V - - 250 µA

VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ= 150oC - - 1000 µA

On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) 9.2 - - A

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

Drain to Source On Resistance (Note 2) rDS(ON) ID = 5.6A, VGS = 10V (Figure 8, 9) - 0.25 0.27 Ω

Forward Transconductance (Note 2) gfs VDS ≥ 50V, ID = 5.6A (Figure 12) 2.7 4.1 - S

Turn-On Delay Time td(ON) VDD = 50V, ID≈ 9.2A, RG = 18Ω, RL = 5.5Ω

MOSFET Switching Times are Essentially

Independent of Operating

Temperature

- 9 13 ns

Rise Time tr-3063ns

Turn-Off Delay Time td(OFF) -1870ns

Fall Time tf-2059ns

Total Gate Charge

(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 9.2A, VDS = 0.8 x Rated BVDSS,

Ig(REF) = 1.5mA (Figure 14) Gate Charge is

Essentially Independent of Operating

Temperature

-1030nC

Gate to Source Charge Qgs - 2.5 - nC

Gate to Drain “Miller” Charge Qgd - 2.5 - nC

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz

(Figure 11) - 350 - pF

Output Capacitance COSS - 130 - pF

Reverse Transfer Capacitance CRSS -25- pF

Internal Drain Inductance LDMeasured From the Contact

Screw On Tab To Center of

Die

Modified MOSFET

Symbol Showing the

Internal Devices

Inductances

- 3.5 - nH

Measured From the Drain

Lead, 6mm (0.25in) From

Package to Center of Die

- 4.5 - nH

Internal Source Inductance LSMeasured From the Source

Lead, 6mm (0.25in) From

Header to Source Bonding

Pad

- 7.5 - nH

Thermal Resistance Junction to Case RθJC - - 2.5 oC/W

Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 80 oC/W

IRF520

4-174

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET Symbol

Showing the Integral

Reverse P-N Junction Diode

- - 9.2 A

Pulse Source to Drain Current (Note 3) ISDM - - 37 A

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 9.2A, VGS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time trr TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs 5.5 100 240 ns

Reverse Recovered Charge QRR TJ = 25oC, ISD = 9.2A, dISD/dt = 100A/µs 0.17 0.5 1.1 µC

NOTES:

2. Pulse test: pulse width ≤300µs, duty cycle ≤2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 25V, starting TJ = 25oC, L = 640mH, RG = 25Ω, peak IAS = 9.2A.

Typical Performance Curves Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC, CASE TEMPERATURE (oC)

25 50 75 100 125 150 175

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

TC, CASE TEMPERATURE (oC)

50 75 100 17525

ID, DRAIN CURRENT (A)

125 150

ZθJC, TRANSIENT

0.1

0.01 10-2

10-5 10-4 10-3 0.1 1 10

t1, RECTANGULAR PULSE DURATION (s)

PDM

t1t2

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ= PDM x ZθJC + TC

SINGLE PULSE

0.5

0.02

0.05

0.2

0.01

0.1

THERMAL IMPEDANCE (oC/W)

IRF520

4-175

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

100

10001 10 100

0.1

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

TC = 25oC

TJ= MAX RATED

SINGLE PULSE

10µs

100µs

1ms

10ms

OPERATION IN THIS

AREA IS LIMITED

BY rDS(ON)

10V

VDS, DRAIN TO SOURCE VOLTAGE (V)

20050

ID, DRAIN CURRENT (A)

VGS = 7V

VGS = 6V

VGS = 8V PULSE DURATION = 80µs

10 40

VGS = 5V

VGS = 4V

DUTY CYCLE = 0.5% MAX

123405

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

VGS = 5V

VGS = 4V

VGS = 7V

VGS = 8V

VGS = 10V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

102

0.1 24680

ID(ON), ON-STATE DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

175oC25oC

VDS ≥ 50V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

ID, DRAIN CURRENT (A)

16 32040

2.5

2.0

1.5

1.0

rDS(ON), DRAIN TO SOURCE ON RESISTANCE

PULSE DURATION = 80µs

824

0.5

VGS = 10V

VGS = 20V

DUTY CYCLE = 0.5% MAX

3.0

1.8

0.6

060-60 TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED ON RESISTANCE

2.4

1.2

0-40 -20 20 40 80 100 140120 160 180

ID = 9.2A, VGS = 10V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

IRF520

4-176

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

1.25

1.05

0.85

0 180

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

1.15

0.95

0.75-60

BREAKDOWN VOLTAGE

60 120

ID = 250µA

VDS, DRAIN TO SOURCE VOLTAGE (V)

C, CAPACITANCE (pF)

1000

800

600

400

200

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

110 102

CISS

COSS

CRSS

ID, DRAIN CURRENT (A)

36912015

gfs, TRANSCONDUCTANCE (S)

TJ = 175oC

TJ = 25oC

PULSE DURATION = 80µs

VDS ≥50

DUTY CYCLE = 0.5% MAX

TJ = 175oC

ISD, SOURCE TO DRAIN CURRENT (A)

VSD, SOURCE TO DRAIN VOLTAGE (V)

100

0.1 0 0.4 1.2 1.6 2.00.8

TJ = 25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

Qg, GATE CHARGE (nC)

36912015

VGS, GATE TO SOURCE VOLTAGE (V)

ID = 9.2A

VDS = 20V

VDS = 50V

VDS = 80V

IRF520

4-177

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS

DUT

-VDD

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0.3µF

12V

BATTERY 50kΩ

VDS

DUT

Ig(REF)

(ISOLATED

VDS

0.2µF

CURRENT

REGULATOR

ID CURRENT

SAMPLING

IG CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPE

AS DUT Qg(TOT)

Qgd

Qgs

VDS

VGS

VDD

IG(REF)

IRF520

4-178

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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IRF520