FN6013.3

Four-Channel Programmable Digital

The ISL5216 Quad Programma ble Digital Downconverter

(QPDC) is designed for high dynamic range applications

such as cellular basestations where multiple channel

digitized IF samples which are mixed with local quadrature

mixers are filtered with a CIC and FIR filters, with a variety of

decimation options. Gain adjustment is provided on the

filtered signal. The digital AGC provides a gain adjust range

A cartesian to polar coordinate converter provides

• Four Independently Programmable Downconverter

Channels in a single package

• Four Parallel 17-Bit Inputs providing 16-bit fixed or one of

• Cascadable Filtering for Additional Bandwidth

• Four Independent Seria l Outputs

• 2.5V Core, 3.3V I/O Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Narrow-Band TDMA through IS-95 CDMA Digital Software

Radio and Basestation Receivers

• Wide-Band Applications: W-CDMA and UMTS Digital

Software Radio and Basestation Receivers

Ordering Information

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Block Diagram

C(15:0), Cm1 I Parallel Data Input bus C. Sampled on the rising edge of clock when ENIC is active (low). Cm1 has internal

weak pull-down.

response to SYNCI is programmable and can be enabled or disabled. This signal is connected to all four

channels and is included for backward compatibility with HSP50216 designs.

is internally pulled low to allow it to be left unconnected.

is internally pulled low to allow it to be left unconnected.

is internally pulled low to allow it to be left unconnected.

is internally pulled low to allow it to be left unconnected.

polarity of SCLK is programmable.

The polarity and position of SYNCA is programmable.

The polarity and position of SYNCB is programmable.

(low). When the μP MODE control is high this input functions as a data read/write strobe. In this mode with

Pin Descriptions (Continued)

four channels are independently programmable. Four 17-bit

parallel data input busses (A(15:-1), B(15:-1), C(15:-1) and

D(15:-1)) and four pairs of serial data outputs (SDxA, SDxB,

SDxC, and SDxD; x = 1 or 2) are provided. Each input can

be connected to any or all of the internal signal processing

between channels for cascading back-end filters or for

filtering or systolic arrays (to provide wider bandwidth

level on any of the parallel data input busses, facilitating

a quadrature numerically controlled oscillator (NCO), digital

Each channel back end section includes an FIR processing

block, an AGC and a cartesian-to-polar coordinate

converter. The F IR pro cessing block is a flexible filter

compute engine that can compute a single FIR or a set of

single filter in a chain can have up to 256 taps and the total

number of taps in a set of filters can be up to 384 provided

resampler. The AGC section can provide up to 96dB of

either fixed or automatic gain control. For automatic gain

control, two settling modes and two sets of loop gains are

cartesian-to-polar coordinate conversion block, used by the

AGC loop, are also provided as outputs to the user for AM

The ISL5216 supports both fixed and floating poin t parallel

Pin Descriptions (Continued)

X(2:0) = 010 12 X15 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0

X(2:0) = 011 18 X15 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 0 0

X(2:0) = 100

4. Or 101, 110, or 111, the exponent input saturates at 100.

5. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0, 0, 0 and 1 respectively.

13-BIT MODE: 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 18dB EXPONENT RANGE (Note 7)

6. Or 100, 101, 110, or 111, the exponent input saturates at 011.

7. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 0, 0, 1 and 0 respectively.

9. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 0, 1 and 1 respectively.

11, 12, 13-BIT MODE: 11, 12, 13-B IT MANTISSA, 3-BIT EXPONENT (-1,1,0) (Note 10), 42dB MAXIMUM EXPONENT RANGE (Note 11)

Halfband

Compute one output

Memory block start at 0

Coefficient block start at 18

Output to step 2

Type = even symme try

Output to AGC

CLOCK

CYCLES FUNCTION PERFORMED

15 30 tap symmetric FIR, 2 taps per clock

Each channel decimates down to 2.048M and then the

channels are multiplexed together in the output formatter to

minus (8 writes + 1 wait + 1 jump = 10 clocks)

22 x 2 = 44 taps.

Multiplexing the four outputs gives a final output sample rate

The impulse response is 44 taps at 16.384M or 22 output

samples (11 symbols at 4.096M).

control the forward AGC gain control of all four channels.

and several control registers. These are describ ed below.

sequencer supporting up to 32 steps. Each step can be a

(conditional or unconditional), load loop counter, or NOP.

data routing controls. Not all of the instruction word bits are

When the filter is reset, the instruction pointer is set to 31

initialized on reset, so a reset must be done when the

A fixed offset can be added to the starting read address of

all filters in the bank will write the same data to the same

instruction sequence step number (0–31 decimal). Note the

(IWA = *0 0Ah) must be set for the microprocessor to read

STEP INSTRUCTION

0 Wait for enough input samples (8 in this case)

2 Jump, Unconditional, to 0

Instruction Bit Fields INSTRUCTION BIT FIELDS

106:105 Clocks Per

119:118 Data Memory

122:120 Coefficient Memory

BIT

Basic Instruc ti on Set Examples

8:0 = 001

8:0 = 1JJJJJ111b

127:9 = 0

is routed through path A with the AGC enabled.

127:126 Reserved Set to 0

BIT

1 - FIR

2 - JUMP TO STEP 0

Wait Preload Register

threshold and two wait counter decreme nt values. Each is

count is greater than or equal to the threshold. The wait

AGC error detector, the AGC error scaler and into the AGC

multiplier and shifters, completing the AGC control loop.

N = 15. The mantissa provides up to an additional 6.02dB of

mantissa interpreted as an unsigned integer ranging from 0

UNSIGNED †

The full AGC range of the multiplier/shifter is from 0dB to

settling mode and SNR). This effectively eliminates AM

ranges from 0 to 2.329, where the maximum output is

error scaling, and an AGC loop filter. The error detector

subtracts the magnitude output of the coordinate converter

to 1.64676 times the desired magnitude of the I1/Q1 output.

register *010h). Each set has both an attack and a decay

gain. This allows asymmetric adjustment for appl ications

these applications, the gains would be set for fast attack and

the signal turns on, but incre ases the gain slowly when the

signal turns off (in anticipation of it turning back on shortly).

the same value, or set the limits to minimum and maximum

gains and set the AGC attack and decay loop gains to zero.

where M LG is a 4-bit binary mantissa value ranging from 0

to 15, and E LG is a 4-bit binary exponent value ranging from

2.18344. The scaled gain error can range (depending on

per sample” range of 0 to 3.275dB/sample.

The PDC provides for the storing of two values of AGC attack

loop gain by simply setting IWA register *013h bits 9 and 10

The AGC loop filter consists of an accumulator with a built in

the following the equation:

where m is a 12-bit mantissa value between 0 and 4095, and