MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 280 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.1 µA
DFive Power Saving Modes
DWake-Up From Standby Mode in Less
Than 6 µs
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
D16-Bit Timer_B With Three or Seven
Capture/Compare-With-Shadow Registers
D16-Bit Timer_A With Three
Capture/Compare Registers
DOn-Chip Comparator
DSerial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)
− One USART (USART0)
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DIntegrated LCD Driver for up to
160 Segments
DBootstrap Loader
DFamily Members Include:
− MSP430F435, MSP430F4351§:
16KB+256B Flash Memory,
512B RAM
− MSP430F436, MSP430F4361§:
24KB+256B Flash Memory,
1KB RAM
− MSP430F437, MSP430F4371§:
32KB+256B Flash Memory,
1KB RAM
− MSP430F447:
32KB+256B Flash Memory,
1KB RAM
− MSP430F448, MSP430F4481§:
48KB+256B Flash Memory,
2KB RAM
− MSP430F449, MSP430F4491§:
60KB+256B Flash Memory,
2KB RAM
DFor Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
MSP430F43x, and MSP430F43x1 devices
MSP430F44x, and MSP430F44x1 devices
§The MSP430F43x1 and MSP430F44x1 devices are identical to
the MSP430F43x and MSP430F44x devices, respectively − with
the exception that the ADC12 module is not implemented.
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 µs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2009, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The MSP430x43x(1) and the MSP430x44x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 and MSP430F44x1 devices), one
or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid
crystal driver (LCD) with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TAPLASTIC 80-PIN QFP
(PN)
PLASTIC 100-PIN QFP
(PZ)
−40°C to 85°C
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
MSP430F4481IPZ
MSP430F4491IPZ
For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
MSP-FET430UIF (USB)
MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
MSP-FET430U100 (PZ package)
DStand-Alone Target Board
MSP-TS430PZ100 (PZ package)
DProduction Programmer
MSP-GANG430
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
22 23
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
25 26 27 28
PN PACKAGE
(TOP VIEW)
TDO/TDI
79 78 77 76 7580 74
P6.1
P6.0
RST/NMI
TCK
TMS
P2.6/CAOUT/S19
S21
S15
S16
S17
72 71 7073
29 30 31 32 33
69 68
21
P4.0/S9
XT2OUT
67 66 65 64
34 35 36 37
S22
S23
P3.7/S24
P3.6/S25
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P3.5/S26
P3.4/S27
38 39 40
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
63 62 61
TDI/TCLK
XT2IN
P1.6/CA0
S10
S20
P3.3/UCLK0/S28
S11
S12
S13
S14
P2.7/S18
P6.2
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
SS1
DV
CC
AV
SS
AV
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1
P6.0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S19
S22
S23
S33
S32
P4.5/S36
P4.4/S37
P4.3/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
22 23
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
25 26 27 28
PN PACKAGE
(TOP VIEW)
TDO/TDI
79 78 77 76 7580 74
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
P2.6/CAOUT/S19
S21
S15
S16
S17
72 71 7073
29 30 31 32 33
69 68
21
P4.0/S9
XT2OUT
67 66 65 64
34 35 36 37
S22
S23
P3.7/S24
P3.6/S25
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P3.5/S26
P3.4/S27
38 39 40
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
63 62 61
TDI/TCLK
XT2IN
P1.6/CA0
S10
S20
P3.3/UCLK0/S28
S11
S12
S13
S14
P2.7/ADC12CLK/S18
P6.2/A2
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
SS1
DV
CC
AV
SS
AV
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1/A1
P6.0/A0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2/A2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S19
S22
S23
S33
S32
P4.5/S36
P4.4/S37
P4.3/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x4481IPZ, MSP430x4491IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1
P6.0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
S19
S22
S23
S33
S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F4481IPZ
MSP430F4491IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1/A1
P6.0/A0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2/A2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
S19
S22
S23
S33
S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x1 functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
32KB
24KB
16KB
RAM
1KB
512B
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B3
3 CC Reg
Shadow
Reg
USART0
UART Mode
SPI Mode
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
MSP430x43x functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
32KB
24KB
16KB
RAM
1KB
512B
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B3
3 CC Reg
Shadow
Reg
USART0
UART Mode
SPI Mode
XT2IN
XT2OUT
ADC12
12-Bit
8 Channels
<10µs Conv.
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x44x1 functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
60KB
48KB
RAM
2KB
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B7
7 CC Reg
Shadow
Reg
USART0
USART1
UART Mode
SPI Mode
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Hardware
Multiplier
MPY, MPYS
MAC,MACS
MSP430x44x functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
60KB
48KB
32KB
RAM
2KB
1KB
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B7
7 CC Reg
Shadow
Reg
USART0
USART1
UART Mode
SPI Mode
XT2IN
XT2OUT
ADC12
12-Bit
8 Channels
<10µs Conv.
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Hardware
Multiplier
MPY, MPYS
MAC,MACS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
DVCC1 1 DVCC1 1Digital supply voltage, positive terminal.
P6.3 2 I/O P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / input to brownout, supply voltage
supervisor
Reserved 7 Reserved 7 Reserved, do not connect externally
XIN 8 I XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
DVSS 10 I DVSS 10 I Connect to DVSS
DVSS 11 I DVSS 11 IConnect to DVSS
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/S18 30 I/O S18 30 O General-purpose digital I/O / LCD segment output 18
P2.6/CAOUT/S19 31 I/O S19 31 O General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29 41 I/O S29 41 O General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30 42 I/O S30 42 O General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31 43 I/O S31 43 O General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23 50 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33 51 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2 52 DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 53 DVSS2 61 Digital supply voltage, negative terminal.
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7 72 I/O General-purpose digital I/O
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 62 I/O P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 63 I/O P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 64 I/O P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1 65 I/O P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 67 I/O P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI 70 I/O TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK 71 I TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming
and test.
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0 75 I/O P6.0 95 I/O General-purpose digital I/O
P6.1 76 I/O P6.1 96 I/O General-purpose digital I/O
P6.2 77 I/O P6.2 97 I/O General-purpose digital I/O
AVSS 78 AVSS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1 79 DVSS1 99 Digital supply voltage, negative terminal.
AVCC 80 AVCC 100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
must not power up prior to DVCC1/DVCC2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x Terminal Functions
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
DVCC1 1 DVCC1 1Digital supply voltage, positive terminal.
P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5 4 I/O P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6 5 I/O P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN 6 I/O P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7—12-bit ADC, analog /
input to brownout, supply voltage supervisor
VREF+ 7 O VREF+ 7 O Output of positive terminal of the reference voltage in the ADC
XIN 8 I XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
VeREF+ 10 I VeREF+ 10 I Input for an external reference voltage to the ADC
VREF−/VeREF− 11 I VREF−/VeREF− 11 INegative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/ADC12CLK/
S18
30 I/O S18 30 O General-purpose digital I/O / conversion clock—12-bit ADC / LCD
segment output 18
P2.6/CAOUT/S19 31 I/O S19 31 O General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29 41 I/O S29 41 O General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30 42 I/O S30 42 O General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31 43 I/O S31 43 O General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23 50 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33 51 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2 52 DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 53 DVSS2 61 Digital supply voltage, negative terminal.
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 62 I/O P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 63 I/O P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 64 I/O P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1 65 I/O P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 67 I/O P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI 70 I/O TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK 71 I TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming
and test.
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0/A0 75 I/O P6.0/A0 95 I/O General-purpose digital I/O / analog input a0 − 12-bit ADC
P6.1/A1 76 I/O P6.1/A1 96 I/O General-purpose digital I/O / analog input a1 − 12-bit ADC
P6.2/A2 77 I/O P6.2/A2 97 I/O General-purpose digital I/O / analog input a2 − 12-bit ADC
AVSS 78 AVSS 98
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry.
DVSS1 79 DVSS1 99 Digital supply voltage, negative terminal.
AVCC 80 AVCC 100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry; must not power up prior to DVCC1/DVCC2.