MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 280 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.1 µA
DFive Power Saving Modes
DWake-Up From Standby Mode in Less
Than 6 µs
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
D16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
D16-Bit Timer_A With Three
Capture/Compare Registers
DOn-Chip Comparator
DSerial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)†
− One USART (USART0)‡
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DIntegrated LCD Driver for up to
160 Segments
DBootstrap Loader
DFamily Members Include:
− MSP430F435, MSP430F4351§:
16KB+256B Flash Memory,
512B RAM
− MSP430F436, MSP430F4361§:
24KB+256B Flash Memory,
1KB RAM
− MSP430F437, MSP430F4371§:
32KB+256B Flash Memory,
1KB RAM
− MSP430F447:
32KB+256B Flash Memory,
1KB RAM
− MSP430F448, MSP430F4481§:
48KB+256B Flash Memory,
2KB RAM
− MSP430F449, MSP430F4491§:
60KB+256B Flash Memory,
2KB RAM
DFor Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
†MSP430F43x, and MSP430F43x1 devices
‡MSP430F44x, and MSP430F44x1 devices
§The MSP430F43x1 and MSP430F44x1 devices are identical to
the MSP430F43x and MSP430F44x devices, respectively − with
the exception that the ADC12 module is not implemented.
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 µs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2009, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The MSP430x43x(1) and the MSP430x44x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 and MSP430F44x1 devices), one
or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid
crystal driver (LCD) with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TAPLASTIC 80-PIN QFP
(PN)
PLASTIC 100-PIN QFP
(PZ)
−40°C to 85°C
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
MSP430F4481IPZ
MSP430F4491IPZ
†For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
− MSP-FET430UIF (USB)
− MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
− MSP-FET430U100 (PZ package)
DStand-Alone Target Board
− MSP-TS430PZ100 (PZ package)
DProduction Programmer
− MSP-GANG430
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
22 23
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
25 26 27 28
PN PACKAGE
(TOP VIEW)
TDO/TDI
79 78 77 76 7580 74
P6.1
P6.0
RST/NMI
TCK
TMS
P2.6/CAOUT/S19
S21
S15
S16
S17
72 71 7073
29 30 31 32 33
69 68
21
P4.0/S9
XT2OUT
67 66 65 64
34 35 36 37
S22
S23
P3.7/S24
P3.6/S25
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P3.5/S26
P3.4/S27
38 39 40
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
63 62 61
TDI/TCLK
XT2IN
P1.6/CA0
S10
S20
P3.3/UCLK0/S28
S11
S12
S13
S14
P2.7/S18
P6.2
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
SS1
DV
CC
AV
SS
AV
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1
P6.0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S19
S22
S23
S33
S32
P4.5/S36
P4.4/S37
P4.3/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
22 23
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
25 26 27 28
PN PACKAGE
(TOP VIEW)
TDO/TDI
79 78 77 76 7580 74
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
P2.6/CAOUT/S19
S21
S15
S16
S17
72 71 7073
29 30 31 32 33
69 68
21
P4.0/S9
XT2OUT
67 66 65 64
34 35 36 37
S22
S23
P3.7/S24
P3.6/S25
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P3.5/S26
P3.4/S27
38 39 40
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
63 62 61
TDI/TCLK
XT2IN
P1.6/CA0
S10
S20
P3.3/UCLK0/S28
S11
S12
S13
S14
P2.7/ADC12CLK/S18
P6.2/A2
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
SS1
DV
CC
AV
SS
AV
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1/A1
P6.0/A0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2/A2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S19
S22
S23
S33
S32
P4.5/S36
P4.4/S37
P4.3/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x4481IPZ, MSP430x4491IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1
P6.0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DVSS
DVSS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
S19
S22
S23
S33
S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F4481IPZ
MSP430F4491IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1/A1
P6.0/A0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
S14
S15
S16
S17
S18
S20
S25
S26
S27
S28
S29
S31
P4.7/S34
S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
S21
SS1
DV
P6.2/A2
P1.2/TA1
S24
P4.6/S35
DVCC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
S19
S22
S23
S33
S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37
4.3/SIMO1/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1 functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
32KB
24KB
16KB
RAM
1KB
512B
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B3
3 CC Reg
Shadow
Reg
USART0
UART Mode
SPI Mode
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
MSP430x43x functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
32KB
24KB
16KB
RAM
1KB
512B
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128/160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B3
3 CC Reg
Shadow
Reg
USART0
UART Mode
SPI Mode
XT2IN
XT2OUT
ADC12
12-Bit
8 Channels
<10µs Conv.
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x1 functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
60KB
48KB
RAM
2KB
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B7
7 CC Reg
Shadow
Reg
USART0
USART1
UART Mode
SPI Mode
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Hardware
Multiplier
MPY, MPYS
MAC,MACS
MSP430x44x functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
60KB
48KB
32KB
RAM
2KB
1KB
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
160
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer_B7
7 CC Reg
Shadow
Reg
USART0
USART1
UART Mode
SPI Mode
XT2IN
XT2OUT
ADC12
12-Bit
8 Channels
<10µs Conv.
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Hardware
Multiplier
MPY, MPYS
MAC,MACS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
DVCC1 1 DVCC1 1Digital supply voltage, positive terminal.
P6.3 2 I/O P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / input to brownout, supply voltage
supervisor
Reserved 7 Reserved 7 Reserved, do not connect externally
XIN 8 I XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
DVSS 10 I DVSS 10 I Connect to DVSS
DVSS 11 I DVSS 11 IConnect to DVSS
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/S18 30 I/O S18 30 O General-purpose digital I/O / LCD segment output 18
P2.6/CAOUT/S19 31 I/O S19 31 O General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29 41 I/O S29 41 O General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30 42 I/O S30 42 O General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31 43 I/O S31 43 O General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23 50 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33 51 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2 52 DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 53 DVSS2 61 Digital supply voltage, negative terminal.
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7 72 I/O General-purpose digital I/O
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 62 I/O P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 63 I/O P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 64 I/O P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1 65 I/O P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 67 I/O P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI 70 I/O TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK 71 I TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming
and test.
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0 75 I/O P6.0 95 I/O General-purpose digital I/O
P6.1 76 I/O P6.1 96 I/O General-purpose digital I/O
P6.2 77 I/O P6.2 97 I/O General-purpose digital I/O
AVSS 78 AVSS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
DVSS1 79 DVSS1 99 Digital supply voltage, negative terminal.
AVCC 80 AVCC 100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
must not power up prior to DVCC1/DVCC2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x Terminal Functions
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
DVCC1 1 DVCC1 1Digital supply voltage, positive terminal.
P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5 4 I/O P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6 5 I/O P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN 6 I/O P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7—12-bit ADC, analog /
input to brownout, supply voltage supervisor
VREF+ 7 O VREF+ 7 O Output of positive terminal of the reference voltage in the ADC
XIN 8 I XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
VeREF+ 10 I VeREF+ 10 I Input for an external reference voltage to the ADC
VREF−/VeREF− 11 I VREF−/VeREF− 11 INegative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/ADC12CLK/
S18
30 I/O S18 30 O General-purpose digital I/O / conversion clock—12-bit ADC / LCD
segment output 18
P2.6/CAOUT/S19 31 I/O S19 31 O General-purpose digital I/O / Comparator_A output / LCD segment
output 19
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O S28 40 O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
P3.2/SOMI0/S29 41 I/O S29 41 O General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
P3.1/SIMO0/S30 42 I/O S30 42 O General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
P3.0/STE0/S31 43 I/O S31 43 O General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
P5.6/R23 50 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
P5.7/R33 51 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD
level (V1)
DVCC2 52 DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 53 DVSS2 61 Digital supply voltage, negative terminal.
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
I/O
PZ
I/O
DESCRIPTION
NAME NO. I/O NAME NO. I/O
DESCRIPTION
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 62 I/O P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 63 I/O P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 64 I/O P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
P1.2/TA1 65 I/O P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 67 I/O P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be
connected.
TDO/TDI 70 I/O TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input
terminal
TDI/TCLK 71 I TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming
and test.
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input
port
P6.0/A0 75 I/O P6.0/A0 95 I/O General-purpose digital I/O / analog input a0 − 12-bit ADC
P6.1/A1 76 I/O P6.1/A1 96 I/O General-purpose digital I/O / analog input a1 − 12-bit ADC
P6.2/A2 77 I/O P6.2/A2 97 I/O General-purpose digital I/O / analog input a2 − 12-bit ADC
AVSS 78 AVSS 98
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry.
DVSS1 79 DVSS1 99 Digital supply voltage, negative terminal.
AVCC 80 AVCC 100
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry; must not power up prior to DVCC1/DVCC2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x1 Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
DVCC1 1Digital supply voltage, positive terminal.
P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O General-purpose digital I/O / analog input to brownout, supply voltage supervisor
Reserved 7 O Reserved, do not connect externally
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
DVSS 10 I Connect to DVSS
DVSS 11 IConnect to DVSS
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
S24 36 O LCD segment output 24
S25 37 O LCD segment output 25
S26 38 O LCD segment output 26
S27 39 O LCD segment output 27
S28 40 O LCD segment output 28
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x1 Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
S29 41 O LCD segment output 29
S30 42 O LCD segment output 30
S31 43 O LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36 48 I/O General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37 49 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38 50 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39 51 I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 61 Digital supply voltage, negative terminal.
P4.1/URXD1 62 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7 72 I/O General-purpose digital I/O
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x1 Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 I Reset input or nonmaskable interrupt input port
P6.0 95 I/O General-purpose digital I/O
P6.1 96 I/O General-purpose digital I/O
P6.2 97 I/O General-purpose digital I/O
AVSS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and
LCD resistive divider circuitry.
DVSS1 99 Digital supply voltage, negative terminal.
AVCC 100 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1, and
LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
DVCC1 1Digital supply voltage, positive terminal.
P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7—12-bit ADC / analog input to brownout, supply voltage
supervisor
VREF+ 7 O Output of positive terminal of the reference voltage in the ADC
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VeREF+ 10 I Input for an external reference voltage to the ADC
VREF−/VeREF− 11 INegative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
S24 36 O LCD segment output 24
S25 37 O LCD segment output 25
S26 38 O LCD segment output 26
S27 39 O LCD segment output 27
S28 40 O LCD segment output 28
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
S29 41 O LCD segment output 29
S30 42 O LCD segment output 30
S31 43 O LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36 48 I/O General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37 49 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38 50 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39 51 I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 61 Digital supply voltage, negative terminal.
P4.1/URXD1 62 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN I/O DESCRIPTION
NAME NO.
P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 I Reset input or nonmaskable interrupt input port
P6.0/A0 95 I/O General-purpose digital I/O, analog input a0—12-bit ADC
P6.1/A1 96 I/O General-purpose digital I/O, analog input a1—12-bit ADC
P6.2/A2 97 I/O General-purpose digital I/O, analog input a2—12-bit ADC
AVSS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12,
port 1, and LCD resistive divider circuitry.
DVSS1 99 Digital supply voltage, negative terminal.
AVCC 100 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1,
and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; Table 2 shows the address
modes.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11
R10 + 2−−> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
− ACLK and SMCLK remain active, MCLK is disabled
− FLL+ loop control remains active
DLow-power mode 1 (LPM1)
− CPU is disabled
− FLL+ loop control is disabled
− ACLK and SMCLK remain active, MCLK is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc generator remains enabled
− ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc generator is disabled
− ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
− ACLK is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc generator is disabled
− Crystal oscillator is stopped
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer_B7†TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13
Timer_B7†TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
ADC12 (see Note 4) ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3 TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
USART1 Receive‡URXIFG1 Maskable 0FFE6h 3
USART1 Transmit‡UTXIFG1 Maskable 0FFE4h 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
†’43x(1) uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x(1) uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6
CCIFGs, and TBIFG
‡USART1 is implemented in ’44x(1) only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
4. ADC12 is not implemented in MSP430x43x1 and MSP430x44x1 devices.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
32 1
rw–0 rw–0 rw–0
Address
0h URXIE0 ACCVIE NMIIE
rw–0 rw–0 rw–0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
7654 0
UTXIE1
32 1
rw–0 rw–0
Address
01h URXIE1
rw–0
BTIE
URXIE1: USART1: UART and SPI receive-interrupt enable (MSP430F44x(1) devices only)
UTXIE1: USART1: UART and SPI transmit-interrupt enable (MSP430F44x(1) devices only)
BTIE: Basic timer interrupt enable
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
32 1
rw–0 rw–1 rw–(0)
Address
02h URXIFG0 NMIIFG
rw–1 rw–0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0
UTXIFG1
32 1
rw–1 rw–0
Address
03h URXIFG1
BTIFG
rw
URXIFG1: USART1: UART and SPI receive flag (MSP430F44x(1) devices only)
UTXIFG1: USART1: UART and SPI transmit flag (MSP430F44x(1) devices only)
BTIFG: Basic timer flag
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
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module enable registers 1 and 2
7654 0
UTXE0
32 1
rw–0 rw–0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0
UTXE1
32 1
rw–0 rw–0
Address
05h URXE1
USPIE1
URXE1: USART1: UART mode receive enable (MSP430F44x(1) devices only)
UTXE1: USART1: UART mode transmit enable (MSP430F44x(1) devices only)
USPIE1: USART1: SPI mode transmit and receive enable (MSP430F44x(1) devices only)
rw–0,1:
Legend: rw: Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
rw–(0,1):
memory organization
MSP430F435
MSP430F4351
MSP430F436
MSP430F4361
MSP430F437
MSP430F4371
MSP430F447
MSP430F448
MSP430F4481
MSP430F449
MSP430F4491
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
24KB
0FFFFh − 0FFE0h
0FFFFh − 0A000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
RAM Size 512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
1KB
05FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Memory Programming User’s
Guide, literature number SLAU265.
BSL Function PN Package Pins PZ Package Pins
Data Transmit 67 - P1.0 87 - P1.0
Data Receive 66 - P1.1 86 - P1.1
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
w/ Interrupt Vectors
Segment 1
Segment 2
Segment n-1
Segment n
Segment A
Segment B
Main
Memory
Information
Memory
24KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
16KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
60KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0A400h
0A3FFh
0A200h
0A1FFh
0A000h
010FFh
01080h
0107Fh
01000h
0C400h
0C3FFh
0C200h
0C1FFh
0C000h
010FFh
01080h
0107Fh
01000h
08400h
083FFh
08200h
081FFh
08000h
010FFh
01080h
0107Fh
01000h
04400h
043FFh
04200h
041FFh
04000h
010FFh
01080h
0107Fh
01000h
01400h
013FFh
01200h
011FFh
01100h
010FFh
01080h
0107Fh
01000h
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system in the MSP430x43x(1) and MSP43x44x(1) family of devices is supported by the FLL+ module,
which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO),
and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both
low system cost and low power consumption. The FLL+ features a digital frequency-locked loop (FLL) hardware
that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the
watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs.
The FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
hardware multiplier (MSP430x44x(1) only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
watchdog timer (WDT)
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
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30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
USART0
The MSP430x43x(1) and the MSP430x44x(1) have one hardware universal synchronous/asynchronous
receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x44x(1) only)
The MSP430x44x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER DEVICE INPUT MODULE INPUT MODULE MODULE
OUTPUT
OUTPUT PIN NUMBER
PN PZ
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK OUTPUT
SIGNAL PN PZ
62 - P1.5 82 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
62 - P1.5 82 - P1.5 TACLK INCLK
67 - P1.0 87 - P1.0 TA0 CCI0A 67 - P1.0 87 - P1.0
66 - P1.1 86 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
65 - P1.2 85 - P1.2 TA1 CCI1A 14 - P1.2 85 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)‡
DVSS GND CCR1 TA1
DVCC VCC
59 - P2.0 79 - P2.0 TA2 CCI2A 15 - P1.3 79 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
‡Not implemented in MSP430x43x1 and MSP430x44x1 devices.
Timer_B3 (MSP430x43x(1) only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_B7 (MSP430x44x(1) only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3/B7 SIGNAL CONNECTIONS†
INPUT PIN NUMBER DEVICE INPUT MODULE INPUT MODULE MODULE
OUTPUT
OUTPUT PIN NUMBER
PN PZ
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
MODULE
BLOCK OUTPUT
SIGNAL PN PZ
63 - P1.4 83 - P1.4 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
63 - P1.4 83 - P1.4 TBCLK INCLK
58 - P2.1 78 - P2.1 TB0 CCI0A 58 - P2.1 78 - P2.1
58 - P2.1 78 - P2.1 TB0 CCI0B
CCR0†
TB0
ADC12 (internal)‡
DVSS GND CCR0†TB0
DVCC VCC
57 - P2.2 77 - P2.2 TB1 CCI1A 57 - P2.2 77 - P2.2
57 - P2.2 77 - P2.2 TB1 CCI1B
CCR1†
TB1
ADC12 (internal)‡
DVSS GND CCR1†TB1
DVCC VCC
56 - P2.3 76 - P2.3 TB2 CCI2A 56 - P2.3 76 - P2.3
56 - P2.3 76 - P2.3 TB2 CCI2B
CCR2†
TB2
DVSS GND CCR2†TB2
DVCC VCC
67 - P3.4 TB3 CCI3A 67 - P3.4
67 - P3.4 TB3 CCI3B
CCR3
TB3
DVSS GND CCR3 TB3
DVCC VCC
66 - P3.5 TB4 CCI4A 66 - P3.5
66 - P3.5 TB4 CCI4B
CCR4
TB4
DVSS GND CCR4 TB4
DVCC VCC
65 - P3.6 TB5 CCI5A 65 - P3.6
65 - P3.6 TB5 CCI5B
CCR5
TB5
DVSS GND CCR5 TB5
DVCC VCC
64 - P3.7 TB6 CCI6A 64 - P3.7
ACLK (internal) CCI6B
CCR6
TB6
DVSS GND CCR6 TB6
DVCC VCC
†Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
‡Not implemented in MSP430x43x1 and MSP430x44x1 devices.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12 (not implemented in MSP430x43x1 and MSP430x44x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD driver
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
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33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B7/ Capture/compare register 6 TBCCR6 019Eh
_
Timer_B3
(see Note 1)
Capture/compare register 5 TBCCR5 019Ch
(see Note 1) Capture/compare register 4 TBCCR4 019Ah
Capture/compare register 3 TBCCR3 0198h
Capture/compare register 2 TBCCR2 0196h
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 6 TBCCTL6 018Eh
Capture/compare control 5 TBCCTL5 018Ch
Capture/compare control 4 TBCCTL4 018Ah
Capture/compare control 3 TBCCTL3 0188h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Reserved 017Eh
_
Reserved 017Ch
Reserved 017Ah
Reserved 0178h
Capture/compare register 2 TACCR2 0176h
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Reserved 016Eh
Reserved 016Ch
Reserved 016Ah
Reserved 0168h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Hardware Sum extend SUMEXT 013Eh
Multiplier
(MSP430x44x(1)
Result high word RESHI 013Ch
(MSP430x44x(1)
onl
y)
Result low word RESLO 013Ah
only)
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
NOTE 1: Timer_B7 in the MSP430x44x(1) family has seven CCRs; Timer_B3 in the MSP430x43x(1) family has three CCRs.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
ADC12 Conversion memory 15 ADC12MEM15 015Eh
(not implemented in
Conversion memory 14 ADC12MEM14 015Ch
MSP430F43x1 and
MSP430F44x1
Conversion memory 13 ADC12MEM13 015Ah
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt-vector-word register ADC12IV 01A8h
Inerrupt-enable register ADC12IE 01A6h
Inerrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
ADC memory-control register15 ADC12MCTL15 08Fh
ADC memory-control register14 ADC12MCTL14 08Eh
ADC memory-control register13 ADC12MCTL13 08Dh
ADC memory-control register12 ADC12MCTL12 08Ch
ADC memory-control register11 ADC12MCTL11 08Bh
ADC memory-control register10 ADC12MCTL10 08Ah
ADC memory-control register9 ADC12MCTL9 089h
ADC memory-control register8 ADC12MCTL8 088h
ADC memory-control register7 ADC12MCTL7 087h
ADC memory-control register6 ADC12MCTL6 086h
ADC memory-control register5 ADC12MCTL5 085h
ADC memory-control register4 ADC12MCTL4 084h
ADC memory-control register3 ADC12MCTL3 083h
ADC memory-control register2 ADC12MCTL2 082h
ADC memory-control register1 ADC12MCTL1 081h
ADC memory-control register0 ADC12MCTL0 080h
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
USART1 Transmit buffer U1TXBUF 07Fh
(MSP430F44x(1)
Receive buffer U1RXBUF 07Eh
only) Baud rate U1BR1 07Dh
Baud rate U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
USART0 Transmit buffer U0TXBUF 077h
Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A Comparator_A port disable CAPD 05Bh
_
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+ Clock FLL+ Control1 FLL_CTL1 054h
FLL+ Control0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter2
BT counter1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special functions SFR module enable2 ME2 005h
p
SFR module enable1 ME1 004h
SFR interrupt flag2 IFG2 003h
SFR interrupt flag1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg: Unprogrammed device −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmed device −55°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage during program execution
VCC (AVCC = DVCC1 = DVCC2 = VCC) (see Note 1)
MSP430F43x(1),
MSP430F44x(1) 1.8 3.6 V
Supply voltage during program execution, SVS enabled, PORON=1
(see Note 1 and Note 2)
VCC (AVCC = DVCC1 = DVCC2 = VCC)
MSP430F43x(1),
MSP430F44x(1) 2 3.6 V
Supply voltage during flash memory programming
VCC (AVCC = DVCC1 = DVCC2 = VCC) (see Note 1)
MSP430F43x(1),
MSP430F44x(1) 2.7 3.6 V
Supply voltage, VSS (AVSS = DVSS1 = DVSS2 = VSS) 0 0 V
Operating free-air temperature range, TA
MSP430x43x(1),
MSP430x44x(1) −40 85 °C
LF selected,
XTS_FLL=0 Watch crystal 32.768 kHz
LFXT1 crystal frequency, f(LFXT1)
(see Note 3)
XT1 selected,
XTS_FLL=1 Ceramic resonator 450 8000 kHz
(see
Note
3)
XT1 selected,
XTS_FLL=1 Crystal 1000 8000 kHz
XT2 crystal frequency f
Ceramic resonator 450 8000
kHz
XT2 crystal frequency, f(XT2) Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f
VCC = 1.8 V DC 4.15
MHz
Processor frequency (signal MCLK), f(System) VCC = 3.6 V DC 8 MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
1.8 3.62.7 3
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
4.15 MHz
8 MHz
Supply Voltage − V
Supply voltage range, ’F43x(1)/’F44x(1),
during flash memory programming
Supply voltage range,
’F43x(1)/’F44x(1), during
program execution
fSystem (MHz)
Figure 1. Frequency vs Supply Voltage, MSP430F43x(1) or MSP430F44x(1)
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
Active mode (see Note 1),
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
2.2 V 280 350
A
I(AM)
f(MCLK)
=
f(SMCLK)
=
1
MHz
,
f(ACLK) = 32768 Hz
XTS_FLL=0, SELM=(0,1)
TA = −40°C to 85°C
3 V 420 560
µA
I
Low-power mode, (LPM0)
2.2 V 32 45
A
I(LPM0)
Low power
mode
,
(LPM0)
(see Note 1 and Note 4) TA = −40°C to 85°C3 V 55 70 µA
I
Low-power mode, (LPM2),
f
(
MCLK
)
= f
(
SMCLK
)
= 0 MHz,
2.2 V 11 14
A
I(LPM2)
f(MCLK)
=
f
(SMCLK)
=
0
MHz
,
f(ACLK) = 32768 Hz, SCG0 = 0
(see Note 2 and Note 4)
TA = −40°C to 85°C
3 V 17 22
µA
TA = −40°C 1 1.5
TA = 25°C
22V
1.1 1.5
A
Low-power mode, (LPM3)
f(MCLK) =f
(SMCLK) = 0 MHz
TA = 60°C2.2 V 2 3 µA
I
f(MCLK) = f(SMCLK) = 0 MHz,
f
(ACLK)
= 32
,
768 Hz
,
SCG0 = 1 TA = 85°C 3.5 6
I(LPM3)
f(ACLK)
=
32
,
768
Hz
,
SCG0
=
1
(see Note 3 and Note 4) TA = −40°C 1.8 2.2
()
TA = 25°C
3V
1.6 1.9
A
TA = 60°C3 V 2.5 3.5 µA
TA = 85°C 4.2 7.5
TA = −40°C 0.1 0.5
TA = 25°C
22V
0.1 0.5
A
Low-power mode (LPM4)
TA = 60°C2.2 V 0.7 1.1 µA
I
L
ow-power mo
d
e,
(LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz, TA = 85°C 1.7 3
I(LPM4)
f(MCLK)
=
0
MHz
,
f(SMCLK)
=
0
MHz
,
f(ACLK) = 0 Hz, SCG0 = 1
( Nt2 dNt4)
TA = −40°C 0.1 0.5
(ACLK)
(see Note 2 and Note 4) TA = 25°C
3V
0.1 0.5
A
TA = 60°C3 V 0.8 1.2 µA
TA = 85°C 1.9 3.5
NOTES: 1. Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM3 is measured with
active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified
in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and OSCCAPx=1h.
4. Current consumption for brownout included.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, P6
PARAMETER VCC MIN TYP MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
VIT+ Positive-going input threshold voltage 3 V 1.5 1.9 V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
VIT− Negative-going input threshold voltage 3 V 0.9 1.3 V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
Vhys Input voltage hysteresis (VIT+ − VIT−)3 V 0.5 1 V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK)
PARAMETER VCC MIN TYP MAX UNIT
VIL Low-level input voltage
VSS VSS+0.6 V
VIH High-level input voltage 2.2 V / 3 V 0.8×VCC VCC V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
P t P1 P2 P1 t P2 t l t i i l
2.2 V/3 V 1.5 cycle
t(int) External interrupt timing Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
2.2 V 62
ns
(int)
pg
for
the
interrupt
flag
,
(see
Note
1)
3 V 50 ns
Timer A Timer B capture
TA0, TA1, TA2 2.2 V 62
t(cap) Timer_A, Timer_B capture
timing TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 2) 3 V 50 ns
f(TAext) Timer_A, Timer_B clock
frequency externally applied
TACLK TBCLK INCLK: t=t
2.2 V 8
MHz
f(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L) 3 V 10
MHz
f(TAint) Timer_A, Timer_B clock
SMCLK or ACLK signal selected
2.2 V 8
MHz
f(TBint)
Timer
_
A,
Timer
_
B
clock
frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x44x(1) and three capture/compare registers in ’x43x(1).
leakage current (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ilkg(P1.x) Port P1 Port 1: V(P1.x) ±50
Ilkg(P2.x) Port P2 Port 2: V(P2.x) ±50
Ilkg(P3.x) Leaka
g
ePort P3 Port 3: V(P3.x)
±50
nA
Ilkg(P4.x)
Leakage
current Port P4 Port 4: V(P4.x)
2.2 V/3 V ±50 nA
Ilkg(P5.x) Port P5 Port 5: V(P5.x) ±50
Ilkg(P6.x) Port P6 Port 6: V(P6.x) ±50
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, P6
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IOH(max) = −1.5 mA (See Note 1) 2.2 V VCC−0.25 VCC
V
High level output voltage
IOH(max) = −6 mA (See Note 2) 2.2 V VCC−0.6 VCC
V
VOH High-level output voltage IOH(max) = −1.5 mA (See Note 1) 3 V VCC−0.25 VCC
V
IOH(max) = −6 mA (See Note 2) 3 V VCC−0.6 VCC
IOL(max) = 1.5 mA (See Note 1) 2.2 V VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA (See Note 2) 2.2 V VSS VSS+0.6
V
VOL Low-level output voltage IOL(max) = 1.5 mA (See Note 1) 3 V VSS VSS+0.25 V
IOL(max) = 6 mA (See Note 2) 3 V VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(1 ≤x≤60≤y≤7)
CL = 20 pF, VCC = 2.2 V DC 5
MHz
f(Px.y) (1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
CL
=
20
pF
,
IL = ±1.5 mA VCC = 3 V DC 7.5 MHz
f(ACLK)
P1.1/TA0/MCLK,
f(MCLK)
P1
.
1/TA0/MCLK
,
P1.5/TACLK/ACLK CL = 20 pF f
(
S
y
stem
)
MHz
f(SMCLK)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
CL
20
pF
f(System)
MHz
P1.5/TACLK/ACLK,
f(ACLK) = f(LFXT1) = f(XT1) 40% 60%
P1
.
5/TACLK/ACLK
,
CL = 20 pF f(ACLK) = f(LFXT1) = f(LF) 30% 70%
CL
20
pF
VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) 50%
P1.1/TA0/MCLK
,
f(MCLK) = f(XT1) 40% 60%
t(Xdc) Duty cycle of output frequency
P1
.
1/TA0/MCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK)
50%−
15 ns 50% 50%+
15 ns
P1.4/TBCLK/SMCLK
,
f(SMCLK) = f(XT2) 40% 60%
P1
.
4/TBCLK/SMCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(SMCLK) = f(DCOCLK)
50%−
15 ns 50% 50%+
15 ns
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
Figure 2
VOL − Low-Level Output Voltage − V
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.7
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.7
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−14
−12
−10
−8
−6
−4
−2
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz 2.2 V/3 V 6µs
td(LPM3)
Delay
time
f = 3 MHz
2.2
V/3
V
6
µs
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(33) Voltage at P5.7/R33 2.5 VCC + 0.2
V(23)
Analog voltage
Voltage at P5.6/R23
V3V
[V(33)−V(03)] × 2/3 + V(03)
V
V(13)
Analog voltage Voltage at P5.5/R13 VCC = 3 V [V(33)−V(03)] × 1/3 + V(03)
V
V(33) − V(03) Voltage at R33 to R03 2.5 VCC + 0.2
I(R03) R03 = VSS No load at all ±20
I(R13) Input leakage P5.5/R13 = VCC/3 segment and
common lines
±20 nA
I(R23)
pg
P5.6/R23 = 2 × VCC/3
common
li
nes,
VCC = 3 V ±20
V(Sxx0) V(03) V(03) − 0.1
V(Sxx1) Se
g
ment line
I=3µA
V=3V
V(13) V(13) − 0.1
V
V(Sxx2)
Segment
line
voltage I(Sxx) = −3 µA, VCC = 3 V V(23) V(23) − 0.1 V
V(Sxx3) V(33) V(33) + 0.1
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
2.2 V 25 40
A
I(CC) CAON=1, CARSEL=0, CAREF=0 3 V 45 60 µA
I
CAON=1, CARSEL=0, CAREF=1/2/3, 2.2 V 30 50
A
I(Refladder/RefDiode)
CAON=1
,
CARSEL=0
,
CAREF=1/2/3
,
No load at P1.6/CA0 and P1.7/CA1 3 V 45 71 µA
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1 2.2 V / 3 V 0.23 0.24 0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1 2.2V / 3 V 0.47 0.48 0.5
V
See Figure 6 and Figure 7
PCA0=1, CARSEL=1, CAREF=3,
No load at P1 6/CA0 and P1 7/CA1;
2.2 V 390 480 540
mV
V(RefVT) See Figure 6 and Figure 7 No load at P1.6/CA0 and P1.7/CA1;
TA = 85°C3 V 400 490 550
mV
VIC
Common-mode input
voltage range CAON=1 2.2 V / 3 V 0 VCC−1 V
Vp−VSOffset voltage See Note 2 2.2 V / 3 V −30 30 mV
Vhys Input hysteresis CAON = 1 2.2 V / 3 V 0 0.7 1.4 mV
TA = 25°C, 2.2 V 160 210 300
ns
t
TA
=
25 C
,
Overdrive 10 mV, without filter: CAF = 0 3 V 80 150 240 ns
t(response LH) TA = 25°C2.2 V 1.4 1.9 3.4
s
TA
=
25 C
Overdrive 10 mV, with filter: CAF = 1 3 V 0.9 1.5 2.6 µs
TA = 25°C2.2 V 130 210 300
ns
t
TA
=
25 C
Overdrive 10 mV, without filter: CAF = 0 3 V 80 150 240 ns
t(response HL) TA = 25°C, 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
,
Overdrive 10 mV, with filter: CAF = 1 3 V 0.9 1.5 2.6 µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Figure 6. V
(
RefVT
)
vs Temperature
VREF − Reference Voltage − mV
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 7. V
(
RefVT
)
vs Temperature
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
VREF − Reference Voltage − mV
_
+
CAON
0
1
V+ 0
1
CAF
Low-Pass Filter
τ ≈ 2 µs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 8. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 9. Overdrive Definition
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 µs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT−) V
V(B_IT−) Brownout dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.71 V
Vhys(B_IT−) (see Note 2) dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV
t(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V 2µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+
settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC(drop)
VCC
3 V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − µst
pw − Pulse Width − µs
VCC = 3 V
VCC(drop) − V
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics (Continued)
VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw − Pulse Width − µs
3 V
0.001 1 1000 tftr
tpw − Pulse Width − µs
tf = tr
Typical Conditions
VCC = 3 V
VCC(drop) − V
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
supply voltage supervisor/monitor (SVS)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 13) 5 150 µs
t(SVSR) dVCC/dt ≤ 30 V/ms 2000 µs
td(SVSon) SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 µs
tsettle VLD ≠ 0‡12 µs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 2 to 14 V(SVS_IT−)
× 0.004
V(SVS_IT−)
× 0.008
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7 VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
V/dt ≤3 V/s (see Figure 13)
VLD = 7 2.46 2.65 2.86
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 8 2.58 2.8 3
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt ≤ 3 V/s (see Figure 13),
external voltage applied on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 3) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 µA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 3: The current consumption of the SVS module is not included in the ICC current consumption data.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V(SVS_IT−)
Software Sets VLD>0:
SVS is Active
td(SVSR)
undefined
Vhys(SVS_IT−)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
Out
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVSOut
Vhys(B_IT−)
Figure 13. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns 1 ns
VCC(drop)
tpw
tpw − Pulse Width − µs
VCC(drop)− V
3 V
1 10 1000
tftr
t − Pulse Width − µs
100
tpw
3 V
tf = tr
Rectangular Drop
Triangular Drop
VCC(drop)
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(DCOCLK)
N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
fCrystal = 32.768 kHz VCC = 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS 1
VCC = 2.2 V 0.3 0.65 1.25
MHz
f(DCO=2) FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1 VCC = 3 V 0.3 0.7 1.3 MHz
f
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS 1
VCC = 2.2 V 2.5 5.6 10.5
MHz
f(DCO=27) FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1 VCC = 3 V 2.7 6.1 11.3 MHz
f
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 VCC = 2.2 V 0.7 1.3 2.3
MHz
f(DCO=2)
FN
_
8=FN
_
4=FN
_
3=0
,
FN
_
2=1;
DCOPLUS
=
1
VCC = 3 V 0.8 1.5 2.5 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
VCC = 2.2 V 5.7 10.8 18
MHz
f(DCO=27) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 VCC = 3 V 6.5 12.1 20 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
VCC = 2.2 V 1.2 2 3
MHz
f(DCO=2) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 VCC = 3 V 1.3 2.2 3.5 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
VCC = 2.2 V 9 15.5 25
MHz
f(DCO=27) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 VCC = 3 V 10.3 17.9 28.5 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
VCC = 2.2 V 1.8 2.8 4.2
MHz
f(DCO=2) FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1 VCC = 3 V 2.1 3.4 5.2 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
VCC = 2.2 V 13.5 21.5 33
MHz
f(DCO=27) FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1 VCC = 3 V 16 26.6 41 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
VCC = 2.2 V 2.8 4.2 6.2
MHz
f(DCO=2) FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1 VCC = 3 V 4.2 6.3 9.2 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
VCC = 2.2 V 21 32 46
MHz
f(DCO=27) FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1 VCC = 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11
Sn
Step
size
between
adjacent
DCO
taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 16 for taps 21 to 27) TAP = 27 1.07 1.17
D
t
Temperature drift, N
(
D
CO)
= 01Eh, FN_8=FN_4=FN_3=FN_2=0 VCC = 2.2 V –0.2 –0.3 –0.4
%/_C
Dt
Temperature
drift
,
N(DCO)
=
01Eh
,
FN
_
8=FN
_
4=FN
_
3=FN
_
2=0
D = 2; DCOPLUS = 0 VCC = 3 V –0.2 –0.3 –0.4 %/_C
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8=FN_4=FN_3=FN_2=0, D= 2; DCOPLUS = 0 VCC = 2.2 V/3 V 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 16. DCO Tap Step Size
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
DCO Frequency
Adjusted by Bits
29 to 2 5 in SCFI1 {N (DCO)}
Overlapping DCO Ranges:
uninterrupted frequency range
f(DCO)
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OSCCAPx = 0h 2.2 V / 3 V 0
C
XIN
Inte
g
rated in
p
ut ca
p
acitance OSCCAPx = 1h 2.2 V/3 V 10
p
F
CXIN
Integrated
input
capacitance
OSCCAPx = 2h 2.2 V/3 V 14
pF
OSCCAPx = 3h 2.2 V/3 V 18
OSCCAPx = 0h 2.2 V/3 V 0
C
Integrated output capacitance
OSCCAPx = 1h 2.2 V/3 V 10
pF
CXOUT Integrated output capacitance OSCCAPx = 2h 2.2 V/3 V 14 pF
OSCCAPx = 3h 2.2 V/3 V 18
VIL
Input levels at XIN
See Note 3
2 2 V/3 V
VSS 0.2 × VCC V
VIH
Input levels at XIN See Note 3 2.2 V/3 V 0.8 × VCC VCC V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN xC
XOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep the trace between the ’F43x(1)/44x(1) and the crystal as short as possible.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
CXT2IN Integrated input capacitance VCC = 2.2 V/3 V 2 pF
CXT2OUT Integrated output capacitance VCC = 2.2 V/3 V 2 pF
VIL
Input levels at XT2IN
V= 2 2 V/3 V (see Note 2)
VSS 0.2 × VCC V
VIH
Input levels at XT2IN VCC = 2.2 V/3 V (see Note 2) 0.8 × VCC VCC V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
USART0/1: deglitch time
VCC = 2.2 V, SYNC = 0, UART mode 200 430 800
ns
t(τ)USART0/1: deglitch time VCC = 3 V, SYNC = 0, UART mode 150 280 500 ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
AVCC Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
2.2 3.6 V
V(P6.x/Ax)
Analog input voltage
range (see Note 2)
All P6.0/A0 to P6.7/A7 terminals.
Analog inputs selected in ADC12MCTLx register
and P6Sel.x=1,
0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
0 VAVCC V
I
Operating supply current
into AV terminal
fADC12CLK = 5.0 MHz
ADC12ON 1 REFON 0
2.2 V 0.65 1.3
mA
IADC12 into AVCC terminal
(see Note 3)
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0 3 V 0.8 1.6
mA
I
Operating supply current
it AV til
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
3 V 0.5 0.8 mA
IREF+ into AVCC terminal
(see Note 4) fADC12CLK = 5.0 MHz
ADC12ON 0
2.2 V 0.5 0.8
mA
(see
Note
4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0 3 V 0.5 0.8
mA
CIInput capacitance Only one terminal can be selected at one time,
P6.x/Ax 2.2 V 40 pF
RIInput MUX ON resistance 0V ≤ VAx ≤ VAVCC 3 V 2000 Ω
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
VeREF+
Positive external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 2) 1.4 VAVCC V
VREF− /VeREF−
Negative external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 3) 0 1.2 V
(VeREF+ −
VREF−/VeREF−)
Differential external
reference voltage input VeREF+ > VREF−/VeREF− (see Note 4) 1.4 VAVCC V
IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC 2.2 V/3 V ±1µA
IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC 2.2 V/3 V ±1µA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
Positive built-in reference volta
g
e
REF2_5V = 1 for 2.5 V
IVREF+ ≤ I
VREF+max 3 V 2.4 2.5 2.6
V
VREF+
Positive
built in
reference
voltage
output REF2_5V = 0 for 1.5 V
IVREF+ ≤ I
VREF+max 2.2 V/3 V 1.44 1.5 1.56
V
AV i i lt P iti
REF2_5V = 0, IVREF+ ≤ 1mA 2.2
AVCC
(
min
)
AVCC minimum voltage, Positive
built
-
in reference active
REF2_5V = 1, IVREF+ ≤ 0.5mA VREF+ + 0.15 V
AVCC(min)
b
u
ilt
-
i
n re
f
erence ac
ti
ve
REF2_5V = 1, IVREF+ ≤ 1mA VREF+ + 0.15
V
I
Load current out of V terminal
2.2 V 0.01 −0.5
mA
IVREF+ Load current out of VREF+ terminal 3 V −1 mA
IVREF+ = 500 µA +/− 100 µA
Analog input voltage 0 75 V;
2.2 V ±2
LSB
I
Load-current re
g
ulation VREF+
Analog input voltage ~0.75 V;
REF2_5V = 0 3 V ±2
LSB
IL(VREF)+
Load current
regulation
VREF
+
terminal IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
3 V ±2 LSB
I
Load current re
g
ulation VREF+ IVREF+ =100 µA → 900 µA,
C 5 µF Ax 05xV
3V
20
ns
IDL(VREF) +
Load
current
regulation
VREF
+
terminal CVREF+=5 µF, Ax ~0.5 x VREF+
Error of conversion result ≤ 1 LSB
3 V 20 ns
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤IVREF+max 2.2 V/3 V 5 10 µF
TREF+
Temperature coefficient of built-in
reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA 2.2 V/3 V ±100 ppm/°C
tREFON
Settle time of internal reference
voltage (see Figure 18 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10µF,
VREF+ = 1.5 V 2.2 V 17 ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1 µF
0
1 ms 10 ms 100 ms tREFON
tREFON ≈.66 x CVREF+ [ms] with CVREF+ in µF
100 µF
10 µF
Figure 18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+
−
10 µF 100 nF
AVSS
MSP430F43x
MSP430F44x
+
−
+
−
10 µF 100 nF
10 µF 100 nF
AVCC
10 µF 100 nF
DVSS1
DVCC1
From
Power
Supply
Apply
External
Reference
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
/DVCC2
/DVSS2
Figure 19. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
+
−
10 µF 100 nF
AVSS
MSP430F43x
MSP430F44x
+
−
10 µF 100 nF
AVCC
10 µF 100 nF
From
Power
Supply
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Reference Is Internally
Switched to AVSS
DVSS1
DVCC1/DVCC2
/DVSS2
Figure 20. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC12CLK
For specified performance of ADC12
linearity parameters 2.2V/3 V 0.45 5 6.3 MHz
fADC12OSC
Internal ADC12
oscillator
ADC12DIV=0,
fADC12CLK=fADC12OSC 2.2 V/ 3 V 3.7 6.3 MHz
t
Conversion time
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz 2.2 V/ 3 V 2.06 3.51 µs
tCONVERT Conversion time External fADC12CLK from ACLK, MCLK
or SMCLK: ADC12SSEL ≠ 0
13×ADC12DIV×
1/fADC12CLK µs
tADC12ON
Turn on settling time of
the ADC See Note 1 100 ns
t
Sampling time
RS = 400 Ω, RI = 1000 Ω,
C30 pF
3 V 1220
ns
tSample Sampling time CI = 30 pF
τ = [RS + RI] x CI;(see Note 2) 2.2 V 1400
ns
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
E
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V
2 2 V/3 V
±2
LSB
EIIntegral linearity error 1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [V(AVCC)]2.2 V/3 V ±1.7 LSB
ED
Differential linearity
error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1 LSB
EOOffset error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V/3 V ±2±4 LSB
EGGain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±1.1 ±2 LSB
ETTotal unadjusted
error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 2.2 V/3 V ±2±5 LSB
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
Operatin
g
suppl
y
current into REFON = 0, INCH = 0Ah, 2.2 V 40 120
A
ISENSOR
Operating
supply
current
into
AVCC terminal (see Note 1)
REFON
=
0
,
INCH
=
0Ah
,
ADC12ON=NA, TA = 25_C3 V 60 160 µA
V
ADC12ON = 1, INCH = 0Ah, 2.2 V 986 986±5%
mV
VSENSOR
ADC12ON
=
1
,
INCH
=
0Ah
,
TA = 0°C3 V 986 986±5% mV
TC
ADC12ON 1 INCH 0Ah
2.2 V 3.55 3.55±3%
mV/°C
TCSENSOR ADC12ON = 1, INCH = 0Ah 3 V 3.55 3.55±3% mV/°C
t
Sample time required if channel ADC12ON = 1, INCH = 0Ah, 2.2 V 30
s
tSENSOR(sample)
Sample
time
required
if
channel
10 is selected (see Note 2)
ADC12ON
=
1
,
INCH
=
0Ah
,
Error of conversion result ≤1 LSB 3 V 30 µs
I
Current into divider at channel 11
ADC12ON = 1, INCH = 0Bh, 2.2 V NA
A
IVMID Current into divider at channel 11
ADC12ON
=
1
,
INCH
=
0Bh
,
(see Note 3) 3 V NA µA
V
AV divider at channel 11
ADC12ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04
V
VMID AVCC divider at channel 11
ADC12ON
=
1
,
INCH
=
0Bh
,
VMID is ~0.5 x VAVCC 3 V 1.5 1.50±0.04 V
t
Sample time required if channel ADC12ON = 1, INCH = 0Bh, 2.2 V 1400
ns
tVMID(sample)
Sample
time
required
if
channel
11 is selected (see Note 4)
ADC12ON
=
1
,
INCH
=
0Bh
,
Error of conversion result ≤ 1 LSB 3 V 1220 ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). Therefore it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
3. No additional current is needed. The VMID is used during sampling.
4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
flash memory
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and Erase supply voltage 2.7 3.6 V
fFTG Flash Timing Generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA
tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 10 ms
tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 35
tBlock, 0Block program time for 1st byte or word 30
tBlock, 1-63 Block program time for each additional byte or word
see Note 3
21
t
tBlock, End Block program end-sequence wait time see Note 3 6tFTG
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pullup resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS MIN TYP MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
port P1, P1.0 to P1.5, input/output with Schmitt trigger
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x
P1.x
EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
Keeper
CAPD.x
Note: 0< x< 5
Note: Port function is active if CAPD.x = 0
PnSel.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
P1Sel.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1Sel.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2
P1Sel.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3
P1Sel.4 P1DIR.4 P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4
P1Sel.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5
P1Sel.0 P1DIR.0 P1OUT.0 P1IN.0 P1IE.0 P1IFG.0 P1IES.0
SVSOUT
Out0 sig.
Out1 sig.
CCI0A
CCI1A
TBOUTH
TBCLK
TACLK
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.0
SMCLK
ACLK
MCLK
Module X IN
P1IN.x
P1.5/TACLK/ACLK
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
CCI0B
†
†
†
†
†
†
Control
‡
‡
†Timer_A
‡Timer_B
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P1, P1.6, P1.7, input/output with Schmitt trigger
P1OUT.7
P1DIR.7
P1SEL.7
D
EN
Interrupt
Edge
Select
P1IES.7 P1SEL.7
P1IE.7
P1IFG.7
P1IRQ.07 EN
Set
Q
0
1
1
0
CAPD.7
P1OUT.6
P1DIR.6
P1SEL.6
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.7
P1IFG.7
P1IRQ.07
P1.6/
CA0
EN
Set
Q
0
1
1
0
CAPD.6
Note: Port function is active if CAPD.6 = 0
P1IN.6
unused
P1.7/
CA1
Comparator_A
Reference Block
CCI1B
CAF
CAREF
P2CA
CAEX
CAREF
to Timer_Ax −
+
2
AVcc
CA0
CA1
Pad Logic
0: Input
1: Output
Bus
Keeper
Pad Logic
0: input
1: output
Bus
keeper
P1DIR.6
P1DIR.7
P1IN.7
unused
Note: Port function is active if CAPD.7 = 0
DVSS
DVSS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
P2Sel.4 P2DIR.4 P2OUT.4 P2IN.4 P2IE.4 P2IFG.4 P2IES.4
P2Sel.5 P2DIR.5 P2OUT.5 P2IN.5 P2IE.5 P2IFG.5 P2IES.5
P2Sel.0 P2DIR.0 P2OUT.0 P2IN.0 P2IE.0 P2IFG.0 P2IES.0
Out2 sig. CCI2AP2DIR.0
UTXD0
DVSS
P2.5/URXD0
P2.0/TA2
P2.4/UTXD0
Module X IN
P2IN.x
x {0,4,5}Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
URXD0
unused
DVSS
†Timer_A
‡USART0
†
‡
†
‡
DVCC
DVSS DVSS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P2, P2.1 to P2.3, input/output with Schmitt trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
P2Sel.1 P2DIR.1 P2OUT.1 P2IN.1 P2IE.1 P2IFG.1 P2IES.1
P2Sel.2 P2DIR.2 P2OUT.2 P2IN.2 P2IE.2 P2IFG.2 P2IES.2
P2Sel.3 P2DIR.3 P2OUT.3 P2IN.3 P2IE.3 P2IFG.3 P2IES.3
P2DIR.1
P2DIR.2
P2.1/TB0
P2.2/TB1
P2.3/TB2
Out0 sig.
Module X IN
P2IN.x
1< x< 3Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P2DIR.3 Out2 sig.
Out1 sig.
CCI0A
CCI0B
CCI1A
CCI1B
CCI2A
CCI2B
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1SEL.3
P1DIR.3
†Timer_B
†
†
†
†
†
†
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P2, P2.6 to P2.7, input/output with Schmitt trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
0: Port active
1: Segment xx function active
P2Sel.6 P2DIR.6
P2Sel.7 P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
P2IN.6
P2IN.7 unused
CAOUT
ADC12CLK
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
Module X IN
P2IN.x
6< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
unused
Port/LCD
0: LCDM<40h
0: LCDM<40h
Port/LCD‡
Segment xx‡
P2.6/CAOUT/S19‡
P2.7/ADC12CLK/S18‡
‡Segment function
only available with
MSP430x43x(1)IPN
‡
‡
‡
†
§
† Comparator_A
‡Port/LCD signal is 1 only with MSP430xIPN and LCDM ≥40h.
§ ADC12
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P3, P3.0 to P3.3, input/output with Schmitt trigger
P3OUT.x
Module X OUT
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P3Sel.1 P3DIR.1 P3OUT.1 P3IN.1
P3Sel.2 P3DIR.2 P3OUT.2 P3IN.2
P3Sel.3 P3DIR.3 P3OUT.3 P3IN.3
P3Sel.0 P3DIR.0 P3OUT.0 P3IN.0
UCLK0(out)
SOMIO(out)
DCM_SIMO0
DCM_SOMI0
DCM_UCLK0
Segment xx
0: Port active
1: Segment xx function active
SIMO0(out)
UCLK0(in)
SOMI0(in)
SIMO0(in)
STE0(in)
Module X IN
P3IN.x
Pad Logic
0: Input
1: Output
Bus
Keeper
LCDM.5
LCDM.6
LCDM.7
Direction
From Module
Control
DVSS
DVSS
x43xIPZ and x44xIPZ have no segment
P3.0/STEO/S31†
P3.1/SIMO0/S30†
P3.2/SOMI0/S29†
P3.3/UCLK0/S28†
function on Port P3: Both lines are low.
Note: 0 ≤ x ≤ 3
MSP430x43x(1)IPN (80-Pin) Only
†S24 to S31 shared with port function only at MSP430x43x(1)IPN (80-pin QFP)
SYNC
MM
STC
STE
SYNC
MM
STC
STE
DCM_SOMI0
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
Direction Control for SIMO0 and UCLK0
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P3, P3.4 to P3.7, input/output with Schmitt trigger
P3OUT.x
Module XOUT
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P3Sel.4 P3DIR.4 P3OUT.4 P3IN.4
P3Sel.5 P3DIR.5 P3OUT.5 P3IN.5
P3DIR.4
0: Port active
1: Segment xx function active
P3Sel.6 P3DIR.6
P3Sel.7 P3DIR.7
P3OUT.6
P3OUT.7
P3IN.6
P3IN.7 unused
CCI6A
unused
CCI5A/B
unused
CCI4A/B
unused
CCI3A/B
Module X IN
P3IN.x
4< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P3.4/S27
P3.5/S26
P3.6/S25
P3.7/S24
P3.4
P3.5
P3.6
P3.7
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P3DIR.5
P3DIR.6
P3DIR.7
DVSS
OUT3
DVSS
OUT4
DVSS
OUT5
DVSS
OUT6
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1SEL.3
’x43x(1)IPN ’x43x(1)IPZ ’x44x(1)
P3SEL.x
TBOUTHiZ
P1DIR.3
P3DIR.x
LCDM.7† or DVSS‡
Segmentxx† or DVSS‡
TBOUTHiZ# or DVSS§
† MSP430x43x(1)IPN
‡ MSP430x43x(1)IPZ, MSP430x44x(1)IPZ
§ MSP430x43x(1)
# MSP430x44x(1)
§
#
§
#
§
#
§
#
§
#
§
#
§
#
§
#
80-Pin 100-Pin
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P4Sel.1 P4DIR.1 P4OUT.1 P4IN.1
P4Sel.2 P4DIR.2 P4OUT.2 P4IN.2
P4Sel.3 P4DIR.3 P4OUT.3 P4IN.3
P4Sel.4 P4DIR.4 P4OUT.4 P4IN.4
P4Sel.5 P4DIR.5 P4OUT.5 P4IN.5
P4Sel.0 P4DIR.0 P4OUT.0 P4IN.0
Segment xx
0: Port active
1: Segment xx function active
P4Sel.6 P4DIR.6
P4Sel.7 P4DIR.7
P4DIR.6
P4DIR.7
P4OUT.6
P4OUT.7
P4IN.6
P4IN.7 unused
unused
unused
Module X IN
P4IN.x
0< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
Direction
From Module
Control
DVSS†
UTXD1‡
DVSS
DVSS
DVSS
DVSS
Port/LCD§
x43x(1)IPN
80-Pin
QFP:
P4.7/S2
P4.6/S3
P4.5/S4
P4.3/S6
P4.4/S5
P4.2/S7
P4.1/S8
P4.0/S9
x43x(1)IPZ
100-Pin
QFP:
P4.7/S34
P4.6/S35
P4.5/S36
P4.3/S37
P4.4/S38
P4.2/S39
P4.0
P4.1
x44x(1)
P4.7/S34
P4.6/S35
P4.5/UCLK1/S36
P4.4/SMO1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
P4.1/URXD1
P4.0/UTXD1
P4DIR.0†
DVCC‡
P4DIR.1†
DVSS‡
P4DIR.2†
DVSS‡
P4DIR3.†
DCM_SIMO1‡
P4DIR4.†
DCM_SOMI1‡
P4DIR5.†
DCM_UCLK1‡
DVSS†
SIMO1(out)‡
DVSS†
SOMI1(out)‡
DVSS†
UCLK1(out)‡
unused†
URXD1‡
unused†
STE1(in)‡
unused†
SIMO1(in)‡
unused
SOMI1(in)‡
unused†
UCLK1(in)‡
†Signal at MSP430x43x(1)
‡Signal at MSP430x44x(1)
DEVICE PORT BITS PORT FUNCTION LCD SEG. FUNCTION
x43x(1)IPN 80-pin QFP P4.0 . . .P4.7 LCDM < 020h LCDM ≥ 020h
x43x(1)IPZ 100-pin QFP P4.2 . . .P4.5 LCDM < 0E0h LCDM ≥ 0E0h
x44x(1)IPZ 100-pin QFP P4.6 . . .P4.7 LCDM < 0C0h LCDM ≥ 0C0h
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger (continued)
SYNC
MM
STC
STE
SYNC
MM
STC
STE
DCM_SOMI1
DCM_SIMO1
DCM_UCLK1
Direction Control for SIMO1 and UCLK1 Direction Control for SOMI1
port P5, P5.0 to P5.1, input/output with Schmitt trigger
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P5Sel.1 P5DIR.1 P5OUT.1 P5IN.1
P5Sel.0 P5DIR.0 P5OUT.0 P5IN.0
P5DIR.1
P5DIR.0
Segment
0: Port active
1: Segment function active
Segment
unused
unused
Module X IN
P5IN.x
0< x< 1Note:
Port Pad Logic
0: Input
1: Output
Bus
Keeper
Segment Pad Logic
Port/LCD
Port/LCD
P5.0/S1
P5.1/S0
S1
S0
0: LCDM<20h
0: LCDM<20h
DVSS
DVSS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P5, P5.2 to P5.4, input/output with Schmitt trigger
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P5Sel.2 P5DIR.2 P5OUT.2 P5IN.2
P5Sel.3 P5DIR.3 P5OUT.3 P5IN.3
P5Sel.4 P5DIR.4 P5OUT.4 P5IN.4
LCD signal
0: Port active
1: LCD function active
LCD signal
unused
unused
unused
Module X IN
P5IN.x
2< x< 4Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P5DIR.3
P5DIR.2
P5DIR.4
Port/LCD
Port/LCD
P5.2/COM1
P5.3/COM2
P5.4/COM3
COM1
COM2
COM3
P5SEL.2
P5SEL.3
P5SEL.4
DVSS
DVSS
DVSS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P5, P5.5 to P5.7, input/output with Schmitt trigger
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P5Sel.5 P5DIR.5 P5OUT.5 P5IN.5
P5Sel.6 P5DIR.6 P5OUT.6 P5IN.6
P5Sel.7 P5DIR.7 P5OUT.7 P5IN.7
LCD signal
0: Port active
1: LCD function active
LCD signal
unused
unused
unused
Module X IN
P5IN.x
5< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P5DIR.6
P5DIR.5
P5DIR.7
Port/LCD
Port/LCD
R13 P5SEL.5
P5.5/R13
P5.6/R23
P5.7/R33
R23
R33
P5SEL.6
P5SEL.7
DVSS
DVSS
DVSS
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P6, P6.0 to P6.6, input/output with Schmitt trigger
P6.6/A6
P6IN.x
Module X IN
Pad Logic
EN
D
P6OUT.x
P6DIR.x
P6SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
Bus Keeper
To ADC
From ADC
0: Input
1: Output
x: Bit Identifier, 0 to 6 for Port P6
P6.0/A0 ..
Note: Not implemented in the MSP430x43x1 and MSP430x44x1 devices
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused
P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused
P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused
P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused
P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused
P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused
P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 DVSS P6IN.6 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P6, P6.7, input/output with Schmitt trigger
P6.7/A7/SVSIN
P6IN.x
Module X IN
Pad Logic
EN
D
P6OUT.x
P6DIR.x
P6SEL.x
Module X OUT
Direction Control
From Module
0
1
0
1
Bus Keeper
To ADC
From ADC
0: Input
1: Output
x: Bit Identifier, 7 for Port P6
To Brownout/SVS Module
VLP(SVS)=15
Note: Not implemented in the MSP430x43x1 and MSP430x44x1 devices
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
RST/NMI
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 21. Fuse Check Mode Current MSP430x43x(1), MSP430x44x(1)
MSP430x43x1, MSP430x43x, MSP430x44x1, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344G − JANUARY 2002 − REVISED OCTOBER 2009
72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS344E
Added MSP430F43x1 devices
Updated functional block diagram (page 6)
Clarified test conditions in recommended operating conditions table (page 27)
Clarified test conditions in electrical characteristics table (page 28)
Added Port 2 through Port 5 to leakage current table (page 29)
Corrected y-axis unit on Figures 6 and 7; changed from V to mV (page 34)
Clarified test conditions in USART0/USART1 table (page 40)
Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 46)
SLAS344F Added MSP430F43x1 devices in PZ (100 pin) package
SLAS344G Added MSP430F44x1 devices
NOTE: Page and figure numbers refer to the respective document revision.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MSP430F4351IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4351IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4351IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4351IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F435IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F435IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F435IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F435IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4361IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4361IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4361IPNRKAM ACTIVE LQFP PN 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4361IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4361IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F436IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F436IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F436IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F436IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4371IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4371IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4371IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4371IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F437IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F437IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F437IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F437IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 2-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MSP430F447IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F447IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4481IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4481IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F448IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F448IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4491IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4491IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F449IPZ ACTIVE LQFP PZ 100 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F449IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F447IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F4481IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F448IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F4491IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F449IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F447IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F4481IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F448IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F4491IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F449IPZR LQFP PZ 100 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
4040135 /B 1 1/96
0,17
0,27
0,13 NOM
40
21
0,25
0,45
0,75
0,05 MIN
Seating Plane
Gage Plane
41
60
61
80
20
SQ
SQ
1
13,80
14,20
12,20
9,50 TYP
11,80
1,45
1,35
1,60 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
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